Revision e034e2c3 target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
|---|---|---|
| 71 | 71 |
int32_t CCRes; |
| 72 | 72 |
int32_t Status_rw_bitmask; |
| 73 | 73 |
int32_t CP1_fcr0; |
| 74 |
int32_t SEGBITS; |
|
| 74 | 75 |
}; |
| 75 | 76 |
|
| 76 | 77 |
/*****************************************************************************/ |
| ... | ... | |
| 87 | 88 |
.SYNCI_Step = 32, |
| 88 | 89 |
.CCRes = 2, |
| 89 | 90 |
.Status_rw_bitmask = 0x3278FF17, |
| 91 |
.SEGBITS = 32, |
|
| 90 | 92 |
}, |
| 91 | 93 |
{
|
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.name = "4KEcR1", |
| ... | ... | |
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.SYNCI_Step = 32, |
| 99 | 101 |
.CCRes = 2, |
| 100 | 102 |
.Status_rw_bitmask = 0x3278FF17, |
| 103 |
.SEGBITS = 32, |
|
| 101 | 104 |
}, |
| 102 | 105 |
{
|
| 103 | 106 |
.name = "4KEc", |
| ... | ... | |
| 109 | 112 |
.SYNCI_Step = 32, |
| 110 | 113 |
.CCRes = 2, |
| 111 | 114 |
.Status_rw_bitmask = 0x3278FF17, |
| 115 |
.SEGBITS = 32, |
|
| 112 | 116 |
}, |
| 113 | 117 |
{
|
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.name = "24Kc", |
| ... | ... | |
| 120 | 124 |
.SYNCI_Step = 32, |
| 121 | 125 |
.CCRes = 2, |
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.Status_rw_bitmask = 0x3278FF17, |
| 127 |
.SEGBITS = 32, |
|
| 123 | 128 |
}, |
| 124 | 129 |
{
|
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.name = "24Kf", |
| ... | ... | |
| 133 | 138 |
.Status_rw_bitmask = 0x3678FF17, |
| 134 | 139 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 135 | 140 |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
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.SEGBITS = 32, |
|
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}, |
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#ifdef TARGET_MIPS64 |
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{
|
| ... | ... | |
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.Status_rw_bitmask = 0x3678FFFF, |
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/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */ |
| 149 | 155 |
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 156 |
.SEGBITS = 40, |
|
| 150 | 157 |
}, |
| 151 | 158 |
{
|
| 152 | 159 |
.name = "5Kc", |
| ... | ... | |
| 161 | 168 |
.SYNCI_Step = 32, |
| 162 | 169 |
.CCRes = 2, |
| 163 | 170 |
.Status_rw_bitmask = 0x32F8FFFF, |
| 171 |
.SEGBITS = 42, |
|
| 164 | 172 |
}, |
| 165 | 173 |
{
|
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.name = "5Kf", |
| ... | ... | |
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/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
| 179 | 187 |
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
| 180 | 188 |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 189 |
.SEGBITS = 42, |
|
| 181 | 190 |
}, |
| 182 | 191 |
{
|
| 183 | 192 |
.name = "20Kc", |
| ... | ... | |
| 198 | 207 |
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 199 | 208 |
(1 << FCR0_D) | (1 << FCR0_S) | |
| 200 | 209 |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 210 |
.SEGBITS = 40, |
|
| 201 | 211 |
}, |
| 202 | 212 |
#endif |
| 203 | 213 |
}; |
| ... | ... | |
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env->CCRes = def->CCRes; |
| 275 | 285 |
env->Status_rw_bitmask = def->Status_rw_bitmask; |
| 276 | 286 |
env->fcr0 = def->CP1_fcr0; |
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#ifdef TARGET_MIPS64 |
|
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env->SEGBITS = def->SEGBITS; |
|
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env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1); |
|
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#endif |
|
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#ifdef CONFIG_USER_ONLY |
| 278 | 292 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
| 279 | 293 |
env->hflags |= MIPS_HFLAG_FPU; |
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