root / target-mips / helper.c @ e034e2c3
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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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enum {
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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}; |
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/* no MMU emulation */
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int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{ |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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return TLBRET_MATCH;
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} |
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|
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/* fixed mapping MMU emulation */
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int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{ |
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if (address <= (int32_t)0x7FFFFFFFUL) { |
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if (!(env->CP0_Status & (1 << CP0St_ERL))) |
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*physical = address + 0x40000000UL;
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else
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*physical = address; |
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} else if (address <= (int32_t)0xBFFFFFFFUL) |
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*physical = address & 0x1FFFFFFF;
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else
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*physical = address; |
61 |
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*prot = PAGE_READ | PAGE_WRITE; |
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return TLBRET_MATCH;
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} |
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|
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{ |
70 |
uint8_t ASID = env->CP0_EntryHi & 0xFF;
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int i;
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|
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for (i = 0; i < env->tlb_in_use; i++) { |
74 |
r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i]; |
75 |
/* 1k pages are not supported. */
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target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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target_ulong tag = address & ~mask; |
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target_ulong VPN = tlb->VPN & ~mask; |
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#ifdef TARGET_MIPS64
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tag &= env->SEGMask; |
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#endif
|
82 |
|
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
85 |
/* TLB match */
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int n = !!(address & mask & ~(mask >> 1)); |
87 |
/* Check access rights */
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if (!(n ? tlb->V1 : tlb->V0))
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return TLBRET_INVALID;
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if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
91 |
*physical = tlb->PFN[n] | (address & (mask >> 1));
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*prot = PAGE_READ; |
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if (n ? tlb->D1 : tlb->D0)
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*prot |= PAGE_WRITE; |
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return TLBRET_MATCH;
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} |
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return TLBRET_DIRTY;
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} |
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} |
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return TLBRET_NOMATCH;
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} |
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static int get_physical_address (CPUState *env, target_ulong *physical, |
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int *prot, target_ulong address,
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int rw, int access_type) |
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{ |
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/* User mode can only access useg/xuseg */
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
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#endif
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int ret = TLBRET_MATCH;
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#if 0
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if (logfile) {
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fprintf(logfile, "user mode %d h %08x\n",
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user_mode, env->hflags);
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}
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#endif
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#ifdef TARGET_MIPS64
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if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL) |
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return TLBRET_BADADDR;
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#else
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if (user_mode && address > 0x7FFFFFFFUL) |
128 |
return TLBRET_BADADDR;
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#endif
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|
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if (address <= (int32_t)0x7FFFFFFFUL) { |
132 |
/* useg */
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if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) { |
134 |
ret = env->map_address(env, physical, prot, address, rw, access_type); |
135 |
} else {
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*physical = address & 0xFFFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE; |
138 |
} |
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#ifdef TARGET_MIPS64
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/*
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XXX: Assuming :
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- PABITS = 36 (correct for MIPS64R1)
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*/
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} else if (address < 0x3FFFFFFFFFFFFFFFULL) { |
145 |
/* xuseg */
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if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
147 |
ret = env->map_address(env, physical, prot, address, rw, access_type); |
148 |
} else {
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ret = TLBRET_BADADDR; |
150 |
} |
151 |
} else if (address < 0x7FFFFFFFFFFFFFFFULL) { |
152 |
/* xsseg */
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if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
154 |
ret = env->map_address(env, physical, prot, address, rw, access_type); |
155 |
} else {
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ret = TLBRET_BADADDR; |
157 |
} |
158 |
} else if (address < 0xBFFFFFFFFFFFFFFFULL) { |
159 |
/* xkphys */
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160 |
/* XXX: check supervisor mode */
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if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL) |
162 |
{ |
163 |
*physical = address & 0X0000000FFFFFFFFFULL;
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*prot = PAGE_READ | PAGE_WRITE; |
165 |
} else {
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ret = TLBRET_BADADDR; |
167 |
} |
168 |
} else if (address < 0xFFFFFFFF7FFFFFFFULL) { |
169 |
/* xkseg */
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170 |
/* XXX: check supervisor mode */
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if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { |
172 |
ret = env->map_address(env, physical, prot, address, rw, access_type); |
173 |
} else {
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ret = TLBRET_BADADDR; |
175 |
} |
176 |
#endif
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} else if (address < (int32_t)0xA0000000UL) { |
178 |
/* kseg0 */
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179 |
/* XXX: check supervisor mode */
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*physical = address - (int32_t)0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
182 |
} else if (address < (int32_t)0xC0000000UL) { |
183 |
/* kseg1 */
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184 |
/* XXX: check supervisor mode */
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*physical = address - (int32_t)0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
187 |
} else if (address < (int32_t)0xE0000000UL) { |
188 |
/* kseg2 */
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ret = env->map_address(env, physical, prot, address, rw, access_type); |
190 |
} else {
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191 |
/* kseg3 */
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192 |
/* XXX: check supervisor mode */
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/* XXX: debug segment is not emulated */
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ret = env->map_address(env, physical, prot, address, rw, access_type); |
195 |
} |
196 |
#if 0
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if (logfile) {
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fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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}
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#endif
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202 |
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return ret;
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} |
205 |
|
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#if defined(CONFIG_USER_ONLY)
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
208 |
{ |
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return addr;
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} |
211 |
#else
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
213 |
{ |
214 |
target_ulong phys_addr; |
215 |
int prot;
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216 |
|
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
218 |
return -1; |
219 |
return phys_addr;
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} |
221 |
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222 |
void cpu_mips_init_mmu (CPUState *env)
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{ |
224 |
} |
225 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
226 |
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227 |
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
228 |
int is_user, int is_softmmu) |
229 |
{ |
230 |
target_ulong physical; |
231 |
int prot;
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232 |
int exception = 0, error_code = 0; |
233 |
int access_type;
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234 |
int ret = 0; |
235 |
|
236 |
if (logfile) {
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237 |
#if 0
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cpu_dump_state(env, logfile, fprintf, 0);
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#endif
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fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n", |
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__func__, env->PC, address, rw, is_user, is_softmmu); |
242 |
} |
243 |
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rw &= 1;
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|
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/* data access */
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/* XXX: put correct access by using cpu_restore_state()
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248 |
correctly */
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249 |
access_type = ACCESS_INT; |
250 |
if (env->user_mode_only) {
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/* user mode only emulation */
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252 |
ret = TLBRET_NOMATCH; |
253 |
goto do_fault;
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254 |
} |
255 |
ret = get_physical_address(env, &physical, &prot, |
256 |
address, rw, access_type); |
257 |
if (logfile) {
|
258 |
fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
259 |
__func__, address, ret, physical, prot); |
260 |
} |
261 |
if (ret == TLBRET_MATCH) {
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262 |
ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
263 |
physical & TARGET_PAGE_MASK, prot, |
264 |
is_user, is_softmmu); |
265 |
} else if (ret < 0) { |
266 |
do_fault:
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267 |
switch (ret) {
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268 |
default:
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269 |
case TLBRET_BADADDR:
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270 |
/* Reference to kernel address from user mode or supervisor mode */
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271 |
/* Reference to supervisor address from user mode */
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272 |
if (rw)
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273 |
exception = EXCP_AdES; |
274 |
else
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275 |
exception = EXCP_AdEL; |
276 |
break;
|
277 |
case TLBRET_NOMATCH:
|
278 |
/* No TLB match for a mapped address */
|
279 |
if (rw)
|
280 |
exception = EXCP_TLBS; |
281 |
else
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282 |
exception = EXCP_TLBL; |
283 |
error_code = 1;
|
284 |
break;
|
285 |
case TLBRET_INVALID:
|
286 |
/* TLB match with no valid bit */
|
287 |
if (rw)
|
288 |
exception = EXCP_TLBS; |
289 |
else
|
290 |
exception = EXCP_TLBL; |
291 |
break;
|
292 |
case TLBRET_DIRTY:
|
293 |
/* TLB match but 'D' bit is cleared */
|
294 |
exception = EXCP_LTLBL; |
295 |
break;
|
296 |
|
297 |
} |
298 |
/* Raise exception */
|
299 |
env->CP0_BadVAddr = address; |
300 |
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
|
301 |
((address >> 9) & 0x007ffff0); |
302 |
env->CP0_EntryHi = |
303 |
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
304 |
#ifdef TARGET_MIPS64
|
305 |
env->CP0_EntryHi &= env->SEGMask; |
306 |
env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | |
307 |
((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) | |
308 |
((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); |
309 |
#endif
|
310 |
env->exception_index = exception; |
311 |
env->error_code = error_code; |
312 |
ret = 1;
|
313 |
} |
314 |
|
315 |
return ret;
|
316 |
} |
317 |
|
318 |
#if defined(CONFIG_USER_ONLY)
|
319 |
void do_interrupt (CPUState *env)
|
320 |
{ |
321 |
env->exception_index = EXCP_NONE; |
322 |
} |
323 |
#else
|
324 |
void do_interrupt (CPUState *env)
|
325 |
{ |
326 |
target_ulong offset; |
327 |
int cause = -1; |
328 |
|
329 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
330 |
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n", |
331 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index); |
332 |
} |
333 |
if (env->exception_index == EXCP_EXT_INTERRUPT &&
|
334 |
(env->hflags & MIPS_HFLAG_DM)) |
335 |
env->exception_index = EXCP_DINT; |
336 |
offset = 0x180;
|
337 |
switch (env->exception_index) {
|
338 |
case EXCP_DSS:
|
339 |
env->CP0_Debug |= 1 << CP0DB_DSS;
|
340 |
/* Debug single step cannot be raised inside a delay slot and
|
341 |
* resume will always occur on the next instruction
|
342 |
* (but we assume the pc has always been updated during
|
343 |
* code translation).
|
344 |
*/
|
345 |
env->CP0_DEPC = env->PC; |
346 |
goto enter_debug_mode;
|
347 |
case EXCP_DINT:
|
348 |
env->CP0_Debug |= 1 << CP0DB_DINT;
|
349 |
goto set_DEPC;
|
350 |
case EXCP_DIB:
|
351 |
env->CP0_Debug |= 1 << CP0DB_DIB;
|
352 |
goto set_DEPC;
|
353 |
case EXCP_DBp:
|
354 |
env->CP0_Debug |= 1 << CP0DB_DBp;
|
355 |
goto set_DEPC;
|
356 |
case EXCP_DDBS:
|
357 |
env->CP0_Debug |= 1 << CP0DB_DDBS;
|
358 |
goto set_DEPC;
|
359 |
case EXCP_DDBL:
|
360 |
env->CP0_Debug |= 1 << CP0DB_DDBL;
|
361 |
set_DEPC:
|
362 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
363 |
/* If the exception was raised from a delay slot,
|
364 |
come back to the jump. */
|
365 |
env->CP0_DEPC = env->PC - 4;
|
366 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
367 |
} else {
|
368 |
env->CP0_DEPC = env->PC; |
369 |
} |
370 |
enter_debug_mode:
|
371 |
env->hflags |= MIPS_HFLAG_DM; |
372 |
env->hflags |= MIPS_HFLAG_64; |
373 |
env->hflags &= ~MIPS_HFLAG_UM; |
374 |
/* EJTAG probe trap enable is not implemented... */
|
375 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
376 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
377 |
env->PC = (int32_t)0xBFC00480;
|
378 |
break;
|
379 |
case EXCP_RESET:
|
380 |
cpu_reset(env); |
381 |
break;
|
382 |
case EXCP_SRESET:
|
383 |
env->CP0_Status |= (1 << CP0St_SR);
|
384 |
memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
385 |
goto set_error_EPC;
|
386 |
case EXCP_NMI:
|
387 |
env->CP0_Status |= (1 << CP0St_NMI);
|
388 |
set_error_EPC:
|
389 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
390 |
/* If the exception was raised from a delay slot,
|
391 |
come back to the jump. */
|
392 |
env->CP0_ErrorEPC = env->PC - 4;
|
393 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
394 |
} else {
|
395 |
env->CP0_ErrorEPC = env->PC; |
396 |
} |
397 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
398 |
env->hflags |= MIPS_HFLAG_64; |
399 |
env->hflags &= ~MIPS_HFLAG_UM; |
400 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
401 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
402 |
env->PC = (int32_t)0xBFC00000;
|
403 |
break;
|
404 |
case EXCP_MCHECK:
|
405 |
cause = 24;
|
406 |
goto set_EPC;
|
407 |
case EXCP_EXT_INTERRUPT:
|
408 |
cause = 0;
|
409 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
410 |
offset = 0x200;
|
411 |
goto set_EPC;
|
412 |
case EXCP_DWATCH:
|
413 |
cause = 23;
|
414 |
/* XXX: TODO: manage defered watch exceptions */
|
415 |
goto set_EPC;
|
416 |
case EXCP_AdEL:
|
417 |
cause = 4;
|
418 |
goto set_EPC;
|
419 |
case EXCP_AdES:
|
420 |
cause = 5;
|
421 |
goto set_EPC;
|
422 |
case EXCP_TLBL:
|
423 |
cause = 2;
|
424 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
425 |
#ifdef TARGET_MIPS64
|
426 |
int R = env->CP0_BadVAddr >> 62; |
427 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
428 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
429 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
430 |
|
431 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
432 |
offset = 0x080;
|
433 |
else
|
434 |
#endif
|
435 |
offset = 0x000;
|
436 |
} |
437 |
goto set_EPC;
|
438 |
case EXCP_IBE:
|
439 |
cause = 6;
|
440 |
goto set_EPC;
|
441 |
case EXCP_DBE:
|
442 |
cause = 7;
|
443 |
goto set_EPC;
|
444 |
case EXCP_SYSCALL:
|
445 |
cause = 8;
|
446 |
goto set_EPC;
|
447 |
case EXCP_BREAK:
|
448 |
cause = 9;
|
449 |
goto set_EPC;
|
450 |
case EXCP_RI:
|
451 |
cause = 10;
|
452 |
goto set_EPC;
|
453 |
case EXCP_CpU:
|
454 |
cause = 11;
|
455 |
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
456 |
(env->error_code << CP0Ca_CE); |
457 |
goto set_EPC;
|
458 |
case EXCP_OVERFLOW:
|
459 |
cause = 12;
|
460 |
goto set_EPC;
|
461 |
case EXCP_TRAP:
|
462 |
cause = 13;
|
463 |
goto set_EPC;
|
464 |
case EXCP_FPE:
|
465 |
cause = 15;
|
466 |
goto set_EPC;
|
467 |
case EXCP_LTLBL:
|
468 |
cause = 1;
|
469 |
goto set_EPC;
|
470 |
case EXCP_TLBS:
|
471 |
cause = 3;
|
472 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
473 |
#ifdef TARGET_MIPS64
|
474 |
int R = env->CP0_BadVAddr >> 62; |
475 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
476 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
477 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
478 |
|
479 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
480 |
offset = 0x080;
|
481 |
else
|
482 |
#endif
|
483 |
offset = 0x000;
|
484 |
} |
485 |
set_EPC:
|
486 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
487 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
488 |
/* If the exception was raised from a delay slot,
|
489 |
come back to the jump. */
|
490 |
env->CP0_EPC = env->PC - 4;
|
491 |
env->CP0_Cause |= (1 << CP0Ca_BD);
|
492 |
} else {
|
493 |
env->CP0_EPC = env->PC; |
494 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
495 |
} |
496 |
env->CP0_Status |= (1 << CP0St_EXL);
|
497 |
env->hflags |= MIPS_HFLAG_64; |
498 |
env->hflags &= ~MIPS_HFLAG_UM; |
499 |
} |
500 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
501 |
if (env->CP0_Status & (1 << CP0St_BEV)) { |
502 |
env->PC = (int32_t)0xBFC00200;
|
503 |
} else {
|
504 |
env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
505 |
} |
506 |
env->PC += offset; |
507 |
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
508 |
break;
|
509 |
default:
|
510 |
if (logfile) {
|
511 |
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
|
512 |
env->exception_index); |
513 |
} |
514 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
515 |
exit(1);
|
516 |
} |
517 |
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
|
518 |
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n" |
519 |
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
520 |
__func__, env->PC, env->CP0_EPC, cause, env->exception_index, |
521 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
522 |
env->CP0_DEPC); |
523 |
} |
524 |
env->exception_index = EXCP_NONE; |
525 |
} |
526 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
527 |
|
528 |
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
529 |
{ |
530 |
r4k_tlb_t *tlb; |
531 |
target_ulong addr; |
532 |
target_ulong end; |
533 |
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
534 |
target_ulong mask; |
535 |
|
536 |
tlb = &env->mmu.r4k.tlb[idx]; |
537 |
/* The qemu TLB is flushed when the ASID changes, so no need to
|
538 |
flush these entries again. */
|
539 |
if (tlb->G == 0 && tlb->ASID != ASID) { |
540 |
return;
|
541 |
} |
542 |
|
543 |
if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
|
544 |
/* For tlbwr, we can shadow the discarded entry into
|
545 |
a new (fake) TLB entry, as long as the guest can not
|
546 |
tell that it's there. */
|
547 |
env->mmu.r4k.tlb[env->tlb_in_use] = *tlb; |
548 |
env->tlb_in_use++; |
549 |
return;
|
550 |
} |
551 |
|
552 |
/* 1k pages are not supported. */
|
553 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
554 |
if (tlb->V0) {
|
555 |
addr = tlb->VPN & ~mask; |
556 |
#ifdef TARGET_MIPS64
|
557 |
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
558 |
addr |= 0x3FFFFF0000000000ULL;
|
559 |
} |
560 |
#endif
|
561 |
end = addr | (mask >> 1);
|
562 |
while (addr < end) {
|
563 |
tlb_flush_page (env, addr); |
564 |
addr += TARGET_PAGE_SIZE; |
565 |
} |
566 |
} |
567 |
if (tlb->V1) {
|
568 |
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
569 |
#ifdef TARGET_MIPS64
|
570 |
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
571 |
addr |= 0x3FFFFF0000000000ULL;
|
572 |
} |
573 |
#endif
|
574 |
end = addr | mask; |
575 |
while (addr < end) {
|
576 |
tlb_flush_page (env, addr); |
577 |
addr += TARGET_PAGE_SIZE; |
578 |
} |
579 |
} |
580 |
} |