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1
/*
2
 *  MIPS emulation micro-operations for qemu.
3
 * 
4
 *  Copyright (c) 2004-2005 Jocelyn Mayer
5
 *  Copyright (c) 2006 Marius Groeger (FPU operations)
6
 *  Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
7
 *
8
 * This library is free software; you can redistribute it and/or
9
 * modify it under the terms of the GNU Lesser General Public
10
 * License as published by the Free Software Foundation; either
11
 * version 2 of the License, or (at your option) any later version.
12
 *
13
 * This library is distributed in the hope that it will be useful,
14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16
 * Lesser General Public License for more details.
17
 *
18
 * You should have received a copy of the GNU Lesser General Public
19
 * License along with this library; if not, write to the Free Software
20
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21
 */
22

    
23
#include "config.h"
24
#include "exec.h"
25

    
26
#ifndef CALL_FROM_TB0
27
#define CALL_FROM_TB0(func) func()
28
#endif
29
#ifndef CALL_FROM_TB1
30
#define CALL_FROM_TB1(func, arg0) func(arg0)
31
#endif
32
#ifndef CALL_FROM_TB1_CONST16
33
#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
34
#endif
35
#ifndef CALL_FROM_TB2
36
#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
37
#endif
38
#ifndef CALL_FROM_TB2_CONST16
39
#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
40
        CALL_FROM_TB2(func, arg0, arg1)
41
#endif
42
#ifndef CALL_FROM_TB3
43
#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
44
#endif
45
#ifndef CALL_FROM_TB4
46
#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
47
        func(arg0, arg1, arg2, arg3)
48
#endif
49

    
50
#define REG 1
51
#include "op_template.c"
52
#undef REG
53
#define REG 2
54
#include "op_template.c"
55
#undef REG
56
#define REG 3
57
#include "op_template.c"
58
#undef REG
59
#define REG 4
60
#include "op_template.c"
61
#undef REG
62
#define REG 5
63
#include "op_template.c"
64
#undef REG
65
#define REG 6
66
#include "op_template.c"
67
#undef REG
68
#define REG 7
69
#include "op_template.c"
70
#undef REG
71
#define REG 8
72
#include "op_template.c"
73
#undef REG
74
#define REG 9
75
#include "op_template.c"
76
#undef REG
77
#define REG 10
78
#include "op_template.c"
79
#undef REG
80
#define REG 11
81
#include "op_template.c"
82
#undef REG
83
#define REG 12
84
#include "op_template.c"
85
#undef REG
86
#define REG 13
87
#include "op_template.c"
88
#undef REG
89
#define REG 14
90
#include "op_template.c"
91
#undef REG
92
#define REG 15
93
#include "op_template.c"
94
#undef REG
95
#define REG 16
96
#include "op_template.c"
97
#undef REG
98
#define REG 17
99
#include "op_template.c"
100
#undef REG
101
#define REG 18
102
#include "op_template.c"
103
#undef REG
104
#define REG 19
105
#include "op_template.c"
106
#undef REG
107
#define REG 20
108
#include "op_template.c"
109
#undef REG
110
#define REG 21
111
#include "op_template.c"
112
#undef REG
113
#define REG 22
114
#include "op_template.c"
115
#undef REG
116
#define REG 23
117
#include "op_template.c"
118
#undef REG
119
#define REG 24
120
#include "op_template.c"
121
#undef REG
122
#define REG 25
123
#include "op_template.c"
124
#undef REG
125
#define REG 26
126
#include "op_template.c"
127
#undef REG
128
#define REG 27
129
#include "op_template.c"
130
#undef REG
131
#define REG 28
132
#include "op_template.c"
133
#undef REG
134
#define REG 29
135
#include "op_template.c"
136
#undef REG
137
#define REG 30
138
#include "op_template.c"
139
#undef REG
140
#define REG 31
141
#include "op_template.c"
142
#undef REG
143

    
144
#define TN
145
#include "op_template.c"
146
#undef TN
147

    
148
#define FREG 0
149
#include "fop_template.c"
150
#undef FREG
151
#define FREG 1
152
#include "fop_template.c"
153
#undef FREG
154
#define FREG 2
155
#include "fop_template.c"
156
#undef FREG
157
#define FREG 3
158
#include "fop_template.c"
159
#undef FREG
160
#define FREG 4
161
#include "fop_template.c"
162
#undef FREG
163
#define FREG 5
164
#include "fop_template.c"
165
#undef FREG
166
#define FREG 6
167
#include "fop_template.c"
168
#undef FREG
169
#define FREG 7
170
#include "fop_template.c"
171
#undef FREG
172
#define FREG 8
173
#include "fop_template.c"
174
#undef FREG
175
#define FREG 9
176
#include "fop_template.c"
177
#undef FREG
178
#define FREG 10
179
#include "fop_template.c"
180
#undef FREG
181
#define FREG 11
182
#include "fop_template.c"
183
#undef FREG
184
#define FREG 12
185
#include "fop_template.c"
186
#undef FREG
187
#define FREG 13
188
#include "fop_template.c"
189
#undef FREG
190
#define FREG 14
191
#include "fop_template.c"
192
#undef FREG
193
#define FREG 15
194
#include "fop_template.c"
195
#undef FREG
196
#define FREG 16
197
#include "fop_template.c"
198
#undef FREG
199
#define FREG 17
200
#include "fop_template.c"
201
#undef FREG
202
#define FREG 18
203
#include "fop_template.c"
204
#undef FREG
205
#define FREG 19
206
#include "fop_template.c"
207
#undef FREG
208
#define FREG 20
209
#include "fop_template.c"
210
#undef FREG
211
#define FREG 21
212
#include "fop_template.c"
213
#undef FREG
214
#define FREG 22
215
#include "fop_template.c"
216
#undef FREG
217
#define FREG 23
218
#include "fop_template.c"
219
#undef FREG
220
#define FREG 24
221
#include "fop_template.c"
222
#undef FREG
223
#define FREG 25
224
#include "fop_template.c"
225
#undef FREG
226
#define FREG 26
227
#include "fop_template.c"
228
#undef FREG
229
#define FREG 27
230
#include "fop_template.c"
231
#undef FREG
232
#define FREG 28
233
#include "fop_template.c"
234
#undef FREG
235
#define FREG 29
236
#include "fop_template.c"
237
#undef FREG
238
#define FREG 30
239
#include "fop_template.c"
240
#undef FREG
241
#define FREG 31
242
#include "fop_template.c"
243
#undef FREG
244

    
245
#define FTN
246
#include "fop_template.c"
247
#undef FTN
248

    
249
void op_dup_T0 (void)
250
{
251
    T2 = T0;
252
    RETURN();
253
}
254

    
255
void op_load_HI (void)
256
{
257
    T0 = env->HI;
258
    RETURN();
259
}
260

    
261
void op_store_HI (void)
262
{
263
    env->HI = T0;
264
    RETURN();
265
}
266

    
267
void op_load_LO (void)
268
{
269
    T0 = env->LO;
270
    RETURN();
271
}
272

    
273
void op_store_LO (void)
274
{
275
    env->LO = T0;
276
    RETURN();
277
}
278

    
279
/* Load and store */
280
#define MEMSUFFIX _raw
281
#include "op_mem.c"
282
#undef MEMSUFFIX
283
#if !defined(CONFIG_USER_ONLY)
284
#define MEMSUFFIX _user
285
#include "op_mem.c"
286
#undef MEMSUFFIX
287

    
288
#define MEMSUFFIX _kernel
289
#include "op_mem.c"
290
#undef MEMSUFFIX
291
#endif
292

    
293
/* Addresses computation */
294
void op_addr_add (void)
295
{
296
/* For compatibility with 32-bit code, data reference in user mode
297
   with Status_UX = 0 should be casted to 32-bit and sign extended.
298
   See the MIPS64 PRA manual, section 4.10. */
299
#ifdef TARGET_MIPS64
300
    if ((env->CP0_Status & (1 << CP0St_UM)) &&
301
        !(env->CP0_Status & (1 << CP0St_UX)))
302
        T0 = (int64_t)(int32_t)(T0 + T1);
303
    else
304
#endif
305
        T0 += T1;
306
    RETURN();
307
}
308

    
309
/* Arithmetic */
310
void op_add (void)
311
{
312
    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
313
    RETURN();
314
}
315

    
316
void op_addo (void)
317
{
318
    target_ulong tmp;
319

    
320
    tmp = (int32_t)T0;
321
    T0 = (int32_t)T0 + (int32_t)T1;
322
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
323
        /* operands of same sign, result different sign */
324
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
325
    }
326
    T0 = (int32_t)T0;
327
    RETURN();
328
}
329

    
330
void op_sub (void)
331
{
332
    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
333
    RETURN();
334
}
335

    
336
void op_subo (void)
337
{
338
    target_ulong tmp;
339

    
340
    tmp = (int32_t)T0;
341
    T0 = (int32_t)T0 - (int32_t)T1;
342
    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
343
        /* operands of different sign, first operand and result different sign */
344
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
345
    }
346
    T0 = (int32_t)T0;
347
    RETURN();
348
}
349

    
350
void op_mul (void)
351
{
352
    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
353
    RETURN();
354
}
355

    
356
#if HOST_LONG_BITS < 64
357
void op_div (void)
358
{
359
    CALL_FROM_TB0(do_div);
360
    RETURN();
361
}
362
#else
363
void op_div (void)
364
{
365
    if (T1 != 0) {
366
        env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
367
        env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
368
    }
369
    RETURN();
370
}
371
#endif
372

    
373
void op_divu (void)
374
{
375
    if (T1 != 0) {
376
        env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
377
        env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
378
    }
379
    RETURN();
380
}
381

    
382
#ifdef TARGET_MIPS64
383
/* Arithmetic */
384
void op_dadd (void)
385
{
386
    T0 += T1;
387
    RETURN();
388
}
389

    
390
void op_daddo (void)
391
{
392
    target_long tmp;
393

    
394
    tmp = T0;
395
    T0 += T1;
396
    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
397
        /* operands of same sign, result different sign */
398
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
399
    }
400
    RETURN();
401
}
402

    
403
void op_dsub (void)
404
{
405
    T0 -= T1;
406
    RETURN();
407
}
408

    
409
void op_dsubo (void)
410
{
411
    target_long tmp;
412

    
413
    tmp = T0;
414
    T0 = (int64_t)T0 - (int64_t)T1;
415
    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
416
        /* operands of different sign, first operand and result different sign */
417
        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
418
    }
419
    RETURN();
420
}
421

    
422
void op_dmul (void)
423
{
424
    T0 = (int64_t)T0 * (int64_t)T1;
425
    RETURN();
426
}
427

    
428
/* Those might call libgcc functions.  */
429
void op_ddiv (void)
430
{
431
    do_ddiv();
432
    RETURN();
433
}
434

    
435
#if TARGET_LONG_BITS > HOST_LONG_BITS
436
void op_ddivu (void)
437
{
438
    do_ddivu();
439
    RETURN();
440
}
441
#else
442
void op_ddivu (void)
443
{
444
    if (T1 != 0) {
445
        env->LO = T0 / T1;
446
        env->HI = T0 % T1;
447
    }
448
    RETURN();
449
}
450
#endif
451
#endif /* TARGET_MIPS64 */
452

    
453
/* Logical */
454
void op_and (void)
455
{
456
    T0 &= T1;
457
    RETURN();
458
}
459

    
460
void op_nor (void)
461
{
462
    T0 = ~(T0 | T1);
463
    RETURN();
464
}
465

    
466
void op_or (void)
467
{
468
    T0 |= T1;
469
    RETURN();
470
}
471

    
472
void op_xor (void)
473
{
474
    T0 ^= T1;
475
    RETURN();
476
}
477

    
478
void op_sll (void)
479
{
480
    T0 = (int32_t)((uint32_t)T0 << T1);
481
    RETURN();
482
}
483

    
484
void op_sra (void)
485
{
486
    T0 = (int32_t)((int32_t)T0 >> T1);
487
    RETURN();
488
}
489

    
490
void op_srl (void)
491
{
492
    T0 = (int32_t)((uint32_t)T0 >> T1);
493
    RETURN();
494
}
495

    
496
void op_rotr (void)
497
{
498
    target_ulong tmp;
499

    
500
    if (T1) {
501
       tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
502
       T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
503
    }
504
    RETURN();
505
}
506

    
507
void op_sllv (void)
508
{
509
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
510
    RETURN();
511
}
512

    
513
void op_srav (void)
514
{
515
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
516
    RETURN();
517
}
518

    
519
void op_srlv (void)
520
{
521
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
522
    RETURN();
523
}
524

    
525
void op_rotrv (void)
526
{
527
    target_ulong tmp;
528

    
529
    T0 &= 0x1F;
530
    if (T0) {
531
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
532
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
533
    } else
534
       T0 = T1;
535
    RETURN();
536
}
537

    
538
void op_clo (void)
539
{
540
    int n;
541

    
542
    if (T0 == ~((target_ulong)0)) {
543
        T0 = 32;
544
    } else {
545
        for (n = 0; n < 32; n++) {
546
            if (!(T0 & (1 << 31)))
547
                break;
548
            T0 = T0 << 1;
549
        }
550
        T0 = n;
551
    }
552
    RETURN();
553
}
554

    
555
void op_clz (void)
556
{
557
    int n;
558

    
559
    if (T0 == 0) {
560
        T0 = 32;
561
    } else {
562
        for (n = 0; n < 32; n++) {
563
            if (T0 & (1 << 31))
564
                break;
565
            T0 = T0 << 1;
566
        }
567
        T0 = n;
568
    }
569
    RETURN();
570
}
571

    
572
#ifdef TARGET_MIPS64
573

    
574
#if TARGET_LONG_BITS > HOST_LONG_BITS
575
/* Those might call libgcc functions.  */
576
void op_dsll (void)
577
{
578
    CALL_FROM_TB0(do_dsll);
579
    RETURN();
580
}
581

    
582
void op_dsll32 (void)
583
{
584
    CALL_FROM_TB0(do_dsll32);
585
    RETURN();
586
}
587

    
588
void op_dsra (void)
589
{
590
    CALL_FROM_TB0(do_dsra);
591
    RETURN();
592
}
593

    
594
void op_dsra32 (void)
595
{
596
    CALL_FROM_TB0(do_dsra32);
597
    RETURN();
598
}
599

    
600
void op_dsrl (void)
601
{
602
    CALL_FROM_TB0(do_dsrl);
603
    RETURN();
604
}
605

    
606
void op_dsrl32 (void)
607
{
608
    CALL_FROM_TB0(do_dsrl32);
609
    RETURN();
610
}
611

    
612
void op_drotr (void)
613
{
614
    CALL_FROM_TB0(do_drotr);
615
    RETURN();
616
}
617

    
618
void op_drotr32 (void)
619
{
620
    CALL_FROM_TB0(do_drotr32);
621
    RETURN();
622
}
623

    
624
void op_dsllv (void)
625
{
626
    CALL_FROM_TB0(do_dsllv);
627
    RETURN();
628
}
629

    
630
void op_dsrav (void)
631
{
632
    CALL_FROM_TB0(do_dsrav);
633
    RETURN();
634
}
635

    
636
void op_dsrlv (void)
637
{
638
    CALL_FROM_TB0(do_dsrlv);
639
    RETURN();
640
}
641

    
642
void op_drotrv (void)
643
{
644
    CALL_FROM_TB0(do_drotrv);
645
    RETURN();
646
}
647

    
648
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
649

    
650
void op_dsll (void)
651
{
652
    T0 = T0 << T1;
653
    RETURN();
654
}
655

    
656
void op_dsll32 (void)
657
{
658
    T0 = T0 << (T1 + 32);
659
    RETURN();
660
}
661

    
662
void op_dsra (void)
663
{
664
    T0 = (int64_t)T0 >> T1;
665
    RETURN();
666
}
667

    
668
void op_dsra32 (void)
669
{
670
    T0 = (int64_t)T0 >> (T1 + 32);
671
    RETURN();
672
}
673

    
674
void op_dsrl (void)
675
{
676
    T0 = T0 >> T1;
677
    RETURN();
678
}
679

    
680
void op_dsrl32 (void)
681
{
682
    T0 = T0 >> (T1 + 32);
683
    RETURN();
684
}
685

    
686
void op_drotr (void)
687
{
688
    target_ulong tmp;
689

    
690
    if (T1) {
691
       tmp = T0 << (0x40 - T1);
692
       T0 = (T0 >> T1) | tmp;
693
    }
694
    RETURN();
695
}
696

    
697
void op_drotr32 (void)
698
{
699
    target_ulong tmp;
700

    
701
    if (T1) {
702
       tmp = T0 << (0x40 - (32 + T1));
703
       T0 = (T0 >> (32 + T1)) | tmp;
704
    }
705
    RETURN();
706
}
707

    
708
void op_dsllv (void)
709
{
710
    T0 = T1 << (T0 & 0x3F);
711
    RETURN();
712
}
713

    
714
void op_dsrav (void)
715
{
716
    T0 = (int64_t)T1 >> (T0 & 0x3F);
717
    RETURN();
718
}
719

    
720
void op_dsrlv (void)
721
{
722
    T0 = T1 >> (T0 & 0x3F);
723
    RETURN();
724
}
725

    
726
void op_drotrv (void)
727
{
728
    target_ulong tmp;
729

    
730
    T0 &= 0x3F;
731
    if (T0) {
732
       tmp = T1 << (0x40 - T0);
733
       T0 = (T1 >> T0) | tmp;
734
    } else
735
       T0 = T1;
736
    RETURN();
737
}
738
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
739

    
740
void op_dclo (void)
741
{
742
    int n;
743

    
744
    if (T0 == ~((target_ulong)0)) {
745
        T0 = 64;
746
    } else {
747
        for (n = 0; n < 64; n++) {
748
            if (!(T0 & (1ULL << 63)))
749
                break;
750
            T0 = T0 << 1;
751
        }
752
        T0 = n;
753
    }
754
    RETURN();
755
}
756

    
757
void op_dclz (void)
758
{
759
    int n;
760

    
761
    if (T0 == 0) {
762
        T0 = 64;
763
    } else {
764
        for (n = 0; n < 64; n++) {
765
            if (T0 & (1ULL << 63))
766
                break;
767
            T0 = T0 << 1;
768
        }
769
        T0 = n;
770
    }
771
    RETURN();
772
}
773
#endif
774

    
775
/* 64 bits arithmetic */
776
#if TARGET_LONG_BITS > HOST_LONG_BITS
777
void op_mult (void)
778
{
779
    CALL_FROM_TB0(do_mult);
780
    RETURN();
781
}
782

    
783
void op_multu (void)
784
{
785
    CALL_FROM_TB0(do_multu);
786
    RETURN();
787
}
788

    
789
void op_madd (void)
790
{
791
    CALL_FROM_TB0(do_madd);
792
    RETURN();
793
}
794

    
795
void op_maddu (void)
796
{
797
    CALL_FROM_TB0(do_maddu);
798
    RETURN();
799
}
800

    
801
void op_msub (void)
802
{
803
    CALL_FROM_TB0(do_msub);
804
    RETURN();
805
}
806

    
807
void op_msubu (void)
808
{
809
    CALL_FROM_TB0(do_msubu);
810
    RETURN();
811
}
812

    
813
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
814

    
815
static inline uint64_t get_HILO (void)
816
{
817
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
818
}
819

    
820
static inline void set_HILO (uint64_t HILO)
821
{
822
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
823
    env->HI = (int32_t)(HILO >> 32);
824
}
825

    
826
void op_mult (void)
827
{
828
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
829
    RETURN();
830
}
831

    
832
void op_multu (void)
833
{
834
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
835
    RETURN();
836
}
837

    
838
void op_madd (void)
839
{
840
    int64_t tmp;
841

    
842
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
843
    set_HILO((int64_t)get_HILO() + tmp);
844
    RETURN();
845
}
846

    
847
void op_maddu (void)
848
{
849
    uint64_t tmp;
850

    
851
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
852
    set_HILO(get_HILO() + tmp);
853
    RETURN();
854
}
855

    
856
void op_msub (void)
857
{
858
    int64_t tmp;
859

    
860
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
861
    set_HILO((int64_t)get_HILO() - tmp);
862
    RETURN();
863
}
864

    
865
void op_msubu (void)
866
{
867
    uint64_t tmp;
868

    
869
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
870
    set_HILO(get_HILO() - tmp);
871
    RETURN();
872
}
873
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
874

    
875
#ifdef TARGET_MIPS64
876
void op_dmult (void)
877
{
878
    CALL_FROM_TB4(muls64, &(env->HI), &(env->LO), T0, T1);
879
    RETURN();
880
}
881

    
882
void op_dmultu (void)
883
{
884
    CALL_FROM_TB4(mulu64, &(env->HI), &(env->LO), T0, T1);
885
    RETURN();
886
}
887
#endif
888

    
889
/* Conditional moves */
890
void op_movn (void)
891
{
892
    if (T1 != 0)
893
        env->gpr[PARAM1] = T0;
894
    RETURN();
895
}
896

    
897
void op_movz (void)
898
{
899
    if (T1 == 0)
900
        env->gpr[PARAM1] = T0;
901
    RETURN();
902
}
903

    
904
void op_movf (void)
905
{
906
    if (!(env->fcr31 & PARAM1))
907
        T0 = T1;
908
    RETURN();
909
}
910

    
911
void op_movt (void)
912
{
913
    if (env->fcr31 & PARAM1)
914
        T0 = T1;
915
    RETURN();
916
}
917

    
918
/* Tests */
919
#define OP_COND(name, cond) \
920
void glue(op_, name) (void) \
921
{                           \
922
    if (cond) {             \
923
        T0 = 1;             \
924
    } else {                \
925
        T0 = 0;             \
926
    }                       \
927
    RETURN();               \
928
}
929

    
930
OP_COND(eq, T0 == T1);
931
OP_COND(ne, T0 != T1);
932
OP_COND(ge, (target_long)T0 >= (target_long)T1);
933
OP_COND(geu, T0 >= T1);
934
OP_COND(lt, (target_long)T0 < (target_long)T1);
935
OP_COND(ltu, T0 < T1);
936
OP_COND(gez, (target_long)T0 >= 0);
937
OP_COND(gtz, (target_long)T0 > 0);
938
OP_COND(lez, (target_long)T0 <= 0);
939
OP_COND(ltz, (target_long)T0 < 0);
940

    
941
/* Branches */
942
void OPPROTO op_goto_tb0(void)
943
{
944
    GOTO_TB(op_goto_tb0, PARAM1, 0);
945
    RETURN();
946
}
947

    
948
void OPPROTO op_goto_tb1(void)
949
{
950
    GOTO_TB(op_goto_tb1, PARAM1, 1);
951
    RETURN();
952
}
953

    
954
/* Branch to register */
955
void op_save_breg_target (void)
956
{
957
    env->btarget = T2;
958
    RETURN();
959
}
960

    
961
void op_restore_breg_target (void)
962
{
963
    T2 = env->btarget;
964
    RETURN();
965
}
966

    
967
void op_breg (void)
968
{
969
    env->PC = T2;
970
    RETURN();
971
}
972

    
973
void op_save_btarget (void)
974
{
975
    env->btarget = PARAM1;
976
    RETURN();
977
}
978

    
979
#ifdef TARGET_MIPS64
980
void op_save_btarget64 (void)
981
{
982
    env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
983
    RETURN();
984
}
985
#endif
986

    
987
/* Conditional branch */
988
void op_set_bcond (void)
989
{
990
    T2 = T0;
991
    RETURN();
992
}
993

    
994
void op_save_bcond (void)
995
{
996
    env->bcond = T2;
997
    RETURN();
998
}
999

    
1000
void op_restore_bcond (void)
1001
{
1002
    T2 = env->bcond;
1003
    RETURN();
1004
}
1005

    
1006
void op_jnz_T2 (void)
1007
{
1008
    if (T2)
1009
        GOTO_LABEL_PARAM(1);
1010
    RETURN();
1011
}
1012

    
1013
/* CP0 functions */
1014
void op_mfc0_index (void)
1015
{
1016
    T0 = env->CP0_Index;
1017
    RETURN();
1018
}
1019

    
1020
void op_mfc0_random (void)
1021
{
1022
    CALL_FROM_TB0(do_mfc0_random);
1023
    RETURN();
1024
}
1025

    
1026
void op_mfc0_entrylo0 (void)
1027
{
1028
    T0 = (int32_t)env->CP0_EntryLo0;
1029
    RETURN();
1030
}
1031

    
1032
void op_mfc0_entrylo1 (void)
1033
{
1034
    T0 = (int32_t)env->CP0_EntryLo1;
1035
    RETURN();
1036
}
1037

    
1038
void op_mfc0_context (void)
1039
{
1040
    T0 = (int32_t)env->CP0_Context;
1041
    RETURN();
1042
}
1043

    
1044
void op_mfc0_pagemask (void)
1045
{
1046
    T0 = env->CP0_PageMask;
1047
    RETURN();
1048
}
1049

    
1050
void op_mfc0_pagegrain (void)
1051
{
1052
    T0 = env->CP0_PageGrain;
1053
    RETURN();
1054
}
1055

    
1056
void op_mfc0_wired (void)
1057
{
1058
    T0 = env->CP0_Wired;
1059
    RETURN();
1060
}
1061

    
1062
void op_mfc0_hwrena (void)
1063
{
1064
    T0 = env->CP0_HWREna;
1065
    RETURN();
1066
}
1067

    
1068
void op_mfc0_badvaddr (void)
1069
{
1070
    T0 = (int32_t)env->CP0_BadVAddr;
1071
    RETURN();
1072
}
1073

    
1074
void op_mfc0_count (void)
1075
{
1076
    CALL_FROM_TB0(do_mfc0_count);
1077
    RETURN();
1078
}
1079

    
1080
void op_mfc0_entryhi (void)
1081
{
1082
    T0 = (int32_t)env->CP0_EntryHi;
1083
    RETURN();
1084
}
1085

    
1086
void op_mfc0_compare (void)
1087
{
1088
    T0 = env->CP0_Compare;
1089
    RETURN();
1090
}
1091

    
1092
void op_mfc0_status (void)
1093
{
1094
    T0 = env->CP0_Status;
1095
    RETURN();
1096
}
1097

    
1098
void op_mfc0_intctl (void)
1099
{
1100
    T0 = env->CP0_IntCtl;
1101
    RETURN();
1102
}
1103

    
1104
void op_mfc0_srsctl (void)
1105
{
1106
    T0 = env->CP0_SRSCtl;
1107
    RETURN();
1108
}
1109

    
1110
void op_mfc0_srsmap (void)
1111
{
1112
    T0 = env->CP0_SRSMap;
1113
    RETURN();
1114
}
1115

    
1116
void op_mfc0_cause (void)
1117
{
1118
    T0 = env->CP0_Cause;
1119
    RETURN();
1120
}
1121

    
1122
void op_mfc0_epc (void)
1123
{
1124
    T0 = (int32_t)env->CP0_EPC;
1125
    RETURN();
1126
}
1127

    
1128
void op_mfc0_prid (void)
1129
{
1130
    T0 = env->CP0_PRid;
1131
    RETURN();
1132
}
1133

    
1134
void op_mfc0_ebase (void)
1135
{
1136
    T0 = env->CP0_EBase;
1137
    RETURN();
1138
}
1139

    
1140
void op_mfc0_config0 (void)
1141
{
1142
    T0 = env->CP0_Config0;
1143
    RETURN();
1144
}
1145

    
1146
void op_mfc0_config1 (void)
1147
{
1148
    T0 = env->CP0_Config1;
1149
    RETURN();
1150
}
1151

    
1152
void op_mfc0_config2 (void)
1153
{
1154
    T0 = env->CP0_Config2;
1155
    RETURN();
1156
}
1157

    
1158
void op_mfc0_config3 (void)
1159
{
1160
    T0 = env->CP0_Config3;
1161
    RETURN();
1162
}
1163

    
1164
void op_mfc0_config6 (void)
1165
{
1166
    T0 = env->CP0_Config6;
1167
    RETURN();
1168
}
1169

    
1170
void op_mfc0_config7 (void)
1171
{
1172
    T0 = env->CP0_Config7;
1173
    RETURN();
1174
}
1175

    
1176
void op_mfc0_lladdr (void)
1177
{
1178
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1179
    RETURN();
1180
}
1181

    
1182
void op_mfc0_watchlo (void)
1183
{
1184
    T0 = (int32_t)env->CP0_WatchLo[PARAM1];
1185
    RETURN();
1186
}
1187

    
1188
void op_mfc0_watchhi (void)
1189
{
1190
    T0 = env->CP0_WatchHi[PARAM1];
1191
    RETURN();
1192
}
1193

    
1194
void op_mfc0_xcontext (void)
1195
{
1196
    T0 = (int32_t)env->CP0_XContext;
1197
    RETURN();
1198
}
1199

    
1200
void op_mfc0_framemask (void)
1201
{
1202
    T0 = env->CP0_Framemask;
1203
    RETURN();
1204
}
1205

    
1206
void op_mfc0_debug (void)
1207
{
1208
    T0 = env->CP0_Debug;
1209
    if (env->hflags & MIPS_HFLAG_DM)
1210
        T0 |= 1 << CP0DB_DM;
1211
    RETURN();
1212
}
1213

    
1214
void op_mfc0_depc (void)
1215
{
1216
    T0 = (int32_t)env->CP0_DEPC;
1217
    RETURN();
1218
}
1219

    
1220
void op_mfc0_performance0 (void)
1221
{
1222
    T0 = env->CP0_Performance0;
1223
    RETURN();
1224
}
1225

    
1226
void op_mfc0_taglo (void)
1227
{
1228
    T0 = env->CP0_TagLo;
1229
    RETURN();
1230
}
1231

    
1232
void op_mfc0_datalo (void)
1233
{
1234
    T0 = env->CP0_DataLo;
1235
    RETURN();
1236
}
1237

    
1238
void op_mfc0_taghi (void)
1239
{
1240
    T0 = env->CP0_TagHi;
1241
    RETURN();
1242
}
1243

    
1244
void op_mfc0_datahi (void)
1245
{
1246
    T0 = env->CP0_DataHi;
1247
    RETURN();
1248
}
1249

    
1250
void op_mfc0_errorepc (void)
1251
{
1252
    T0 = (int32_t)env->CP0_ErrorEPC;
1253
    RETURN();
1254
}
1255

    
1256
void op_mfc0_desave (void)
1257
{
1258
    T0 = env->CP0_DESAVE;
1259
    RETURN();
1260
}
1261

    
1262
void op_mtc0_index (void)
1263
{
1264
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->nb_tlb);
1265
    RETURN();
1266
}
1267

    
1268
void op_mtc0_entrylo0 (void)
1269
{
1270
    /* Large physaddr not implemented */
1271
    /* 1k pages not implemented */
1272
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1273
    RETURN();
1274
}
1275

    
1276
void op_mtc0_entrylo1 (void)
1277
{
1278
    /* Large physaddr not implemented */
1279
    /* 1k pages not implemented */
1280
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1281
    RETURN();
1282
}
1283

    
1284
void op_mtc0_context (void)
1285
{
1286
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1287
    RETURN();
1288
}
1289

    
1290
void op_mtc0_pagemask (void)
1291
{
1292
    /* 1k pages not implemented */
1293
    env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1294
    RETURN();
1295
}
1296

    
1297
void op_mtc0_pagegrain (void)
1298
{
1299
    /* SmartMIPS not implemented */
1300
    /* Large physaddr not implemented */
1301
    /* 1k pages not implemented */
1302
    env->CP0_PageGrain = 0;
1303
    RETURN();
1304
}
1305

    
1306
void op_mtc0_wired (void)
1307
{
1308
    env->CP0_Wired = T0 % env->nb_tlb;
1309
    RETURN();
1310
}
1311

    
1312
void op_mtc0_hwrena (void)
1313
{
1314
    env->CP0_HWREna = T0 & 0x0000000F;
1315
    RETURN();
1316
}
1317

    
1318
void op_mtc0_count (void)
1319
{
1320
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1321
    RETURN();
1322
}
1323

    
1324
void op_mtc0_entryhi (void)
1325
{
1326
    target_ulong old, val;
1327

    
1328
    /* 1k pages not implemented */
1329
    val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1330
#ifdef TARGET_MIPS64
1331
    val &= env->SEGMask;
1332
#endif
1333
    old = env->CP0_EntryHi;
1334
    env->CP0_EntryHi = val;
1335
    /* If the ASID changes, flush qemu's TLB.  */
1336
    if ((old & 0xFF) != (val & 0xFF))
1337
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1338
    RETURN();
1339
}
1340

    
1341
void op_mtc0_compare (void)
1342
{
1343
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1344
    RETURN();
1345
}
1346

    
1347
void op_mtc0_status (void)
1348
{
1349
    uint32_t val, old;
1350
    uint32_t mask = env->Status_rw_bitmask;
1351

    
1352
    /* No reverse endianness, no MDMX/DSP implemented. */
1353
    val = T0 & mask;
1354
    old = env->CP0_Status;
1355
    if (!(val & (1 << CP0St_EXL)) &&
1356
        !(val & (1 << CP0St_ERL)) &&
1357
        !(env->hflags & MIPS_HFLAG_DM) &&
1358
        (val & (1 << CP0St_UM)))
1359
        env->hflags |= MIPS_HFLAG_UM;
1360
#ifdef TARGET_MIPS64
1361
    if ((env->hflags & MIPS_HFLAG_UM) &&
1362
        !(val & (1 << CP0St_PX)) &&
1363
        !(val & (1 << CP0St_UX)))
1364
        env->hflags &= ~MIPS_HFLAG_64;
1365
#endif
1366
    if (val & (1 << CP0St_CU1))
1367
        env->hflags |= MIPS_HFLAG_FPU;
1368
    else
1369
        env->hflags &= ~MIPS_HFLAG_FPU;
1370
    if (val & (1 << CP0St_FR))
1371
        env->hflags |= MIPS_HFLAG_F64;
1372
    else
1373
        env->hflags &= ~MIPS_HFLAG_F64;
1374
    env->CP0_Status = (env->CP0_Status & ~mask) | val;
1375
    if (loglevel & CPU_LOG_EXEC)
1376
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1377
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1378
    RETURN();
1379
}
1380

    
1381
void op_mtc0_intctl (void)
1382
{
1383
    /* vectored interrupts not implemented, timer on int 7,
1384
       no performance counters. */
1385
    env->CP0_IntCtl |= T0 & 0x000002e0;
1386
    RETURN();
1387
}
1388

    
1389
void op_mtc0_srsctl (void)
1390
{
1391
    /* shadow registers not implemented */
1392
    env->CP0_SRSCtl = 0;
1393
    RETURN();
1394
}
1395

    
1396
void op_mtc0_srsmap (void)
1397
{
1398
    /* shadow registers not implemented */
1399
    env->CP0_SRSMap = 0;
1400
    RETURN();
1401
}
1402

    
1403
void op_mtc0_cause (void)
1404
{
1405
    uint32_t mask = 0x00C00300;
1406

    
1407
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1408
        mask |= 1 << CP0Ca_DC;
1409

    
1410
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1411

    
1412
    /* Handle the software interrupt as an hardware one, as they
1413
       are very similar */
1414
    if (T0 & CP0Ca_IP_mask) {
1415
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1416
    }
1417
    RETURN();
1418
}
1419

    
1420
void op_mtc0_epc (void)
1421
{
1422
    env->CP0_EPC = T0;
1423
    RETURN();
1424
}
1425

    
1426
void op_mtc0_ebase (void)
1427
{
1428
    /* vectored interrupts not implemented */
1429
    /* Multi-CPU not implemented */
1430
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1431
    RETURN();
1432
}
1433

    
1434
void op_mtc0_config0 (void)
1435
{
1436
    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
1437
    RETURN();
1438
}
1439

    
1440
void op_mtc0_config2 (void)
1441
{
1442
    /* tertiary/secondary caches not implemented */
1443
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1444
    RETURN();
1445
}
1446

    
1447
void op_mtc0_watchlo (void)
1448
{
1449
    /* Watch exceptions for instructions, data loads, data stores
1450
       not implemented. */
1451
    env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
1452
    RETURN();
1453
}
1454

    
1455
void op_mtc0_watchhi (void)
1456
{
1457
    env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
1458
    env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
1459
    RETURN();
1460
}
1461

    
1462
void op_mtc0_framemask (void)
1463
{
1464
    env->CP0_Framemask = T0; /* XXX */
1465
    RETURN();
1466
}
1467

    
1468
void op_mtc0_debug (void)
1469
{
1470
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1471
    if (T0 & (1 << CP0DB_DM))
1472
        env->hflags |= MIPS_HFLAG_DM;
1473
    else
1474
        env->hflags &= ~MIPS_HFLAG_DM;
1475
    RETURN();
1476
}
1477

    
1478
void op_mtc0_depc (void)
1479
{
1480
    env->CP0_DEPC = T0;
1481
    RETURN();
1482
}
1483

    
1484
void op_mtc0_performance0 (void)
1485
{
1486
    env->CP0_Performance0 = T0; /* XXX */
1487
    RETURN();
1488
}
1489

    
1490
void op_mtc0_taglo (void)
1491
{
1492
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1493
    RETURN();
1494
}
1495

    
1496
void op_mtc0_datalo (void)
1497
{
1498
    env->CP0_DataLo = T0; /* XXX */
1499
    RETURN();
1500
}
1501

    
1502
void op_mtc0_taghi (void)
1503
{
1504
    env->CP0_TagHi = T0; /* XXX */
1505
    RETURN();
1506
}
1507

    
1508
void op_mtc0_datahi (void)
1509
{
1510
    env->CP0_DataHi = T0; /* XXX */
1511
    RETURN();
1512
}
1513

    
1514
void op_mtc0_errorepc (void)
1515
{
1516
    env->CP0_ErrorEPC = T0;
1517
    RETURN();
1518
}
1519

    
1520
void op_mtc0_desave (void)
1521
{
1522
    env->CP0_DESAVE = T0;
1523
    RETURN();
1524
}
1525

    
1526
#ifdef TARGET_MIPS64
1527
void op_mtc0_xcontext (void)
1528
{
1529
    target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1530
    env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
1531
    RETURN();
1532
}
1533

    
1534
void op_dmfc0_entrylo0 (void)
1535
{
1536
    T0 = env->CP0_EntryLo0;
1537
    RETURN();
1538
}
1539

    
1540
void op_dmfc0_entrylo1 (void)
1541
{
1542
    T0 = env->CP0_EntryLo1;
1543
    RETURN();
1544
}
1545

    
1546
void op_dmfc0_context (void)
1547
{
1548
    T0 = env->CP0_Context;
1549
    RETURN();
1550
}
1551

    
1552
void op_dmfc0_badvaddr (void)
1553
{
1554
    T0 = env->CP0_BadVAddr;
1555
    RETURN();
1556
}
1557

    
1558
void op_dmfc0_entryhi (void)
1559
{
1560
    T0 = env->CP0_EntryHi;
1561
    RETURN();
1562
}
1563

    
1564
void op_dmfc0_epc (void)
1565
{
1566
    T0 = env->CP0_EPC;
1567
    RETURN();
1568
}
1569

    
1570
void op_dmfc0_lladdr (void)
1571
{
1572
    T0 = env->CP0_LLAddr >> 4;
1573
    RETURN();
1574
}
1575

    
1576
void op_dmfc0_watchlo (void)
1577
{
1578
    T0 = env->CP0_WatchLo[PARAM1];
1579
    RETURN();
1580
}
1581

    
1582
void op_dmfc0_xcontext (void)
1583
{
1584
    T0 = env->CP0_XContext;
1585
    RETURN();
1586
}
1587

    
1588
void op_dmfc0_depc (void)
1589
{
1590
    T0 = env->CP0_DEPC;
1591
    RETURN();
1592
}
1593

    
1594
void op_dmfc0_errorepc (void)
1595
{
1596
    T0 = env->CP0_ErrorEPC;
1597
    RETURN();
1598
}
1599
#endif /* TARGET_MIPS64 */
1600

    
1601
/* CP1 functions */
1602
#if 0
1603
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1604
#else
1605
# define DEBUG_FPU_STATE() do { } while(0)
1606
#endif
1607

    
1608
void op_cp0_enabled(void)
1609
{
1610
    if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
1611
        (env->hflags & MIPS_HFLAG_UM)) {
1612
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
1613
    }
1614
    RETURN();
1615
}
1616

    
1617
void op_cfc1 (void)
1618
{
1619
    switch (T1) {
1620
    case 0:
1621
        T0 = (int32_t)env->fcr0;
1622
        break;
1623
    case 25:
1624
        T0 = ((env->fcr31 >> 24) & 0xfe) | ((env->fcr31 >> 23) & 0x1);
1625
        break;
1626
    case 26:
1627
        T0 = env->fcr31 & 0x0003f07c;
1628
        break;
1629
    case 28:
1630
        T0 = (env->fcr31 & 0x00000f83) | ((env->fcr31 >> 22) & 0x4);
1631
        break;
1632
    default:
1633
        T0 = (int32_t)env->fcr31;
1634
        break;
1635
    }
1636
    DEBUG_FPU_STATE();
1637
    RETURN();
1638
}
1639

    
1640
void op_ctc1 (void)
1641
{
1642
    CALL_FROM_TB0(do_ctc1);
1643
    DEBUG_FPU_STATE();
1644
    RETURN();
1645
}
1646

    
1647
void op_mfc1 (void)
1648
{
1649
    T0 = WT0;
1650
    DEBUG_FPU_STATE();
1651
    RETURN();
1652
}
1653

    
1654
void op_mtc1 (void)
1655
{
1656
    WT0 = T0;
1657
    DEBUG_FPU_STATE();
1658
    RETURN();
1659
}
1660

    
1661
void op_dmfc1 (void)
1662
{
1663
    T0 = DT0;
1664
    DEBUG_FPU_STATE();
1665
    RETURN();
1666
}
1667

    
1668
void op_dmtc1 (void)
1669
{
1670
    DT0 = T0;
1671
    DEBUG_FPU_STATE();
1672
    RETURN();
1673
}
1674

    
1675
void op_mfhc1 (void)
1676
{
1677
    T0 = WTH0;
1678
    DEBUG_FPU_STATE();
1679
    RETURN();
1680
}
1681

    
1682
void op_mthc1 (void)
1683
{
1684
    WTH0 = T0;
1685
    DEBUG_FPU_STATE();
1686
    RETURN();
1687
}
1688

    
1689
/* Float support.
1690
   Single precition routines have a "s" suffix, double precision a
1691
   "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
1692
   paired single lowwer "pl", paired single upper "pu".  */
1693

    
1694
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1695

    
1696
FLOAT_OP(cvtd, s)
1697
{
1698
    CALL_FROM_TB0(do_float_cvtd_s);
1699
    DEBUG_FPU_STATE();
1700
    RETURN();
1701
}
1702
FLOAT_OP(cvtd, w)
1703
{
1704
    CALL_FROM_TB0(do_float_cvtd_w);
1705
    DEBUG_FPU_STATE();
1706
    RETURN();
1707
}
1708
FLOAT_OP(cvtd, l)
1709
{
1710
    CALL_FROM_TB0(do_float_cvtd_l);
1711
    DEBUG_FPU_STATE();
1712
    RETURN();
1713
}
1714
FLOAT_OP(cvtl, d)
1715
{
1716
    CALL_FROM_TB0(do_float_cvtl_d);
1717
    DEBUG_FPU_STATE();
1718
    RETURN();
1719
}
1720
FLOAT_OP(cvtl, s)
1721
{
1722
    CALL_FROM_TB0(do_float_cvtl_s);
1723
    DEBUG_FPU_STATE();
1724
    RETURN();
1725
}
1726
FLOAT_OP(cvtps, s)
1727
{
1728
    WT2 = WT0;
1729
    WTH2 = WT1;
1730
    DEBUG_FPU_STATE();
1731
    RETURN();
1732
}
1733
FLOAT_OP(cvtps, pw)
1734
{
1735
    CALL_FROM_TB0(do_float_cvtps_pw);
1736
    DEBUG_FPU_STATE();
1737
    RETURN();
1738
}
1739
FLOAT_OP(cvtpw, ps)
1740
{
1741
    CALL_FROM_TB0(do_float_cvtpw_ps);
1742
    DEBUG_FPU_STATE();
1743
    RETURN();
1744
}
1745
FLOAT_OP(cvts, d)
1746
{
1747
    CALL_FROM_TB0(do_float_cvts_d);
1748
    DEBUG_FPU_STATE();
1749
    RETURN();
1750
}
1751
FLOAT_OP(cvts, w)
1752
{
1753
    CALL_FROM_TB0(do_float_cvts_w);
1754
    DEBUG_FPU_STATE();
1755
    RETURN();
1756
}
1757
FLOAT_OP(cvts, l)
1758
{
1759
    CALL_FROM_TB0(do_float_cvts_l);
1760
    DEBUG_FPU_STATE();
1761
    RETURN();
1762
}
1763
FLOAT_OP(cvts, pl)
1764
{
1765
    CALL_FROM_TB0(do_float_cvts_pl);
1766
    DEBUG_FPU_STATE();
1767
    RETURN();
1768
}
1769
FLOAT_OP(cvts, pu)
1770
{
1771
    CALL_FROM_TB0(do_float_cvts_pu);
1772
    DEBUG_FPU_STATE();
1773
    RETURN();
1774
}
1775
FLOAT_OP(cvtw, s)
1776
{
1777
    CALL_FROM_TB0(do_float_cvtw_s);
1778
    DEBUG_FPU_STATE();
1779
    RETURN();
1780
}
1781
FLOAT_OP(cvtw, d)
1782
{
1783
    CALL_FROM_TB0(do_float_cvtw_d);
1784
    DEBUG_FPU_STATE();
1785
    RETURN();
1786
}
1787

    
1788
FLOAT_OP(pll, ps)
1789
{
1790
    DT2 = ((uint64_t)WT0 << 32) | WT1;
1791
    DEBUG_FPU_STATE();
1792
    RETURN();
1793
}
1794
FLOAT_OP(plu, ps)
1795
{
1796
    DT2 = ((uint64_t)WT0 << 32) | WTH1;
1797
    DEBUG_FPU_STATE();
1798
    RETURN();
1799
}
1800
FLOAT_OP(pul, ps)
1801
{
1802
    DT2 = ((uint64_t)WTH0 << 32) | WT1;
1803
    DEBUG_FPU_STATE();
1804
    RETURN();
1805
}
1806
FLOAT_OP(puu, ps)
1807
{
1808
    DT2 = ((uint64_t)WTH0 << 32) | WTH1;
1809
    DEBUG_FPU_STATE();
1810
    RETURN();
1811
}
1812

    
1813
#define FLOAT_ROUNDOP(op, ttype, stype)                    \
1814
FLOAT_OP(op ## ttype, stype)                               \
1815
{                                                          \
1816
    CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
1817
    DEBUG_FPU_STATE();                                     \
1818
    RETURN();                                              \
1819
}
1820

    
1821
FLOAT_ROUNDOP(round, l, d)
1822
FLOAT_ROUNDOP(round, l, s)
1823
FLOAT_ROUNDOP(round, w, d)
1824
FLOAT_ROUNDOP(round, w, s)
1825

    
1826
FLOAT_ROUNDOP(trunc, l, d)
1827
FLOAT_ROUNDOP(trunc, l, s)
1828
FLOAT_ROUNDOP(trunc, w, d)
1829
FLOAT_ROUNDOP(trunc, w, s)
1830

    
1831
FLOAT_ROUNDOP(ceil, l, d)
1832
FLOAT_ROUNDOP(ceil, l, s)
1833
FLOAT_ROUNDOP(ceil, w, d)
1834
FLOAT_ROUNDOP(ceil, w, s)
1835

    
1836
FLOAT_ROUNDOP(floor, l, d)
1837
FLOAT_ROUNDOP(floor, l, s)
1838
FLOAT_ROUNDOP(floor, w, d)
1839
FLOAT_ROUNDOP(floor, w, s)
1840
#undef FLOAR_ROUNDOP
1841

    
1842
FLOAT_OP(movf, d)
1843
{
1844
    if (!(env->fcr31 & PARAM1))
1845
        DT2 = DT0;
1846
    DEBUG_FPU_STATE();
1847
    RETURN();
1848
}
1849
FLOAT_OP(movf, s)
1850
{
1851
    if (!(env->fcr31 & PARAM1))
1852
        WT2 = WT0;
1853
    DEBUG_FPU_STATE();
1854
    RETURN();
1855
}
1856
FLOAT_OP(movf, ps)
1857
{
1858
    if (!(env->fcr31 & PARAM1)) {
1859
        WT2 = WT0;
1860
        WTH2 = WTH0;
1861
    }
1862
    DEBUG_FPU_STATE();
1863
    RETURN();
1864
}
1865
FLOAT_OP(movt, d)
1866
{
1867
    if (env->fcr31 & PARAM1)
1868
        DT2 = DT0;
1869
    DEBUG_FPU_STATE();
1870
    RETURN();
1871
}
1872
FLOAT_OP(movt, s)
1873
{
1874
    if (env->fcr31 & PARAM1)
1875
        WT2 = WT0;
1876
    DEBUG_FPU_STATE();
1877
    RETURN();
1878
}
1879
FLOAT_OP(movt, ps)
1880
{
1881
    if (env->fcr31 & PARAM1) {
1882
        WT2 = WT0;
1883
        WTH2 = WTH0;
1884
    }
1885
    DEBUG_FPU_STATE();
1886
    RETURN();
1887
}
1888
FLOAT_OP(movz, d)
1889
{
1890
    if (!T0)
1891
        DT2 = DT0;
1892
    DEBUG_FPU_STATE();
1893
    RETURN();
1894
}
1895
FLOAT_OP(movz, s)
1896
{
1897
    if (!T0)
1898
        WT2 = WT0;
1899
    DEBUG_FPU_STATE();
1900
    RETURN();
1901
}
1902
FLOAT_OP(movz, ps)
1903
{
1904
    if (!T0) {
1905
        WT2 = WT0;
1906
        WTH2 = WTH0;
1907
    }
1908
    DEBUG_FPU_STATE();
1909
    RETURN();
1910
}
1911
FLOAT_OP(movn, d)
1912
{
1913
    if (T0)
1914
        DT2 = DT0;
1915
    DEBUG_FPU_STATE();
1916
    RETURN();
1917
}
1918
FLOAT_OP(movn, s)
1919
{
1920
    if (T0)
1921
        WT2 = WT0;
1922
    DEBUG_FPU_STATE();
1923
    RETURN();
1924
}
1925
FLOAT_OP(movn, ps)
1926
{
1927
    if (T0) {
1928
        WT2 = WT0;
1929
        WTH2 = WTH0;
1930
    }
1931
    DEBUG_FPU_STATE();
1932
    RETURN();
1933
}
1934

    
1935
/* operations calling helpers, for s, d and ps */
1936
#define FLOAT_HOP(name) \
1937
FLOAT_OP(name, d)         \
1938
{                         \
1939
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
1940
    DEBUG_FPU_STATE();    \
1941
    RETURN();             \
1942
}                         \
1943
FLOAT_OP(name, s)         \
1944
{                         \
1945
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
1946
    DEBUG_FPU_STATE();    \
1947
    RETURN();             \
1948
}                         \
1949
FLOAT_OP(name, ps)        \
1950
{                         \
1951
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
1952
    DEBUG_FPU_STATE();    \
1953
    RETURN();             \
1954
}
1955
FLOAT_HOP(add)
1956
FLOAT_HOP(sub)
1957
FLOAT_HOP(mul)
1958
FLOAT_HOP(div)
1959
FLOAT_HOP(recip2)
1960
FLOAT_HOP(rsqrt2)
1961
FLOAT_HOP(rsqrt1)
1962
FLOAT_HOP(recip1)
1963
#undef FLOAT_HOP
1964

    
1965
/* operations calling helpers, for s and d */
1966
#define FLOAT_HOP(name)   \
1967
FLOAT_OP(name, d)         \
1968
{                         \
1969
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
1970
    DEBUG_FPU_STATE();    \
1971
    RETURN();             \
1972
}                         \
1973
FLOAT_OP(name, s)         \
1974
{                         \
1975
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
1976
    DEBUG_FPU_STATE();    \
1977
    RETURN();             \
1978
}
1979
FLOAT_HOP(rsqrt)
1980
FLOAT_HOP(recip)
1981
#undef FLOAT_HOP
1982

    
1983
/* operations calling helpers, for ps */
1984
#define FLOAT_HOP(name)   \
1985
FLOAT_OP(name, ps)        \
1986
{                         \
1987
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
1988
    DEBUG_FPU_STATE();    \
1989
    RETURN();             \
1990
}
1991
FLOAT_HOP(addr)
1992
FLOAT_HOP(mulr)
1993
#undef FLOAT_HOP
1994

    
1995
/* ternary operations */
1996
#define FLOAT_TERNOP(name1, name2) \
1997
FLOAT_OP(name1 ## name2, d)        \
1998
{                                  \
1999
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status);    \
2000
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status);    \
2001
    DEBUG_FPU_STATE();             \
2002
    RETURN();                      \
2003
}                                  \
2004
FLOAT_OP(name1 ## name2, s)        \
2005
{                                  \
2006
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2007
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2008
    DEBUG_FPU_STATE();             \
2009
    RETURN();                      \
2010
}                                  \
2011
FLOAT_OP(name1 ## name2, ps)       \
2012
{                                  \
2013
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2014
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2015
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2016
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2017
    DEBUG_FPU_STATE();             \
2018
    RETURN();                      \
2019
}
2020
FLOAT_TERNOP(mul, add)
2021
FLOAT_TERNOP(mul, sub)
2022
#undef FLOAT_TERNOP
2023

    
2024
/* negated ternary operations */
2025
#define FLOAT_NTERNOP(name1, name2) \
2026
FLOAT_OP(n ## name1 ## name2, d)    \
2027
{                                   \
2028
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status);    \
2029
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status);    \
2030
    FDT2 ^= 1ULL << 63;             \
2031
    DEBUG_FPU_STATE();              \
2032
    RETURN();                       \
2033
}                                   \
2034
FLOAT_OP(n ## name1 ## name2, s)    \
2035
{                                   \
2036
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2037
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2038
    FST2 ^= 1 << 31;                \
2039
    DEBUG_FPU_STATE();              \
2040
    RETURN();                       \
2041
}                                   \
2042
FLOAT_OP(n ## name1 ## name2, ps)   \
2043
{                                   \
2044
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2045
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2046
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2047
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2048
    FST2 ^= 1 << 31;                \
2049
    FSTH2 ^= 1 << 31;               \
2050
    DEBUG_FPU_STATE();              \
2051
    RETURN();                       \
2052
}
2053
FLOAT_NTERNOP(mul, add)
2054
FLOAT_NTERNOP(mul, sub)
2055
#undef FLOAT_NTERNOP
2056

    
2057
/* unary operations, modifying fp status  */
2058
#define FLOAT_UNOP(name)  \
2059
FLOAT_OP(name, d)         \
2060
{                         \
2061
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
2062
    DEBUG_FPU_STATE();    \
2063
    RETURN();                      \
2064
}                         \
2065
FLOAT_OP(name, s)         \
2066
{                         \
2067
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
2068
    DEBUG_FPU_STATE();    \
2069
    RETURN();             \
2070
}
2071
FLOAT_UNOP(sqrt)
2072
#undef FLOAT_UNOP
2073

    
2074
/* unary operations, not modifying fp status  */
2075
#define FLOAT_UNOP(name)  \
2076
FLOAT_OP(name, d)         \
2077
{                         \
2078
    FDT2 = float64_ ## name(FDT0);   \
2079
    DEBUG_FPU_STATE();    \
2080
    RETURN();             \
2081
}                         \
2082
FLOAT_OP(name, s)         \
2083
{                         \
2084
    FST2 = float32_ ## name(FST0);   \
2085
    DEBUG_FPU_STATE();    \
2086
    RETURN();             \
2087
}                         \
2088
FLOAT_OP(name, ps)        \
2089
{                         \
2090
    FST2 = float32_ ## name(FST0);   \
2091
    FSTH2 = float32_ ## name(FSTH0); \
2092
    DEBUG_FPU_STATE();    \
2093
    RETURN();             \
2094
}
2095
FLOAT_UNOP(abs)
2096
FLOAT_UNOP(chs)
2097
#undef FLOAT_UNOP
2098

    
2099
FLOAT_OP(mov, d)
2100
{
2101
    FDT2 = FDT0;
2102
    DEBUG_FPU_STATE();
2103
    RETURN();
2104
}
2105
FLOAT_OP(mov, s)
2106
{
2107
    FST2 = FST0;
2108
    DEBUG_FPU_STATE();
2109
    RETURN();
2110
}
2111
FLOAT_OP(mov, ps)
2112
{
2113
    FST2 = FST0;
2114
    FSTH2 = FSTH0;
2115
    DEBUG_FPU_STATE();
2116
    RETURN();
2117
}
2118
FLOAT_OP(alnv, ps)
2119
{
2120
    switch (T0 & 0x7) {
2121
    case 0:
2122
        FST2 = FST0;
2123
        FSTH2 = FSTH0;
2124
        break;
2125
    case 4:
2126
#ifdef TARGET_WORDS_BIGENDIAN
2127
        FSTH2 = FST0;
2128
        FST2 = FSTH1;
2129
#else
2130
        FSTH2 = FST1;
2131
        FST2 = FSTH0;
2132
#endif
2133
        break;
2134
    default: /* unpredictable */
2135
        break;
2136
    }
2137
    DEBUG_FPU_STATE();
2138
    RETURN();
2139
}
2140

    
2141
#ifdef CONFIG_SOFTFLOAT
2142
#define clear_invalid() do {                                \
2143
    int flags = get_float_exception_flags(&env->fp_status); \
2144
    flags &= ~float_flag_invalid;                           \
2145
    set_float_exception_flags(flags, &env->fp_status);      \
2146
} while(0)
2147
#else
2148
#define clear_invalid() do { } while(0)
2149
#endif
2150

    
2151
extern void dump_fpu_s(CPUState *env);
2152

    
2153
#define CMP_OP(fmt, op)                                \
2154
void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void)       \
2155
{                                                      \
2156
    CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2157
    DEBUG_FPU_STATE();                                 \
2158
    RETURN();                                          \
2159
}                                                      \
2160
void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void)    \
2161
{                                                      \
2162
    CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2163
    DEBUG_FPU_STATE();                                 \
2164
    RETURN();                                          \
2165
}
2166
#define CMP_OPS(op)   \
2167
CMP_OP(d, op)         \
2168
CMP_OP(s, op)         \
2169
CMP_OP(ps, op)
2170

    
2171
CMP_OPS(f)
2172
CMP_OPS(un)
2173
CMP_OPS(eq)
2174
CMP_OPS(ueq)
2175
CMP_OPS(olt)
2176
CMP_OPS(ult)
2177
CMP_OPS(ole)
2178
CMP_OPS(ule)
2179
CMP_OPS(sf)
2180
CMP_OPS(ngle)
2181
CMP_OPS(seq)
2182
CMP_OPS(ngl)
2183
CMP_OPS(lt)
2184
CMP_OPS(nge)
2185
CMP_OPS(le)
2186
CMP_OPS(ngt)
2187
#undef CMP_OPS
2188
#undef CMP_OP
2189

    
2190
void op_bc1f (void)
2191
{
2192
    T0 = !!(~GET_FP_COND(env) & (0x1 << PARAM1));
2193
    DEBUG_FPU_STATE();
2194
    RETURN();
2195
}
2196
void op_bc1any2f (void)
2197
{
2198
    T0 = !!(~GET_FP_COND(env) & (0x3 << PARAM1));
2199
    DEBUG_FPU_STATE();
2200
    RETURN();
2201
}
2202
void op_bc1any4f (void)
2203
{
2204
    T0 = !!(~GET_FP_COND(env) & (0xf << PARAM1));
2205
    DEBUG_FPU_STATE();
2206
    RETURN();
2207
}
2208

    
2209
void op_bc1t (void)
2210
{
2211
    T0 = !!(GET_FP_COND(env) & (0x1 << PARAM1));
2212
    DEBUG_FPU_STATE();
2213
    RETURN();
2214
}
2215
void op_bc1any2t (void)
2216
{
2217
    T0 = !!(GET_FP_COND(env) & (0x3 << PARAM1));
2218
    DEBUG_FPU_STATE();
2219
    RETURN();
2220
}
2221
void op_bc1any4t (void)
2222
{
2223
    T0 = !!(GET_FP_COND(env) & (0xf << PARAM1));
2224
    DEBUG_FPU_STATE();
2225
    RETURN();
2226
}
2227

    
2228
void op_tlbwi (void)
2229
{
2230
    CALL_FROM_TB0(env->do_tlbwi);
2231
    RETURN();
2232
}
2233

    
2234
void op_tlbwr (void)
2235
{
2236
    CALL_FROM_TB0(env->do_tlbwr);
2237
    RETURN();
2238
}
2239

    
2240
void op_tlbp (void)
2241
{
2242
    CALL_FROM_TB0(env->do_tlbp);
2243
    RETURN();
2244
}
2245

    
2246
void op_tlbr (void)
2247
{
2248
    CALL_FROM_TB0(env->do_tlbr);
2249
    RETURN();
2250
}
2251

    
2252
/* Specials */
2253
#if defined (CONFIG_USER_ONLY)
2254
void op_tls_value (void)
2255
{
2256
    T0 = env->tls_value;
2257
}
2258
#endif
2259

    
2260
void op_pmon (void)
2261
{
2262
    CALL_FROM_TB1(do_pmon, PARAM1);
2263
    RETURN();
2264
}
2265

    
2266
void op_di (void)
2267
{
2268
    T0 = env->CP0_Status;
2269
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2270
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2271
    RETURN();
2272
}
2273

    
2274
void op_ei (void)
2275
{
2276
    T0 = env->CP0_Status;
2277
    env->CP0_Status = T0 | (1 << CP0St_IE);
2278
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2279
    RETURN();
2280
}
2281

    
2282
void op_trap (void)
2283
{
2284
    if (T0) {
2285
        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2286
    }
2287
    RETURN();
2288
}
2289

    
2290
void op_debug (void)
2291
{
2292
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2293
    RETURN();
2294
}
2295

    
2296
void op_set_lladdr (void)
2297
{
2298
    env->CP0_LLAddr = T2;
2299
    RETURN();
2300
}
2301

    
2302
void debug_pre_eret (void);
2303
void debug_post_eret (void);
2304
void op_eret (void)
2305
{
2306
    if (loglevel & CPU_LOG_EXEC)
2307
        CALL_FROM_TB0(debug_pre_eret);
2308
    if (env->CP0_Status & (1 << CP0St_ERL)) {
2309
        env->PC = env->CP0_ErrorEPC;
2310
        env->CP0_Status &= ~(1 << CP0St_ERL);
2311
    } else {
2312
        env->PC = env->CP0_EPC;
2313
        env->CP0_Status &= ~(1 << CP0St_EXL);
2314
    }
2315
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2316
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2317
        !(env->hflags & MIPS_HFLAG_DM) &&
2318
        (env->CP0_Status & (1 << CP0St_UM)))
2319
        env->hflags |= MIPS_HFLAG_UM;
2320
#ifdef TARGET_MIPS64
2321
    if ((env->hflags & MIPS_HFLAG_UM) &&
2322
        !(env->CP0_Status & (1 << CP0St_PX)) &&
2323
        !(env->CP0_Status & (1 << CP0St_UX)))
2324
        env->hflags &= ~MIPS_HFLAG_64;
2325
#endif
2326
    if (loglevel & CPU_LOG_EXEC)
2327
        CALL_FROM_TB0(debug_post_eret);
2328
    env->CP0_LLAddr = 1;
2329
    RETURN();
2330
}
2331

    
2332
void op_deret (void)
2333
{
2334
    if (loglevel & CPU_LOG_EXEC)
2335
        CALL_FROM_TB0(debug_pre_eret);
2336
    env->PC = env->CP0_DEPC;
2337
    env->hflags |= MIPS_HFLAG_DM;
2338
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2339
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2340
        !(env->hflags & MIPS_HFLAG_DM) &&
2341
        (env->CP0_Status & (1 << CP0St_UM)))
2342
        env->hflags |= MIPS_HFLAG_UM;
2343
#ifdef TARGET_MIPS64
2344
    if ((env->hflags & MIPS_HFLAG_UM) &&
2345
        !(env->CP0_Status & (1 << CP0St_PX)) &&
2346
        !(env->CP0_Status & (1 << CP0St_UX)))
2347
        env->hflags &= ~MIPS_HFLAG_64;
2348
#endif
2349
    if (loglevel & CPU_LOG_EXEC)
2350
        CALL_FROM_TB0(debug_post_eret);
2351
    env->CP0_LLAddr = 1;
2352
    RETURN();
2353
}
2354

    
2355
void op_rdhwr_cpunum(void)
2356
{
2357
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2358
        (env->CP0_HWREna & (1 << 0)) ||
2359
        (env->CP0_Status & (1 << CP0St_CU0)))
2360
        T0 = env->CP0_EBase & 0x3ff;
2361
    else
2362
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2363
    RETURN();
2364
}
2365

    
2366
void op_rdhwr_synci_step(void)
2367
{
2368
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2369
        (env->CP0_HWREna & (1 << 1)) ||
2370
        (env->CP0_Status & (1 << CP0St_CU0)))
2371
        T0 = env->SYNCI_Step;
2372
    else
2373
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2374
    RETURN();
2375
}
2376

    
2377
void op_rdhwr_cc(void)
2378
{
2379
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2380
        (env->CP0_HWREna & (1 << 2)) ||
2381
        (env->CP0_Status & (1 << CP0St_CU0)))
2382
        T0 = env->CP0_Count;
2383
    else
2384
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2385
    RETURN();
2386
}
2387

    
2388
void op_rdhwr_ccres(void)
2389
{
2390
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2391
        (env->CP0_HWREna & (1 << 3)) ||
2392
        (env->CP0_Status & (1 << CP0St_CU0)))
2393
        T0 = env->CCRes;
2394
    else
2395
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2396
    RETURN();
2397
}
2398

    
2399
void op_save_state (void)
2400
{
2401
    env->hflags = PARAM1;
2402
    RETURN();
2403
}
2404

    
2405
void op_save_pc (void)
2406
{
2407
    env->PC = PARAM1;
2408
    RETURN();
2409
}
2410

    
2411
#ifdef TARGET_MIPS64
2412
void op_save_pc64 (void)
2413
{
2414
    env->PC = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
2415
    RETURN();
2416
}
2417
#endif
2418

    
2419
void op_interrupt_restart (void)
2420
{
2421
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2422
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2423
        !(env->hflags & MIPS_HFLAG_DM) &&
2424
        (env->CP0_Status & (1 << CP0St_IE)) &&
2425
        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
2426
        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
2427
        CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
2428
    }
2429
    RETURN();
2430
}
2431

    
2432
void op_raise_exception (void)
2433
{
2434
    CALL_FROM_TB1(do_raise_exception, PARAM1);
2435
    RETURN();
2436
}
2437

    
2438
void op_raise_exception_err (void)
2439
{
2440
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2441
    RETURN();
2442
}
2443

    
2444
void op_exit_tb (void)
2445
{
2446
    EXIT_TB();
2447
    RETURN();
2448
}
2449

    
2450
void op_wait (void)
2451
{
2452
    env->halted = 1;
2453
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2454
    RETURN();
2455
}
2456

    
2457
/* Bitfield operations. */
2458
void op_ext(void)
2459
{
2460
    unsigned int pos = PARAM1;
2461
    unsigned int size = PARAM2;
2462

    
2463
    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2464
    RETURN();
2465
}
2466

    
2467
void op_ins(void)
2468
{
2469
    unsigned int pos = PARAM1;
2470
    unsigned int size = PARAM2;
2471
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2472

    
2473
    T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
2474
    RETURN();
2475
}
2476

    
2477
void op_wsbh(void)
2478
{
2479
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2480
    RETURN();
2481
}
2482

    
2483
#ifdef TARGET_MIPS64
2484
void op_dext(void)
2485
{
2486
    unsigned int pos = PARAM1;
2487
    unsigned int size = PARAM2;
2488

    
2489
    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2490
    RETURN();
2491
}
2492

    
2493
void op_dins(void)
2494
{
2495
    unsigned int pos = PARAM1;
2496
    unsigned int size = PARAM2;
2497
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2498

    
2499
    T0 = (T0 & ~mask) | ((T1 << pos) & mask);
2500
    RETURN();
2501
}
2502

    
2503
void op_dsbh(void)
2504
{
2505
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2506
    RETURN();
2507
}
2508

    
2509
void op_dshd(void)
2510
{
2511
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2512
    RETURN();
2513
}
2514
#endif
2515

    
2516
void op_seb(void)
2517
{
2518
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2519
    RETURN();
2520
}
2521

    
2522
void op_seh(void)
2523
{
2524
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2525
    RETURN();
2526
}