Archipelago » qemu

    /* we restore the process signal mask as the sigreturn should

       do it (XXX: use sigsetjmp) */

        sigprocmask(SIG_SETMASK, old_set, NULL);

    } else {

        /* activate soft MMU for this block */

        cpu_resume_from_signal(env, puc);

#include "softmmu_exec.h"

#endif /* !defined(CONFIG_USER_ONLY) */

int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,

                          int rw, int access_type);

//#define FLUSH_ALL_TLBS

/*****************************************************************************/

/* PowerPC MMU emulation */

#if defined(CONFIG_USER_ONLY)

#include "def-helper.h"

DEF_HELPER_2(raise_exception_err, void, i32, i32)

DEF_HELPER_3(tw, void, tl, tl, i32)

#if defined(TARGET_PPC64)

DEF_HELPER_3(td, void, tl, tl, i32)

void helper_raise_exception_err (uint32_t exception, uint32_t error_code)

{

}

{

}

/*****************************************************************************/

    if (likely(xer_bc != 0)) {

        if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||

                     (reg < rb && (reg + xer_bc) > rb))) {

        } else {

            helper_lsw(addr, xer_bc, reg);

        }

        /* Update the floating-point enabled exception summary */

        env->fpscr |= 1 << FPSCR_FEX;

        if (msr_fe0 != 0 || msr_fe1 != 0)

    }

    return ret;

}

        /* Update the floating-point enabled exception summary */

        env->fpscr |= 1 << FPSCR_FEX;

        if (msr_fe0 != 0 || msr_fe1 != 0) {

        }

    } else {

        /* Set the result to infinity */

        (env->error_code & POWERPC_EXCP_FP)) {

        /* Differred floating-point exception after target FPR update */

        if (msr_fe0 != 0 || msr_fe1 != 0)

    } else if (env->fp_status.float_exception_flags & float_flag_overflow) {

        float_overflow_excp();

    } else if (env->fp_status.float_exception_flags & float_flag_underflow) {

        (env->error_code & POWERPC_EXCP_FP)) {

        /* Differred floating-point exception after target FPR update */

        if (msr_fe0 != 0 || msr_fe1 != 0)

    }

#endif

}

    val = hreg_store_msr(env, val, 0);

    if (val != 0) {

        env->interrupt_request |= CPU_INTERRUPT_EXITTB;

    }

}

                  ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||

                  ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||

                  ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {

    }

}

                  ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||

                  ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||

                  ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))

}

#endif

        if (loglevel != 0) {

            fprintf(logfile, "No DCR environment\n");

        }

    } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {

        if (loglevel != 0) {

            fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);

        }

    }

    return val;

}

        if (loglevel != 0) {

            fprintf(logfile, "No DCR environment\n");

        }

    } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {

        if (loglevel != 0) {

            fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);

        }

    }

}

                cpu_restore_state(tb, env, pc, NULL);

            }

        }

    }

    env = saved_env;

}

        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);

}

/* Stop translation */

{

    gen_update_nip(ctx, ctx->nip);

    ctx->exception = POWERPC_EXCP_STOP;

}

/* No need to update nip here, as execution flow will change */

{

    ctx->exception = POWERPC_EXCP_SYNC;

}

/* Invalid instruction */

GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)

{

}

static opc_handler_t invalid_handler = {

GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \

{                                                                             \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_reset_fpstatus();                                                     \

GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \

{                                                                             \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_reset_fpstatus();                                                     \

GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \

{                                                                             \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_reset_fpstatus();                                                     \

GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \

{                                                                             \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_reset_fpstatus();                                                     \

GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \

{                                                                             \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_reset_fpstatus();                                                     \

GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_reset_fpstatus();

GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_reset_fpstatus();

GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_reset_fpstatus();

GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_reset_fpstatus();

GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_reset_fpstatus();

GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);

    int bfa;

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_optimize_fprf();

GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)

{

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_optimize_fprf();

    uint8_t crb;

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    crb = 32 - (crbD(ctx->opcode) >> 2);

    uint8_t crb;

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    crb = 32 - (crbD(ctx->opcode) >> 2);

    TCGv_i32 t0;

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    gen_optimize_fprf();

    TCGv_i32 t1;

    if (unlikely(!ctx->fpu_enabled)) {

        return;

    }

    bf = crbD(ctx->opcode) >> 2;

    TCGv EA;                                                                  \

    if (unlikely(rA(ctx->opcode) == 0 ||                                      \

                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_INT);                                     \

    TCGv EA;                                                                  \

    if (unlikely(rA(ctx->opcode) == 0 ||                                      \

                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_INT);                                     \

    if (Rc(ctx->opcode)) {

        if (unlikely(rA(ctx->opcode) == 0 ||

                     rA(ctx->opcode) == rD(ctx->opcode))) {

            return;

        }

    }

GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)

{

#if defined(CONFIG_USER_ONLY)

#else

    int ra, rd;

    TCGv EA;

    /* Restore CPU state */

    if (unlikely(ctx->mem_idx == 0)) {

        return;

    }

    ra = rA(ctx->opcode);

    rd = rD(ctx->opcode);

    if (unlikely((rd & 1) || rd == ra)) {

        return;

    }

    if (unlikely(ctx->le_mode)) {

        /* Little-endian mode is not handled */

        return;

    }

    gen_set_access_type(ctx, ACCESS_INT);

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(rA(ctx->opcode) == 0)) {                                     \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_INT);                                     \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(rA(ctx->opcode) == 0)) {                                     \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_INT);                                     \

    rs = rS(ctx->opcode);

    if ((ctx->opcode & 0x3) == 0x2) {

#if defined(CONFIG_USER_ONLY)

#else

        /* stq */

        if (unlikely(ctx->mem_idx == 0)) {

            return;

        }

        if (unlikely(rs & 1)) {

            return;

        }

        if (unlikely(ctx->le_mode)) {

            /* Little-endian mode is not handled */

            return;

        }

        gen_set_access_type(ctx, ACCESS_INT);

        /* std / stdu */

        if (Rc(ctx->opcode)) {

            if (unlikely(rA(ctx->opcode) == 0)) {

                return;

            }

        }

    if (unlikely(((start + nr) > 32  &&

                  start <= ra && (start + nr - 32) > ra) ||

                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {

        return;

    }

    gen_set_access_type(ctx, ACCESS_INT);

/* isync */

GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)

{

}

/* lwarx */

    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));

    tcg_temp_free_i32(t0);

    /* Stop translation, as the CPU is supposed to sleep from now */

}

/***                         Floating-point load                           ***/

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    if (unlikely(rA(ctx->opcode) == 0)) {                                     \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    if (unlikely(rA(ctx->opcode) == 0)) {                                     \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    if (unlikely(rA(ctx->opcode) == 0)) {                                     \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    if (unlikely(rA(ctx->opcode) == 0)) {                                     \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

{                                                                             \

    TCGv EA;                                                                  \

    if (unlikely(!ctx->fpu_enabled)) {                                        \

        return;                                                               \

    }                                                                         \

    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \

                ctx->exception == POWERPC_EXCP_BRANCH) {

                target_ulong tmp = ctx->nip;

                ctx->nip = dest;

                ctx->nip = tmp;

            }

            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {

            }

        }

        tcg_gen_exit_tb(0);

        /* Decrement and test CTR */

        TCGv temp = tcg_temp_new();

        if (unlikely(type == BCOND_CTR)) {

            return;

        }

        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);

GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)

{

#if defined(CONFIG_USER_ONLY)

#else

    /* Restore CPU state */

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_rfi();

#endif

}

GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)

{

#if defined(CONFIG_USER_ONLY)

#else

    /* Restore CPU state */

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_rfid();

#endif

}

GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)

{

#if defined(CONFIG_USER_ONLY)

#else

    /* Restore CPU state */

    if (unlikely(ctx->mem_idx <= 1)) {

        return;

    }

    gen_helper_hrfid();

#endif

}

#endif

    uint32_t lev;

    lev = (ctx->opcode >> 5) & 0x7F;

}

/***                                Trap                                   ***/

GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);

                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",

                       sprn, sprn, ctx->nip);

            }

        }

    } else {

        /* Not defined */

        }

        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",

               sprn, sprn, ctx->nip);

    }

}

GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    if (ctx->opcode & 0x00010000) {

        gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);

        /* Must stop the translation as machine state (may have) changed */

        /* Note that mtmsr is not always defined as context-synchronizing */

    }

#endif

}

GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    if (ctx->opcode & 0x00010000) {

            gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);

        /* Must stop the translation as machine state (may have) changed */

        /* Note that mtmsr is not always defined as context-synchronizing */

    }

#endif

}

            }

            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",

                   sprn, sprn, ctx->nip);

        }

    } else {

        /* Not defined */

        }

        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",

               sprn, sprn, ctx->nip);

    }

}

GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv EA, val;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    EA = tcg_temp_new();

GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_const_tl(SR(ctx->opcode));

GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_const_tl(SR(ctx->opcode));

GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_const_tl(SR(ctx->opcode));

             PPC_SEGMENT_64B)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_const_tl(SR(ctx->opcode));

             PPC_SEGMENT_64B)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_tlbia();

GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

#if defined(TARGET_PPC64)

GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* This has no effect: it should ensure that all previous

     * tlbie have completed

     */

#endif

}

GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_slbia();

GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);

GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)

{

    /* XXX: TODO */

}

/* esa */

GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)

{

    /* XXX: TODO */

}

/* mfrom */

GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);

GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);

GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);

GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);

GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);

{

    /* Cache line invalidate: privileged and treated as no-op */

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

#endif

GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)

{

#if defined(CONFIG_USER_ONLY)

#else

    int ra = rA(ctx->opcode);

    int rd = rD(ctx->opcode);

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_helper_rfsvc();

#endif

}

GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)

{

    /* XXX: TODO */

}

/* XXX: not implemented on 440 ? */

GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv dcrn;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* NIP cannot be restored if the memory exception comes from an helper */

GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv dcrn;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* NIP cannot be restored if the memory exception comes from an helper */

GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* NIP cannot be restored if the memory exception comes from an helper */

GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* NIP cannot be restored if the memory exception comes from an helper */

GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* interpreted as no-op */

GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv EA, val;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    gen_set_access_type(ctx, ACCESS_CACHE);

GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* interpreted as no-op */

GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* interpreted as no-op */

GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* Restore CPU state */

    gen_helper_40x_rfci();

#endif

}

GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* Restore CPU state */

    gen_helper_rfci();

#endif

}

GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* Restore CPU state */

    gen_helper_rfdi();

#endif

}

GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    /* Restore CPU state */

    gen_helper_rfmci();

#endif

}

GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    switch (rB(ctx->opcode)) {

        gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);

        break;

    default:

        break;

    }

#endif

GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    TCGv t0;

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    t0 = tcg_temp_new();

GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)

{

#if defined(CONFIG_USER_ONLY)

#else

    if (unlikely(!ctx->mem_idx)) {

        return;

    }

    switch (rB(ctx->opcode)) {

        gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);

        break;

    default:

        break;

    }

#endif