Revision e0bcb9ca
| b/hw/sh7750.c | ||
|---|---|---|
| 396 | 396 |
portb_changed(s, temp); |
| 397 | 397 |
return; |
| 398 | 398 |
case SH7750_MMUCR_A7: |
| 399 |
s->cpu->mmucr = mem_value; |
|
| 400 |
return; |
|
| 399 |
if (mem_value & MMUCR_TI) {
|
|
| 400 |
cpu_sh4_invalidate_tlb(s->cpu); |
|
| 401 |
} |
|
| 402 |
s->cpu->mmucr = mem_value & ~MMUCR_TI; |
|
| 403 |
return; |
|
| 401 | 404 |
case SH7750_PTEH_A7: |
| 402 | 405 |
/* If asid changes, clear all registered tlb entries. */ |
| 403 | 406 |
if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) |
| b/target-sh4/cpu.h | ||
|---|---|---|
| 167 | 167 |
void do_interrupt(CPUSH4State * env); |
| 168 | 168 |
|
| 169 | 169 |
void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 170 |
void cpu_sh4_invalidate_tlb(CPUSH4State *s); |
|
| 170 | 171 |
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, |
| 171 | 172 |
uint32_t mem_value); |
| 172 | 173 |
|
| ... | ... | |
| 222 | 223 |
/* MMU control register */ |
| 223 | 224 |
#define MMUCR 0x1F000010 |
| 224 | 225 |
#define MMUCR_AT (1<<0) |
| 226 |
#define MMUCR_TI (1<<2) |
|
| 225 | 227 |
#define MMUCR_SV (1<<8) |
| 226 | 228 |
#define MMUCR_URC_BITS (6) |
| 227 | 229 |
#define MMUCR_URC_OFFSET (10) |
| b/target-sh4/helper.c | ||
|---|---|---|
| 574 | 574 |
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
| 575 | 575 |
} |
| 576 | 576 |
|
| 577 |
void cpu_sh4_invalidate_tlb(CPUSH4State *s) |
|
| 578 |
{
|
|
| 579 |
int i; |
|
| 580 |
|
|
| 581 |
/* UTLB */ |
|
| 582 |
for (i = 0; i < UTLB_SIZE; i++) {
|
|
| 583 |
tlb_t * entry = &s->utlb[i]; |
|
| 584 |
entry->v = 0; |
|
| 585 |
} |
|
| 586 |
/* ITLB */ |
|
| 587 |
for (i = 0; i < UTLB_SIZE; i++) {
|
|
| 588 |
tlb_t * entry = &s->utlb[i]; |
|
| 589 |
entry->v = 0; |
|
| 590 |
} |
|
| 591 |
|
|
| 592 |
tlb_flush(s, 1); |
|
| 593 |
} |
|
| 594 |
|
|
| 577 | 595 |
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, |
| 578 | 596 |
uint32_t mem_value) |
| 579 | 597 |
{
|
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