Revision e1571908

b/target-ppc/cpu.h
829 829
#include "cpu-all.h"
830 830

  
831 831
/*****************************************************************************/
832
/* Registers definitions */
832
/* CRF definitions */
833
#define CRF_LT  3
834
#define CRF_GT  2
835
#define CRF_EQ  1
836
#define CRF_SO  0
837

  
838
/* XER definitions */
833 839
#define XER_SO  31
834 840
#define XER_OV  30
835 841
#define XER_CA  29
b/target-ppc/helper.h
2 2
#define DEF_HELPER(ret, name, params) ret name params;
3 3
#endif
4 4

  
5
DEF_HELPER(uint32_t, helper_fcmpo, (void))
6
DEF_HELPER(uint32_t, helper_fcmpu, (void))
7

  
8
DEF_HELPER(uint32_t, helper_load_cr, (void))
9
DEF_HELPER(void, helper_store_cr, (target_ulong, uint32_t))
b/target-ppc/op.c
26 26
#include "helper_regs.h"
27 27
#include "op_helper.h"
28 28

  
29
/* PowerPC state maintenance operations */
30
/* set_Rc0 */
31
void OPPROTO op_set_Rc0 (void)
32
{
33
    env->crf[0] = T0 | xer_so;
34
    RETURN();
35
}
36

  
37 29
/* Generate exceptions */
38 30
void OPPROTO op_raise_exception_err (void)
39 31
{
......
46 38
}
47 39

  
48 40
/* Load/store special registers */
49
void OPPROTO op_load_cr (void)
50
{
51
    do_load_cr();
52
    RETURN();
53
}
54

  
55
void OPPROTO op_store_cr (void)
56
{
57
    do_store_cr(PARAM1);
58
    RETURN();
59
}
60

  
61 41
#if defined(TARGET_PPC64)
62 42
void OPPROTO op_store_pri (void)
63 43
{
......
337 317
    RETURN();
338 318
}
339 319

  
340
void OPPROTO op_load_fpscr_T0 (void)
341
{
342
    T0 = (env->fpscr >> PARAM1) & 0xF;
343
    RETURN();
344
}
345

  
346
void OPPROTO op_load_fpcc (void)
347
{
348
    T0 = fpscr_fpcc;
349
    RETURN();
350
}
351

  
352 320
void OPPROTO op_fpscr_resetbit (void)
353 321
{
354 322
    env->fpscr &= PARAM1;
......
953 921
}
954 922
#endif
955 923

  
956
/***                           Integer comparison                          ***/
957
/* compare */
958
void OPPROTO op_cmp (void)
959
{
960
    if ((int32_t)T0 < (int32_t)T1) {
961
        T0 = 0x08;
962
    } else if ((int32_t)T0 > (int32_t)T1) {
963
        T0 = 0x04;
964
    } else {
965
        T0 = 0x02;
966
    }
967
    T0 |= xer_so;
968
    RETURN();
969
}
970

  
971
#if defined(TARGET_PPC64)
972
void OPPROTO op_cmp_64 (void)
973
{
974
    if ((int64_t)T0 < (int64_t)T1) {
975
        T0 = 0x08;
976
    } else if ((int64_t)T0 > (int64_t)T1) {
977
        T0 = 0x04;
978
    } else {
979
        T0 = 0x02;
980
    }
981
    T0 |= xer_so;
982
    RETURN();
983
}
984
#endif
985

  
986
/* compare immediate */
987
void OPPROTO op_cmpi (void)
988
{
989
    if ((int32_t)T0 < (int32_t)PARAM1) {
990
        T0 = 0x08;
991
    } else if ((int32_t)T0 > (int32_t)PARAM1) {
992
        T0 = 0x04;
993
    } else {
994
        T0 = 0x02;
995
    }
996
    T0 |= xer_so;
997
    RETURN();
998
}
999

  
1000
#if defined(TARGET_PPC64)
1001
void OPPROTO op_cmpi_64 (void)
1002
{
1003
    if ((int64_t)T0 < (int64_t)((int32_t)PARAM1)) {
1004
        T0 = 0x08;
1005
    } else if ((int64_t)T0 > (int64_t)((int32_t)PARAM1)) {
1006
        T0 = 0x04;
1007
    } else {
1008
        T0 = 0x02;
1009
    }
1010
    T0 |= xer_so;
1011
    RETURN();
1012
}
1013
#endif
1014

  
1015
/* compare logical */
1016
void OPPROTO op_cmpl (void)
1017
{
1018
    if ((uint32_t)T0 < (uint32_t)T1) {
1019
        T0 = 0x08;
1020
    } else if ((uint32_t)T0 > (uint32_t)T1) {
1021
        T0 = 0x04;
1022
    } else {
1023
        T0 = 0x02;
1024
    }
1025
    T0 |= xer_so;
1026
    RETURN();
1027
}
1028

  
1029
#if defined(TARGET_PPC64)
1030
void OPPROTO op_cmpl_64 (void)
1031
{
1032
    if ((uint64_t)T0 < (uint64_t)T1) {
1033
        T0 = 0x08;
1034
    } else if ((uint64_t)T0 > (uint64_t)T1) {
1035
        T0 = 0x04;
1036
    } else {
1037
        T0 = 0x02;
1038
    }
1039
    T0 |= xer_so;
1040
    RETURN();
1041
}
1042
#endif
1043

  
1044
/* compare logical immediate */
1045
void OPPROTO op_cmpli (void)
1046
{
1047
    if ((uint32_t)T0 < (uint32_t)PARAM1) {
1048
        T0 = 0x08;
1049
    } else if ((uint32_t)T0 > (uint32_t)PARAM1) {
1050
        T0 = 0x04;
1051
    } else {
1052
        T0 = 0x02;
1053
    }
1054
    T0 |= xer_so;
1055
    RETURN();
1056
}
1057

  
1058
#if defined(TARGET_PPC64)
1059
void OPPROTO op_cmpli_64 (void)
1060
{
1061
    if ((uint64_t)T0 < (uint64_t)PARAM1) {
1062
        T0 = 0x08;
1063
    } else if ((uint64_t)T0 > (uint64_t)PARAM1) {
1064
        T0 = 0x04;
1065
    } else {
1066
        T0 = 0x02;
1067
    }
1068
    T0 |= xer_so;
1069
    RETURN();
1070
}
1071
#endif
1072

  
1073
void OPPROTO op_isel (void)
1074
{
1075
    if (T0)
1076
        T0 = T1;
1077
    else
1078
        T0 = T2;
1079
    RETURN();
1080
}
1081

  
1082 924
void OPPROTO op_popcntb (void)
1083 925
{
1084 926
    do_popcntb();
......
1339 1181
    RETURN();
1340 1182
}
1341 1183

  
1342
void OPPROTO op_sli_T1 (void)
1343
{
1344
    T1 = T1 << PARAM1;
1345
    RETURN();
1346
}
1347

  
1348 1184
void OPPROTO op_srl_T0_T1 (void)
1349 1185
{
1350 1186
    T0 = (uint32_t)T0 >> T1;
......
1579 1415
    RETURN();
1580 1416
}
1581 1417

  
1582
/***                         Floating-Point compare                        ***/
1583
/* fcmpu */
1584
void OPPROTO op_fcmpu (void)
1585
{
1586
    do_fcmpu();
1587
    RETURN();
1588
}
1589

  
1590
/* fcmpo */
1591
void OPPROTO op_fcmpo (void)
1592
{
1593
    do_fcmpo();
1594
    RETURN();
1595
}
1596

  
1597 1418
/***                         Floating-point move                           ***/
1598 1419
/* fabs */
1599 1420
void OPPROTO op_fabs (void)
b/target-ppc/op_helper.c
62 62

  
63 63
/*****************************************************************************/
64 64
/* Registers load and stores */
65
void do_load_cr (void)
65
uint32_t helper_load_cr (void)
66 66
{
67
    T0 = (env->crf[0] << 28) |
68
        (env->crf[1] << 24) |
69
        (env->crf[2] << 20) |
70
        (env->crf[3] << 16) |
71
        (env->crf[4] << 12) |
72
        (env->crf[5] << 8) |
73
        (env->crf[6] << 4) |
74
        (env->crf[7] << 0);
67
    return (env->crf[0] << 28) |
68
           (env->crf[1] << 24) |
69
           (env->crf[2] << 20) |
70
           (env->crf[3] << 16) |
71
           (env->crf[4] << 12) |
72
           (env->crf[5] << 8) |
73
           (env->crf[6] << 4) |
74
           (env->crf[7] << 0);
75 75
}
76 76

  
77
void do_store_cr (uint32_t mask)
77
void helper_store_cr (target_ulong val, uint32_t mask)
78 78
{
79 79
    int i, sh;
80 80

  
81 81
    for (i = 0, sh = 7; i < 8; i++, sh--) {
82 82
        if (mask & (1 << sh))
83
            env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
83
            env->crf[i] = (val >> (sh * 4)) & 0xFUL;
84 84
    }
85 85
}
86 86

  
......
1364 1364
        FT0 = FT2;
1365 1365
}
1366 1366

  
1367
void do_fcmpu (void)
1367
uint32_t helper_fcmpu (void)
1368 1368
{
1369
    uint32_t ret = 0;
1370

  
1369 1371
    if (unlikely(float64_is_signaling_nan(FT0) ||
1370 1372
                 float64_is_signaling_nan(FT1))) {
1371 1373
        /* sNaN comparison */
1372 1374
        fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1373 1375
    } else {
1374 1376
        if (float64_lt(FT0, FT1, &env->fp_status)) {
1375
            T0 = 0x08UL;
1377
            ret = 0x08UL;
1376 1378
        } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1377
            T0 = 0x04UL;
1379
            ret = 0x04UL;
1378 1380
        } else {
1379
            T0 = 0x02UL;
1381
            ret = 0x02UL;
1380 1382
        }
1381 1383
    }
1382 1384
    env->fpscr &= ~(0x0F << FPSCR_FPRF);
1383
    env->fpscr |= T0 << FPSCR_FPRF;
1385
    env->fpscr |= ret << FPSCR_FPRF;
1386
    return ret;
1384 1387
}
1385 1388

  
1386
void do_fcmpo (void)
1389
uint32_t helper_fcmpo (void)
1387 1390
{
1391
    uint32_t ret = 0;
1392

  
1388 1393
    if (unlikely(float64_is_nan(FT0) ||
1389 1394
                 float64_is_nan(FT1))) {
1390 1395
        if (float64_is_signaling_nan(FT0) ||
......
1398 1403
        }
1399 1404
    } else {
1400 1405
        if (float64_lt(FT0, FT1, &env->fp_status)) {
1401
            T0 = 0x08UL;
1406
            ret = 0x08UL;
1402 1407
        } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1403
            T0 = 0x04UL;
1408
            ret = 0x04UL;
1404 1409
        } else {
1405
            T0 = 0x02UL;
1410
            ret = 0x02UL;
1406 1411
        }
1407 1412
    }
1408 1413
    env->fpscr &= ~(0x0F << FPSCR_FPRF);
1409
    env->fpscr |= T0 << FPSCR_FPRF;
1414
    env->fpscr |= ret << FPSCR_FPRF;
1415
    return ret;
1410 1416
}
1411 1417

  
1412 1418
#if !defined (CONFIG_USER_ONLY)
b/target-ppc/translate.c
63 63
static TCGv cpu_ctr;
64 64
static TCGv cpu_lr;
65 65
static TCGv cpu_xer;
66
static TCGv cpu_fpscr;
66 67

  
67 68
/* dyngen register indexes */
68 69
static TCGv cpu_T[3];
......
179 180
    cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
180 181
                                 offsetof(CPUState, xer), "xer");
181 182

  
183
    cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184
                                   offsetof(CPUState, fpscr), "fpscr");
185

  
182 186
    /* register helpers */
183 187
#undef DEF_HELPER
184 188
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
......
230 234
#endif
231 235
};
232 236

  
233
static always_inline void gen_set_Rc0 (DisasContext *ctx)
234
{
235
#if defined(TARGET_PPC64)
236
    if (ctx->sf_mode)
237
        gen_op_cmpi_64(0);
238
    else
239
#endif
240
        gen_op_cmpi(0);
241
    gen_op_set_Rc0();
242
}
243

  
244 237
static always_inline void gen_reset_fpstatus (void)
245 238
{
246 239
#ifdef CONFIG_SOFTFLOAT
......
708 701
    .handler = gen_invalid,
709 702
};
710 703

  
704
/***                           Integer comparison                          ***/
705

  
706
static always_inline void gen_op_cmp(TCGv t0, TCGv t1, int s, int crf)
707
{
708
    int l1, l2, l3;
709

  
710
    tcg_gen_shri_i32(cpu_crf[crf], cpu_xer, XER_SO);
711
    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
712

  
713
    l1 = gen_new_label();
714
    l2 = gen_new_label();
715
    l3 = gen_new_label();
716
    if (s) {
717
        tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
718
        tcg_gen_brcond_tl(TCG_COND_GT, t0, t1, l2);
719
    } else {
720
        tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
721
        tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l2);
722
    }
723
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
724
    tcg_gen_br(l3);
725
    gen_set_label(l1);
726
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
727
    tcg_gen_br(l3);
728
    gen_set_label(l2);
729
    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
730
    gen_set_label(l3);
731
}
732

  
733
static always_inline void gen_op_cmpi(TCGv t0, target_ulong t1, int s, int crf)
734
{
735
    TCGv temp = tcg_const_local_tl(t1);
736
    gen_op_cmp(t0, temp, s, crf);
737
    tcg_temp_free(temp);
738
}
739

  
740
#if defined(TARGET_PPC64)
741
static always_inline void gen_op_cmp32(TCGv t0, TCGv t1, int s, int crf)
742
{
743
    TCGv t0_32, t1_32;
744
    t0_32 = tcg_temp_local_new(TCG_TYPE_TL);
745
    t1_32 = tcg_temp_local_new(TCG_TYPE_TL);
746
    if (s) {
747
        tcg_gen_ext32s_tl(t0_32, t0);
748
        tcg_gen_ext32s_tl(t1_32, t1);
749
    } else {
750
        tcg_gen_ext32u_tl(t0_32, t0);
751
        tcg_gen_ext32u_tl(t1_32, t1);
752
    }
753
    gen_op_cmp(t0_32, t1_32, s, crf);
754
    tcg_temp_free(t1_32);
755
    tcg_temp_free(t0_32);
756
}
757

  
758
static always_inline void gen_op_cmpi32(TCGv t0, target_ulong t1, int s, int crf)
759
{
760
    TCGv temp = tcg_const_local_tl(t1);
761
    gen_op_cmp32(t0, temp, s, crf);
762
    tcg_temp_free(temp);
763
}
764
#endif
765

  
766
static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
767
{
768
#if defined(TARGET_PPC64)
769
    if (!(ctx->sf_mode))
770
        gen_op_cmpi32(reg, 0, 1, 0);
771
    else
772
#endif
773
        gen_op_cmpi(reg, 0, 1, 0);
774
}
775

  
776
/* cmp */
777
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
778
{
779
#if defined(TARGET_PPC64)
780
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
781
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
782
                     1, crfD(ctx->opcode));
783
    else
784
#endif
785
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786
                   1, crfD(ctx->opcode));
787
}
788

  
789
/* cmpi */
790
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
791
{
792
#if defined(TARGET_PPC64)
793
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
794
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
795
                      1, crfD(ctx->opcode));
796
    else
797
#endif
798
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799
                    1, crfD(ctx->opcode));
800
}
801

  
802
/* cmpl */
803
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
804
{
805
#if defined(TARGET_PPC64)
806
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
807
        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
808
                     0, crfD(ctx->opcode));
809
    else
810
#endif
811
        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812
                   0, crfD(ctx->opcode));
813
}
814

  
815
/* cmpli */
816
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
817
{
818
#if defined(TARGET_PPC64)
819
    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
820
        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
821
                      0, crfD(ctx->opcode));
822
    else
823
#endif
824
        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825
                    0, crfD(ctx->opcode));
826
}
827

  
828
/* isel (PowerPC 2.03 specification) */
829
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
830
{
831
    int l1, l2;
832
    uint32_t bi = rC(ctx->opcode);
833
    uint32_t mask;
834
    TCGv temp;
835

  
836
    l1 = gen_new_label();
837
    l2 = gen_new_label();
838

  
839
    mask = 1 << (3 - (bi & 0x03));
840
    temp = tcg_temp_new(TCG_TYPE_I32);
841
    tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
842
    tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
843
    if (rA(ctx->opcode) == 0)
844
        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
845
    else
846
        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
847
    tcg_gen_br(l2);
848
    gen_set_label(l1);
849
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
850
    gen_set_label(l2);
851
}
852

  
711 853
/***                           Integer arithmetic                          ***/
712 854
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
713 855
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
......
717 859
    gen_op_##name();                                                          \
718 860
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
719 861
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
720
        gen_set_Rc0(ctx);                                                     \
862
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
721 863
}
722 864

  
723 865
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
......
728 870
    gen_op_##name();                                                          \
729 871
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
730 872
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
731
        gen_set_Rc0(ctx);                                                     \
873
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
732 874
}
733 875

  
734 876
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
......
738 880
    gen_op_##name();                                                          \
739 881
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
740 882
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
741
        gen_set_Rc0(ctx);                                                     \
883
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
742 884
}
743 885
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
744 886
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
......
747 889
    gen_op_##name();                                                          \
748 890
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
749 891
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
750
        gen_set_Rc0(ctx);                                                     \
892
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
751 893
}
752 894

  
753 895
/* Two operands arithmetic functions */
......
776 918
        gen_op_##name();                                                      \
777 919
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
778 920
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
779
        gen_set_Rc0(ctx);                                                     \
921
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
780 922
}
781 923

  
782 924
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
......
790 932
        gen_op_##name();                                                      \
791 933
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
792 934
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
793
        gen_set_Rc0(ctx);                                                     \
935
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
794 936
}
795 937

  
796 938
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
......
803 945
        gen_op_##name();                                                      \
804 946
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
805 947
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
806
        gen_set_Rc0(ctx);                                                     \
948
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
807 949
}
808 950
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
809 951
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
......
815 957
        gen_op_##name();                                                      \
816 958
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
817 959
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
818
        gen_set_Rc0(ctx);                                                     \
960
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
819 961
}
820 962

  
821 963
/* Two operands arithmetic functions */
......
1084 1226
        tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
1085 1227
    }
1086 1228
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1087
    gen_set_Rc0(ctx);
1229
    gen_set_Rc0(ctx, cpu_T[0]);
1088 1230
}
1089 1231
/* addis */
1090 1232
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
......
1134 1276
GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
1135 1277
#endif
1136 1278

  
1137
/***                           Integer comparison                          ***/
1138
#if defined(TARGET_PPC64)
1139
#define GEN_CMP(name, opc, type)                                              \
1140
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1141
{                                                                             \
1142
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
1143
    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
1144
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
1145
        gen_op_##name##_64();                                                 \
1146
    else                                                                      \
1147
        gen_op_##name();                                                      \
1148
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);              \
1149
}
1150
#else
1151
#define GEN_CMP(name, opc, type)                                              \
1152
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1153
{                                                                             \
1154
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
1155
    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
1156
    gen_op_##name();                                                          \
1157
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);              \
1158
}
1159
#endif
1160

  
1161
/* cmp */
1162
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1163
/* cmpi */
1164
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1165
{
1166
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1167
#if defined(TARGET_PPC64)
1168
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1169
        gen_op_cmpi_64(SIMM(ctx->opcode));
1170
    else
1171
#endif
1172
        gen_op_cmpi(SIMM(ctx->opcode));
1173
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
1174
}
1175
/* cmpl */
1176
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1177
/* cmpli */
1178
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1179
{
1180
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
1181
#if defined(TARGET_PPC64)
1182
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1183
        gen_op_cmpli_64(UIMM(ctx->opcode));
1184
    else
1185
#endif
1186
        gen_op_cmpli(UIMM(ctx->opcode));
1187
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
1188
}
1189

  
1190
/* isel (PowerPC 2.03 specification) */
1191
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
1192
{
1193
    uint32_t bi = rC(ctx->opcode);
1194
    uint32_t mask;
1195

  
1196
    if (rA(ctx->opcode) == 0) {
1197
        tcg_gen_movi_tl(cpu_T[0], 0);
1198
    } else {
1199
        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
1200
    }
1201
    tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
1202
    mask = 1 << (3 - (bi & 0x03));
1203
    tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
1204
    gen_op_test_true(mask);
1205
    gen_op_isel();
1206
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
1207
}
1208

  
1209 1279
/***                            Integer logical                            ***/
1210 1280
#define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
1211 1281
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
......
1215 1285
    gen_op_##name();                                                          \
1216 1286
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
1217 1287
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1218
        gen_set_Rc0(ctx);                                                     \
1288
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
1219 1289
}
1220 1290
#define GEN_LOGICAL2(name, opc, type)                                         \
1221 1291
__GEN_LOGICAL2(name, 0x1C, opc, type)
......
1227 1297
    gen_op_##name();                                                          \
1228 1298
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
1229 1299
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1230
        gen_set_Rc0(ctx);                                                     \
1300
        gen_set_Rc0(ctx, cpu_T[0]);                                           \
1231 1301
}
1232 1302

  
1233 1303
/* and & and. */
......
1240 1310
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1241 1311
    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
1242 1312
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1243
    gen_set_Rc0(ctx);
1313
    gen_set_Rc0(ctx, cpu_T[0]);
1244 1314
}
1245 1315
/* andis. */
1246 1316
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
......
1248 1318
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1249 1319
    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
1250 1320
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1251
    gen_set_Rc0(ctx);
1321
    gen_set_Rc0(ctx, cpu_T[0]);
1252 1322
}
1253 1323

  
1254 1324
/* cntlzw */
......
1281 1351
        }
1282 1352
        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
1283 1353
        if (unlikely(Rc(ctx->opcode) != 0))
1284
            gen_set_Rc0(ctx);
1354
            gen_set_Rc0(ctx, cpu_T[0]);
1285 1355
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1286 1356
        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
1287
        gen_set_Rc0(ctx);
1357
        gen_set_Rc0(ctx, cpu_T[0]);
1288 1358
#if defined(TARGET_PPC64)
1289 1359
    } else {
1290 1360
        switch (rs) {
......
1349 1419
    }
1350 1420
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1351 1421
    if (unlikely(Rc(ctx->opcode) != 0))
1352
        gen_set_Rc0(ctx);
1422
        gen_set_Rc0(ctx, cpu_T[0]);
1353 1423
}
1354 1424
/* ori */
1355 1425
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
......
1467 1537
 do_store:
1468 1538
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1469 1539
    if (unlikely(Rc(ctx->opcode) != 0))
1470
        gen_set_Rc0(ctx);
1540
        gen_set_Rc0(ctx, cpu_T[0]);
1471 1541
}
1472 1542
/* rlwinm & rlwinm. */
1473 1543
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
......
1505 1575
 do_store:
1506 1576
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1507 1577
    if (unlikely(Rc(ctx->opcode) != 0))
1508
        gen_set_Rc0(ctx);
1578
        gen_set_Rc0(ctx, cpu_T[0]);
1509 1579
}
1510 1580
/* rlwnm & rlwnm. */
1511 1581
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
......
1526 1596
    }
1527 1597
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1528 1598
    if (unlikely(Rc(ctx->opcode) != 0))
1529
        gen_set_Rc0(ctx);
1599
        gen_set_Rc0(ctx, cpu_T[0]);
1530 1600
}
1531 1601

  
1532 1602
#if defined(TARGET_PPC64)
......
1588 1658
 do_store:
1589 1659
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1590 1660
    if (unlikely(Rc(ctx->opcode) != 0))
1591
        gen_set_Rc0(ctx);
1661
        gen_set_Rc0(ctx, cpu_T[0]);
1592 1662
}
1593 1663
/* rldicl - rldicl. */
1594 1664
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
......
1632 1702
    }
1633 1703
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1634 1704
    if (unlikely(Rc(ctx->opcode) != 0))
1635
        gen_set_Rc0(ctx);
1705
        gen_set_Rc0(ctx, cpu_T[0]);
1636 1706
}
1637 1707

  
1638 1708
/* rldcl - rldcl. */
......
1682 1752
 do_store:
1683 1753
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1684 1754
    if (unlikely(Rc(ctx->opcode) != 0))
1685
        gen_set_Rc0(ctx);
1755
        gen_set_Rc0(ctx, cpu_T[0]);
1686 1756
}
1687 1757
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1688 1758
#endif
......
1709 1779
    }
1710 1780
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1711 1781
    if (unlikely(Rc(ctx->opcode) != 0))
1712
        gen_set_Rc0(ctx);
1782
        gen_set_Rc0(ctx, cpu_T[0]);
1713 1783
}
1714 1784
/* srw & srw. */
1715 1785
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
......
1736 1806
    }
1737 1807
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
1738 1808
    if (unlikely(Rc(ctx->opcode) != 0))
1739
        gen_set_Rc0(ctx);
1809
        gen_set_Rc0(ctx, cpu_T[0]);
1740 1810
}
1741 1811
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1742 1812
{
......
1947 2017
    tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1948 2018
    tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
1949 2019
    gen_reset_fpstatus();
1950
    gen_op_fcmpo();
1951
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
2020
    tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
1952 2021
    gen_op_float_check_status();
1953 2022
}
1954 2023

  
......
1962 2031
    tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
1963 2032
    tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
1964 2033
    gen_reset_fpstatus();
1965
    gen_op_fcmpu();
1966
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
2034
    tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
1967 2035
    gen_op_float_check_status();
1968 2036
}
1969 2037

  
......
2004 2072
    }
2005 2073
    gen_optimize_fprf();
2006 2074
    bfa = 4 * (7 - crfS(ctx->opcode));
2007
    gen_op_load_fpscr_T0(bfa);
2008
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf);
2075
    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2076
    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2009 2077
    gen_op_fpscr_resetbit(~(0xF << bfa));
2010 2078
}
2011 2079

  
......
2038 2106
    if (likely(crb != 30 && crb != 29))
2039 2107
        gen_op_fpscr_resetbit(~(1 << crb));
2040 2108
    if (unlikely(Rc(ctx->opcode) != 0)) {
2041
        gen_op_load_fpcc();
2042
        gen_op_set_Rc0();
2109
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2043 2110
    }
2044 2111
}
2045 2112

  
......
2059 2126
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2060 2127
        gen_op_fpscr_setbit(crb);
2061 2128
    if (unlikely(Rc(ctx->opcode) != 0)) {
2062
        gen_op_load_fpcc();
2063
        gen_op_set_Rc0();
2129
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2064 2130
    }
2065 2131
    /* We can raise a differed exception */
2066 2132
    gen_op_float_check_status();
......
2078 2144
    gen_reset_fpstatus();
2079 2145
    gen_op_store_fpscr(FM(ctx->opcode));
2080 2146
    if (unlikely(Rc(ctx->opcode) != 0)) {
2081
        gen_op_load_fpcc();
2082
        gen_op_set_Rc0();
2147
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2083 2148
    }
2084 2149
    /* We can raise a differed exception */
2085 2150
    gen_op_float_check_status();
......
2101 2166
    gen_reset_fpstatus();
2102 2167
    gen_op_store_fpscr(1 << sh);
2103 2168
    if (unlikely(Rc(ctx->opcode) != 0)) {
2104
        gen_op_load_fpcc();
2105
        gen_op_set_Rc0();
2169
        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2106 2170
    }
2107 2171
    /* We can raise a differed exception */
2108 2172
    gen_op_float_check_status();
......
3356 3420
}
3357 3421

  
3358 3422
/***                      Condition register logical                       ***/
3359
#define GEN_CRLOGIC(op, opc)                                                  \
3360
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
3423
#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3424
GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                   \
3361 3425
{                                                                             \
3362 3426
    uint8_t bitmask;                                                          \
3363 3427
    int sh;                                                                   \
3364
    tcg_gen_mov_i32(cpu_T[0], cpu_crf[crbA(ctx->opcode) >> 2]);               \
3428
    TCGv temp1, temp2;                                                        \
3365 3429
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3430
    temp1 = tcg_temp_new(TCG_TYPE_I32);                                       \
3366 3431
    if (sh > 0)                                                               \
3367
        gen_op_srli_T0(sh);                                                   \
3432
        tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh);         \
3368 3433
    else if (sh < 0)                                                          \
3369
        gen_op_sli_T0(-sh);                                                   \
3370
    tcg_gen_mov_i32(cpu_T[1], cpu_crf[crbB(ctx->opcode) >> 2]);               \
3434
        tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh);        \
3435
    else                                                                      \
3436
        tcg_gen_mov_i32(temp1, cpu_crf[crbB(ctx->opcode) >> 2]);              \
3437
    temp2 = tcg_temp_new(TCG_TYPE_I32);                                       \
3371 3438
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3372 3439
    if (sh > 0)                                                               \
3373
        gen_op_srli_T1(sh);                                                   \
3440
        tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh);         \
3374 3441
    else if (sh < 0)                                                          \
3375
        gen_op_sli_T1(-sh);                                                   \
3376
    gen_op_##op();                                                            \
3442
        tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh);        \
3443
    else                                                                      \
3444
        tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]);              \
3445
    tcg_op(temp1, temp1, temp2);                                              \
3377 3446
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3378
    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask);                             \
3379
    tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);    \
3380
    gen_op_or();                                                              \
3381
    tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf);         \
3447
    tcg_gen_andi_i32(temp1, temp1, bitmask);                                  \
3448
    tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);       \
3449
    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2);            \
3450
    tcg_temp_free(temp1);                                                     \
3451
    tcg_temp_free(temp2);                                                     \
3382 3452
}
3383 3453

  
3384 3454
/* crand */
3385
GEN_CRLOGIC(and, 0x08);
3455
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3386 3456
/* crandc */
3387
GEN_CRLOGIC(andc, 0x04);
3457
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3388 3458
/* creqv */
3389
GEN_CRLOGIC(eqv, 0x09);
3459
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3390 3460
/* crnand */
3391
GEN_CRLOGIC(nand, 0x07);
3461
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3392 3462
/* crnor */
3393
GEN_CRLOGIC(nor, 0x01);
3463
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3394 3464
/* cror */
3395
GEN_CRLOGIC(or, 0x0E);
3465
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3396 3466
/* crorc */
3397
GEN_CRLOGIC(orc, 0x0D);
3467
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3398 3468
/* crxor */
3399
GEN_CRLOGIC(xor, 0x06);
3469
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3400 3470
/* mcrf */
3401 3471
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3402 3472
{
......
3527 3597
        crm = CRM(ctx->opcode);
3528 3598
        if (likely((crm ^ (crm - 1)) == 0)) {
3529 3599
            crn = ffs(crm);
3530
            tcg_gen_mov_i32(cpu_T[0], cpu_crf[7 - crn]);
3600
            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3531 3601
        }
3532 3602
    } else {
3533
        gen_op_load_cr();
3603
        tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
3534 3604
    }
3535
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3536 3605
}
3537 3606

  
3538 3607
/* mfmsr */
......
3624 3693
{
3625 3694
    uint32_t crm, crn;
3626 3695

  
3627
    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3628 3696
    crm = CRM(ctx->opcode);
3629 3697
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3630 3698
        crn = ffs(crm);
3631
        gen_op_srli_T0(crn * 4);
3632
        tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_T[0], 0xf);
3699
        tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3700
        tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3633 3701
    } else {
3634
        gen_op_store_cr(crm);
3702
        TCGv temp = tcg_const_tl(crm);
3703
        tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);
3704
        tcg_temp_free(temp);
3635 3705
    }
3636 3706
}
3637 3707

  
......
4183 4253
    gen_op_POWER_abs();
4184 4254
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4185 4255
    if (unlikely(Rc(ctx->opcode) != 0))
4186
        gen_set_Rc0(ctx);
4256
        gen_set_Rc0(ctx, cpu_T[0]);
4187 4257
}
4188 4258

  
4189 4259
/* abso - abso. */
......
4193 4263
    gen_op_POWER_abso();
4194 4264
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4195 4265
    if (unlikely(Rc(ctx->opcode) != 0))
4196
        gen_set_Rc0(ctx);
4266
        gen_set_Rc0(ctx, cpu_T[0]);
4197 4267
}
4198 4268

  
4199 4269
/* clcs */
......
4213 4283
    gen_op_POWER_div();
4214 4284
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4215 4285
    if (unlikely(Rc(ctx->opcode) != 0))
4216
        gen_set_Rc0(ctx);
4286
        gen_set_Rc0(ctx, cpu_T[0]);
4217 4287
}
4218 4288

  
4219 4289
/* divo - divo. */
......
4224 4294
    gen_op_POWER_divo();
4225 4295
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4226 4296
    if (unlikely(Rc(ctx->opcode) != 0))
4227
        gen_set_Rc0(ctx);
4297
        gen_set_Rc0(ctx, cpu_T[0]);
4228 4298
}
4229 4299

  
4230 4300
/* divs - divs. */
......
4235 4305
    gen_op_POWER_divs();
4236 4306
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4237 4307
    if (unlikely(Rc(ctx->opcode) != 0))
4238
        gen_set_Rc0(ctx);
4308
        gen_set_Rc0(ctx, cpu_T[0]);
4239 4309
}
4240 4310

  
4241 4311
/* divso - divso. */
......
4246 4316
    gen_op_POWER_divso();
4247 4317
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4248 4318
    if (unlikely(Rc(ctx->opcode) != 0))
4249
        gen_set_Rc0(ctx);
4319
        gen_set_Rc0(ctx, cpu_T[0]);
4250 4320
}
4251 4321

  
4252 4322
/* doz - doz. */
......
4257 4327
    gen_op_POWER_doz();
4258 4328
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4259 4329
    if (unlikely(Rc(ctx->opcode) != 0))
4260
        gen_set_Rc0(ctx);
4330
        gen_set_Rc0(ctx, cpu_T[0]);
4261 4331
}
4262 4332

  
4263 4333
/* dozo - dozo. */
......
4268 4338
    gen_op_POWER_dozo();
4269 4339
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4270 4340
    if (unlikely(Rc(ctx->opcode) != 0))
4271
        gen_set_Rc0(ctx);
4341
        gen_set_Rc0(ctx, cpu_T[0]);
4272 4342
}
4273 4343

  
4274 4344
/* dozi */
......
4320 4390
    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4321 4391
    tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
4322 4392
    if (unlikely(Rc(ctx->opcode) != 0))
4323
        gen_set_Rc0(ctx);
4393
        gen_set_Rc0(ctx, cpu_T[0]);
4324 4394
}
4325 4395

  
4326 4396
/* maskg - maskg. */
......
4331 4401
    gen_op_POWER_maskg();
4332 4402
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4333 4403
    if (unlikely(Rc(ctx->opcode) != 0))
4334
        gen_set_Rc0(ctx);
4404
        gen_set_Rc0(ctx, cpu_T[0]);
4335 4405
}
4336 4406

  
4337 4407
/* maskir - maskir. */
......
4343 4413
    gen_op_POWER_maskir();
4344 4414
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4345 4415
    if (unlikely(Rc(ctx->opcode) != 0))
4346
        gen_set_Rc0(ctx);
4416
        gen_set_Rc0(ctx, cpu_T[0]);
4347 4417
}
4348 4418

  
4349 4419
/* mul - mul. */
......
4354 4424
    gen_op_POWER_mul();
4355 4425
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4356 4426
    if (unlikely(Rc(ctx->opcode) != 0))
4357
        gen_set_Rc0(ctx);
4427
        gen_set_Rc0(ctx, cpu_T[0]);
4358 4428
}
4359 4429

  
4360 4430
/* mulo - mulo. */
......
4365 4435
    gen_op_POWER_mulo();
4366 4436
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4367 4437
    if (unlikely(Rc(ctx->opcode) != 0))
4368
        gen_set_Rc0(ctx);
4438
        gen_set_Rc0(ctx, cpu_T[0]);
4369 4439
}
4370 4440

  
4371 4441
/* nabs - nabs. */
......
4375 4445
    gen_op_POWER_nabs();
4376 4446
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4377 4447
    if (unlikely(Rc(ctx->opcode) != 0))
4378
        gen_set_Rc0(ctx);
4448
        gen_set_Rc0(ctx, cpu_T[0]);
4379 4449
}
4380 4450

  
4381 4451
/* nabso - nabso. */
......
4385 4455
    gen_op_POWER_nabso();
4386 4456
    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4387 4457
    if (unlikely(Rc(ctx->opcode) != 0))
4388
        gen_set_Rc0(ctx);
4458
        gen_set_Rc0(ctx, cpu_T[0]);
4389 4459
}
4390 4460

  
4391 4461
/* rlmi - rlmi. */
......
4401 4471
    gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4402 4472
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4403 4473
    if (unlikely(Rc(ctx->opcode) != 0))
4404
        gen_set_Rc0(ctx);
4474
        gen_set_Rc0(ctx, cpu_T[0]);
4405 4475
}
4406 4476

  
4407 4477
/* rrib - rrib. */
......
4413 4483
    gen_op_POWER_rrib();
4414 4484
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4415 4485
    if (unlikely(Rc(ctx->opcode) != 0))
4416
        gen_set_Rc0(ctx);
4486
        gen_set_Rc0(ctx, cpu_T[0]);
4417 4487
}
4418 4488

  
4419 4489
/* sle - sle. */
......
4424 4494
    gen_op_POWER_sle();
4425 4495
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4426 4496
    if (unlikely(Rc(ctx->opcode) != 0))
4427
        gen_set_Rc0(ctx);
4497
        gen_set_Rc0(ctx, cpu_T[0]);
4428 4498
}
4429 4499

  
4430 4500
/* sleq - sleq. */
......
4435 4505
    gen_op_POWER_sleq();
4436 4506
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4437 4507
    if (unlikely(Rc(ctx->opcode) != 0))
4438
        gen_set_Rc0(ctx);
4508
        gen_set_Rc0(ctx, cpu_T[0]);
4439 4509
}
4440 4510

  
4441 4511
/* sliq - sliq. */
......
4446 4516
    gen_op_POWER_sle();
4447 4517
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4448 4518
    if (unlikely(Rc(ctx->opcode) != 0))
4449
        gen_set_Rc0(ctx);
4519
        gen_set_Rc0(ctx, cpu_T[0]);
4450 4520
}
4451 4521

  
4452 4522
/* slliq - slliq. */
......
4457 4527
    gen_op_POWER_sleq();
4458 4528
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4459 4529
    if (unlikely(Rc(ctx->opcode) != 0))
4460
        gen_set_Rc0(ctx);
4530
        gen_set_Rc0(ctx, cpu_T[0]);
4461 4531
}
4462 4532

  
4463 4533
/* sllq - sllq. */
......
4468 4538
    gen_op_POWER_sllq();
4469 4539
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4470 4540
    if (unlikely(Rc(ctx->opcode) != 0))
4471
        gen_set_Rc0(ctx);
4541
        gen_set_Rc0(ctx, cpu_T[0]);
4472 4542
}
4473 4543

  
4474 4544
/* slq - slq. */
......
4479 4549
    gen_op_POWER_slq();
4480 4550
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4481 4551
    if (unlikely(Rc(ctx->opcode) != 0))
4482
        gen_set_Rc0(ctx);
4552
        gen_set_Rc0(ctx, cpu_T[0]);
4483 4553
}
4484 4554

  
4485 4555
/* sraiq - sraiq. */
......
4490 4560
    gen_op_POWER_sraq();
4491 4561
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4492 4562
    if (unlikely(Rc(ctx->opcode) != 0))
4493
        gen_set_Rc0(ctx);
4563
        gen_set_Rc0(ctx, cpu_T[0]);
4494 4564
}
4495 4565

  
4496 4566
/* sraq - sraq. */
......
4501 4571
    gen_op_POWER_sraq();
4502 4572
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4503 4573
    if (unlikely(Rc(ctx->opcode) != 0))
4504
        gen_set_Rc0(ctx);
4574
        gen_set_Rc0(ctx, cpu_T[0]);
4505 4575
}
4506 4576

  
4507 4577
/* sre - sre. */
......
4512 4582
    gen_op_POWER_sre();
4513 4583
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4514 4584
    if (unlikely(Rc(ctx->opcode) != 0))
4515
        gen_set_Rc0(ctx);
4585
        gen_set_Rc0(ctx, cpu_T[0]);
4516 4586
}
4517 4587

  
4518 4588
/* srea - srea. */
......
4523 4593
    gen_op_POWER_srea();
4524 4594
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4525 4595
    if (unlikely(Rc(ctx->opcode) != 0))
4526
        gen_set_Rc0(ctx);
4596
        gen_set_Rc0(ctx, cpu_T[0]);
4527 4597
}
4528 4598

  
4529 4599
/* sreq */
......
4534 4604
    gen_op_POWER_sreq();
4535 4605
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4536 4606
    if (unlikely(Rc(ctx->opcode) != 0))
4537
        gen_set_Rc0(ctx);
4607
        gen_set_Rc0(ctx, cpu_T[0]);
4538 4608
}
4539 4609

  
4540 4610
/* sriq */
......
4545 4615
    gen_op_POWER_srq();
4546 4616
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4547 4617
    if (unlikely(Rc(ctx->opcode) != 0))
4548
        gen_set_Rc0(ctx);
4618
        gen_set_Rc0(ctx, cpu_T[0]);
4549 4619
}
4550 4620

  
4551 4621
/* srliq */
......
4557 4627
    gen_op_POWER_srlq();
4558 4628
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4559 4629
    if (unlikely(Rc(ctx->opcode) != 0))
4560
        gen_set_Rc0(ctx);
4630
        gen_set_Rc0(ctx, cpu_T[0]);
4561 4631
}
4562 4632

  
4563 4633
/* srlq */
......
4568 4638
    gen_op_POWER_srlq();
4569 4639
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4570 4640
    if (unlikely(Rc(ctx->opcode) != 0))
4571
        gen_set_Rc0(ctx);
4641
        gen_set_Rc0(ctx, cpu_T[0]);
4572 4642
}
4573 4643

  
4574 4644
/* srq */
......
4579 4649
    gen_op_POWER_srq();
4580 4650
    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4581 4651
    if (unlikely(Rc(ctx->opcode) != 0))
4582
        gen_set_Rc0(ctx);
4652
        gen_set_Rc0(ctx, cpu_T[0]);
4583 4653
}
4584 4654

  
4585 4655
/* PowerPC 602 specific instructions */
......
4992 5062
    tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
4993 5063
    if (unlikely(Rc) != 0) {
4994 5064
        /* Update Rc0 */
4995
        gen_set_Rc0(ctx);
5065
        gen_set_Rc0(ctx, cpu_T[0]);
4996 5066
    }
4997 5067
}
4998 5068

  

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