root / target-ppc / op_helper.c @ e1571908
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/*
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* PowerPC emulation helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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#include "host-utils.h" |
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#include "helper_regs.h" |
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#include "op_helper.h" |
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#define MEMSUFFIX _raw
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#include "op_helper.h" |
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#include "op_helper_mem.h" |
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper.h" |
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#include "op_helper_mem.h" |
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#define MEMSUFFIX _kernel
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#include "op_helper.h" |
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#include "op_helper_mem.h" |
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#define MEMSUFFIX _hypv
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#include "op_helper.h" |
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#include "op_helper_mem.h" |
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#endif
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//#define DEBUG_OP
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//#define DEBUG_EXCEPTIONS
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//#define DEBUG_SOFTWARE_TLB
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void do_raise_exception_err (uint32_t exception, int error_code) |
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{ |
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#if 0
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printf("Raise exception %3x code : %d\n", exception, error_code);
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#endif
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env->exception_index = exception; |
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env->error_code = error_code; |
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cpu_loop_exit(); |
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} |
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void do_raise_exception (uint32_t exception)
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{ |
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do_raise_exception_err(exception, 0);
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} |
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/*****************************************************************************/
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/* Registers load and stores */
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uint32_t helper_load_cr (void)
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{ |
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return (env->crf[0] << 28) | |
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(env->crf[1] << 24) | |
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(env->crf[2] << 20) | |
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(env->crf[3] << 16) | |
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(env->crf[4] << 12) | |
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(env->crf[5] << 8) | |
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(env->crf[6] << 4) | |
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(env->crf[7] << 0); |
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} |
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void helper_store_cr (target_ulong val, uint32_t mask)
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{ |
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int i, sh;
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for (i = 0, sh = 7; i < 8; i++, sh--) { |
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if (mask & (1 << sh)) |
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env->crf[i] = (val >> (sh * 4)) & 0xFUL; |
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_store_pri (int prio) |
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{ |
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env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
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env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50; |
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} |
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#endif
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target_ulong ppc_load_dump_spr (int sprn)
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{ |
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if (loglevel != 0) { |
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fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n", |
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sprn, sprn, env->spr[sprn]); |
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} |
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return env->spr[sprn];
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} |
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void ppc_store_dump_spr (int sprn, target_ulong val) |
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{ |
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if (loglevel != 0) { |
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fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n", |
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sprn, sprn, env->spr[sprn], val); |
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} |
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env->spr[sprn] = val; |
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} |
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/*****************************************************************************/
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/* Fixed point operations helpers */
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void do_adde (void) |
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{ |
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T2 = T0; |
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T0 += T1 + xer_ca; |
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if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
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(xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_adde_64 (void) |
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{ |
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T2 = T0; |
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T0 += T1 + xer_ca; |
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if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
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(xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
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} |
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#endif
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void do_addmeo (void) |
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{ |
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int ov;
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T1 = T0; |
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T0 += xer_ca + (-1);
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ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
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if (ov) {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} else {
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env->xer &= ~(1 << XER_OV);
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} |
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if (likely((uint32_t)T1 != 0)) |
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env->xer |= (1 << XER_CA);
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} |
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#if defined(TARGET_PPC64)
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void do_addmeo_64 (void) |
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{ |
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int ov;
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T1 = T0; |
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T0 += xer_ca + (-1);
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ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
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if (ov) {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} else {
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env->xer &= ~(1 << XER_OV);
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} |
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if (likely((uint64_t)T1 != 0)) |
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env->xer |= (1 << XER_CA);
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} |
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#endif
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void do_divwo (void) |
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{ |
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if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) || |
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(int32_t)T1 == 0))) {
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env->xer &= ~(1 << XER_OV);
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T0 = (int32_t)T0 / (int32_t)T1; |
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_divdo (void) |
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{ |
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if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == (int64_t)-1LL) || |
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(int64_t)T1 == 0))) {
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env->xer &= ~(1 << XER_OV);
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T0 = (int64_t)T0 / (int64_t)T1; |
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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T0 = UINT64_MAX * ((uint64_t)T0 >> 63);
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} |
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} |
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#endif
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void do_divwuo (void) |
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{ |
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if (likely((uint32_t)T1 != 0)) { |
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env->xer &= ~(1 << XER_OV);
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T0 = (uint32_t)T0 / (uint32_t)T1; |
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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T0 = 0;
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_divduo (void) |
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{ |
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if (likely((uint64_t)T1 != 0)) { |
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env->xer &= ~(1 << XER_OV);
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T0 = (uint64_t)T0 / (uint64_t)T1; |
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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T0 = 0;
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} |
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} |
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#endif
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void do_mullwo (void) |
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{ |
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int64_t res = (int64_t)(int32_t)T0 * (int64_t)(int32_t)T1; |
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if (likely((int32_t)res == res)) {
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env->xer &= ~(1 << XER_OV);
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} |
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T0 = (int32_t)res; |
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} |
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#if defined(TARGET_PPC64)
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void do_mulldo (void) |
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{ |
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int64_t th; |
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uint64_t tl; |
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muls64(&tl, (uint64_t *)&th, T0, T1); |
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T0 = (int64_t)tl; |
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/* If th != 0 && th != -1, then we had an overflow */
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if (likely((uint64_t)(th + 1) <= 1)) { |
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env->xer &= ~(1 << XER_OV);
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} |
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} |
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#endif
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void do_nego (void) |
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{ |
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if (likely((int32_t)T0 != INT32_MIN)) {
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env->xer &= ~(1 << XER_OV);
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T0 = -(int32_t)T0; |
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_nego_64 (void) |
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{ |
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if (likely((int64_t)T0 != INT64_MIN)) {
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env->xer &= ~(1 << XER_OV);
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T0 = -(int64_t)T0; |
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} else {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} |
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} |
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#endif
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void do_subfe (void) |
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{ |
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T0 = T1 + ~T0 + xer_ca; |
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if (likely((uint32_t)T0 >= (uint32_t)T1 &&
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(xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_subfe_64 (void) |
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{ |
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T0 = T1 + ~T0 + xer_ca; |
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if (likely((uint64_t)T0 >= (uint64_t)T1 &&
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(xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
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} |
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#endif
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void do_subfmeo (void) |
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{ |
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int ov;
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T1 = T0; |
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T0 = ~T0 + xer_ca - 1;
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ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
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if (ov) {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} else {
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env->xer &= ~(1 << XER_OV);
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} |
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if (likely((uint32_t)T1 != UINT32_MAX))
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env->xer |= (1 << XER_CA);
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} |
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#if defined(TARGET_PPC64)
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void do_subfmeo_64 (void) |
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{ |
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int ov;
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T1 = T0; |
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T0 = ~T0 + xer_ca - 1;
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ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
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if (ov) {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} else {
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env->xer &= ~(1 << XER_OV);
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} |
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if (likely((uint64_t)T1 != UINT64_MAX))
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env->xer |= (1 << XER_CA);
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} |
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#endif
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void do_subfzeo (void) |
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{ |
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int ov;
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T1 = T0; |
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T0 = ~T0 + xer_ca; |
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ov = (((uint32_t)~T1 ^ UINT32_MAX) & |
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((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
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if (ov) {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} else {
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env->xer &= ~(1 << XER_OV);
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} |
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if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
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} |
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#if defined(TARGET_PPC64)
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void do_subfzeo_64 (void) |
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{ |
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int ov;
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T1 = T0; |
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T0 = ~T0 + xer_ca; |
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ov = (((uint64_t)~T1 ^ UINT64_MAX) & |
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((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
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if (ov) {
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env->xer |= (1 << XER_OV) | (1 << XER_SO); |
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} else {
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env->xer &= ~(1 << XER_OV);
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} |
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if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
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} |
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#endif
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void do_cntlzw (void) |
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{ |
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T0 = clz32(T0); |
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} |
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#if defined(TARGET_PPC64)
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void do_cntlzd (void) |
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{ |
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T0 = clz64(T0); |
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} |
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#endif
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/* shift right arithmetic helper */
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void do_sraw (void) |
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{ |
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int32_t ret; |
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388 |
if (likely(!(T1 & 0x20UL))) { |
389 |
if (likely((uint32_t)T1 != 0)) { |
390 |
ret = (int32_t)T0 >> (T1 & 0x1fUL);
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if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) { |
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env->xer &= ~(1 << XER_CA);
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} else {
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env->xer |= (1 << XER_CA);
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} |
396 |
} else {
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ret = T0; |
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env->xer &= ~(1 << XER_CA);
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} |
400 |
} else {
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ret = UINT32_MAX * ((uint32_t)T0 >> 31);
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if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) { |
403 |
env->xer &= ~(1 << XER_CA);
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} else {
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405 |
env->xer |= (1 << XER_CA);
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406 |
} |
407 |
} |
408 |
T0 = ret; |
409 |
} |
410 |
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411 |
#if defined(TARGET_PPC64)
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412 |
void do_srad (void) |
413 |
{ |
414 |
int64_t ret; |
415 |
|
416 |
if (likely(!(T1 & 0x40UL))) { |
417 |
if (likely((uint64_t)T1 != 0)) { |
418 |
ret = (int64_t)T0 >> (T1 & 0x3FUL);
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419 |
if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) { |
420 |
env->xer &= ~(1 << XER_CA);
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421 |
} else {
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422 |
env->xer |= (1 << XER_CA);
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423 |
} |
424 |
} else {
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425 |
ret = T0; |
426 |
env->xer &= ~(1 << XER_CA);
|
427 |
} |
428 |
} else {
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429 |
ret = UINT64_MAX * ((uint64_t)T0 >> 63);
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430 |
if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) { |
431 |
env->xer &= ~(1 << XER_CA);
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432 |
} else {
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433 |
env->xer |= (1 << XER_CA);
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434 |
} |
435 |
} |
436 |
T0 = ret; |
437 |
} |
438 |
#endif
|
439 |
|
440 |
void do_popcntb (void) |
441 |
{ |
442 |
uint32_t ret; |
443 |
int i;
|
444 |
|
445 |
ret = 0;
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446 |
for (i = 0; i < 32; i += 8) |
447 |
ret |= ctpop8((T0 >> i) & 0xFF) << i;
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448 |
T0 = ret; |
449 |
} |
450 |
|
451 |
#if defined(TARGET_PPC64)
|
452 |
void do_popcntb_64 (void) |
453 |
{ |
454 |
uint64_t ret; |
455 |
int i;
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456 |
|
457 |
ret = 0;
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458 |
for (i = 0; i < 64; i += 8) |
459 |
ret |= ctpop8((T0 >> i) & 0xFF) << i;
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460 |
T0 = ret; |
461 |
} |
462 |
#endif
|
463 |
|
464 |
/*****************************************************************************/
|
465 |
/* Floating point operations helpers */
|
466 |
static always_inline int fpisneg (float64 d) |
467 |
{ |
468 |
CPU_DoubleU u; |
469 |
|
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u.d = d; |
471 |
|
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return u.ll >> 63 != 0; |
473 |
} |
474 |
|
475 |
static always_inline int isden (float64 d) |
476 |
{ |
477 |
CPU_DoubleU u; |
478 |
|
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u.d = d; |
480 |
|
481 |
return ((u.ll >> 52) & 0x7FF) == 0; |
482 |
} |
483 |
|
484 |
static always_inline int iszero (float64 d) |
485 |
{ |
486 |
CPU_DoubleU u; |
487 |
|
488 |
u.d = d; |
489 |
|
490 |
return (u.ll & ~0x8000000000000000ULL) == 0; |
491 |
} |
492 |
|
493 |
static always_inline int isinfinity (float64 d) |
494 |
{ |
495 |
CPU_DoubleU u; |
496 |
|
497 |
u.d = d; |
498 |
|
499 |
return ((u.ll >> 52) & 0x7FF) == 0x7FF && |
500 |
(u.ll & 0x000FFFFFFFFFFFFFULL) == 0; |
501 |
} |
502 |
|
503 |
#ifdef CONFIG_SOFTFLOAT
|
504 |
static always_inline int isfinite (float64 d) |
505 |
{ |
506 |
CPU_DoubleU u; |
507 |
|
508 |
u.d = d; |
509 |
|
510 |
return (((u.ll >> 52) & 0x7FF) != 0x7FF); |
511 |
} |
512 |
|
513 |
static always_inline int isnormal (float64 d) |
514 |
{ |
515 |
CPU_DoubleU u; |
516 |
|
517 |
u.d = d; |
518 |
|
519 |
uint32_t exp = (u.ll >> 52) & 0x7FF; |
520 |
return ((0 < exp) && (exp < 0x7FF)); |
521 |
} |
522 |
#endif
|
523 |
|
524 |
void do_compute_fprf (int set_fprf) |
525 |
{ |
526 |
int isneg;
|
527 |
|
528 |
isneg = fpisneg(FT0); |
529 |
if (unlikely(float64_is_nan(FT0))) {
|
530 |
if (float64_is_signaling_nan(FT0)) {
|
531 |
/* Signaling NaN: flags are undefined */
|
532 |
T0 = 0x00;
|
533 |
} else {
|
534 |
/* Quiet NaN */
|
535 |
T0 = 0x11;
|
536 |
} |
537 |
} else if (unlikely(isinfinity(FT0))) { |
538 |
/* +/- infinity */
|
539 |
if (isneg)
|
540 |
T0 = 0x09;
|
541 |
else
|
542 |
T0 = 0x05;
|
543 |
} else {
|
544 |
if (iszero(FT0)) {
|
545 |
/* +/- zero */
|
546 |
if (isneg)
|
547 |
T0 = 0x12;
|
548 |
else
|
549 |
T0 = 0x02;
|
550 |
} else {
|
551 |
if (isden(FT0)) {
|
552 |
/* Denormalized numbers */
|
553 |
T0 = 0x10;
|
554 |
} else {
|
555 |
/* Normalized numbers */
|
556 |
T0 = 0x00;
|
557 |
} |
558 |
if (isneg) {
|
559 |
T0 |= 0x08;
|
560 |
} else {
|
561 |
T0 |= 0x04;
|
562 |
} |
563 |
} |
564 |
} |
565 |
if (set_fprf) {
|
566 |
/* We update FPSCR_FPRF */
|
567 |
env->fpscr &= ~(0x1F << FPSCR_FPRF);
|
568 |
env->fpscr |= T0 << FPSCR_FPRF; |
569 |
} |
570 |
/* We just need fpcc to update Rc1 */
|
571 |
T0 &= 0xF;
|
572 |
} |
573 |
|
574 |
/* Floating-point invalid operations exception */
|
575 |
static always_inline void fload_invalid_op_excp (int op) |
576 |
{ |
577 |
int ve;
|
578 |
|
579 |
ve = fpscr_ve; |
580 |
if (op & POWERPC_EXCP_FP_VXSNAN) {
|
581 |
/* Operation on signaling NaN */
|
582 |
env->fpscr |= 1 << FPSCR_VXSNAN;
|
583 |
} |
584 |
if (op & POWERPC_EXCP_FP_VXSOFT) {
|
585 |
/* Software-defined condition */
|
586 |
env->fpscr |= 1 << FPSCR_VXSOFT;
|
587 |
} |
588 |
switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
|
589 |
case POWERPC_EXCP_FP_VXISI:
|
590 |
/* Magnitude subtraction of infinities */
|
591 |
env->fpscr |= 1 << FPSCR_VXISI;
|
592 |
goto update_arith;
|
593 |
case POWERPC_EXCP_FP_VXIDI:
|
594 |
/* Division of infinity by infinity */
|
595 |
env->fpscr |= 1 << FPSCR_VXIDI;
|
596 |
goto update_arith;
|
597 |
case POWERPC_EXCP_FP_VXZDZ:
|
598 |
/* Division of zero by zero */
|
599 |
env->fpscr |= 1 << FPSCR_VXZDZ;
|
600 |
goto update_arith;
|
601 |
case POWERPC_EXCP_FP_VXIMZ:
|
602 |
/* Multiplication of zero by infinity */
|
603 |
env->fpscr |= 1 << FPSCR_VXIMZ;
|
604 |
goto update_arith;
|
605 |
case POWERPC_EXCP_FP_VXVC:
|
606 |
/* Ordered comparison of NaN */
|
607 |
env->fpscr |= 1 << FPSCR_VXVC;
|
608 |
env->fpscr &= ~(0xF << FPSCR_FPCC);
|
609 |
env->fpscr |= 0x11 << FPSCR_FPCC;
|
610 |
/* We must update the target FPR before raising the exception */
|
611 |
if (ve != 0) { |
612 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
613 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; |
614 |
/* Update the floating-point enabled exception summary */
|
615 |
env->fpscr |= 1 << FPSCR_FEX;
|
616 |
/* Exception is differed */
|
617 |
ve = 0;
|
618 |
} |
619 |
break;
|
620 |
case POWERPC_EXCP_FP_VXSQRT:
|
621 |
/* Square root of a negative number */
|
622 |
env->fpscr |= 1 << FPSCR_VXSQRT;
|
623 |
update_arith:
|
624 |
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); |
625 |
if (ve == 0) { |
626 |
/* Set the result to quiet NaN */
|
627 |
FT0 = UINT64_MAX; |
628 |
env->fpscr &= ~(0xF << FPSCR_FPCC);
|
629 |
env->fpscr |= 0x11 << FPSCR_FPCC;
|
630 |
} |
631 |
break;
|
632 |
case POWERPC_EXCP_FP_VXCVI:
|
633 |
/* Invalid conversion */
|
634 |
env->fpscr |= 1 << FPSCR_VXCVI;
|
635 |
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); |
636 |
if (ve == 0) { |
637 |
/* Set the result to quiet NaN */
|
638 |
FT0 = UINT64_MAX; |
639 |
env->fpscr &= ~(0xF << FPSCR_FPCC);
|
640 |
env->fpscr |= 0x11 << FPSCR_FPCC;
|
641 |
} |
642 |
break;
|
643 |
} |
644 |
/* Update the floating-point invalid operation summary */
|
645 |
env->fpscr |= 1 << FPSCR_VX;
|
646 |
/* Update the floating-point exception summary */
|
647 |
env->fpscr |= 1 << FPSCR_FX;
|
648 |
if (ve != 0) { |
649 |
/* Update the floating-point enabled exception summary */
|
650 |
env->fpscr |= 1 << FPSCR_FEX;
|
651 |
if (msr_fe0 != 0 || msr_fe1 != 0) |
652 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op); |
653 |
} |
654 |
} |
655 |
|
656 |
static always_inline void float_zero_divide_excp (void) |
657 |
{ |
658 |
CPU_DoubleU u0, u1; |
659 |
|
660 |
env->fpscr |= 1 << FPSCR_ZX;
|
661 |
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); |
662 |
/* Update the floating-point exception summary */
|
663 |
env->fpscr |= 1 << FPSCR_FX;
|
664 |
if (fpscr_ze != 0) { |
665 |
/* Update the floating-point enabled exception summary */
|
666 |
env->fpscr |= 1 << FPSCR_FEX;
|
667 |
if (msr_fe0 != 0 || msr_fe1 != 0) { |
668 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
669 |
POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX); |
670 |
} |
671 |
} else {
|
672 |
/* Set the result to infinity */
|
673 |
u0.d = FT0; |
674 |
u1.d = FT1; |
675 |
u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
|
676 |
u0.ll |= 0x7FFULL << 52; |
677 |
FT0 = u0.d; |
678 |
} |
679 |
} |
680 |
|
681 |
static always_inline void float_overflow_excp (void) |
682 |
{ |
683 |
env->fpscr |= 1 << FPSCR_OX;
|
684 |
/* Update the floating-point exception summary */
|
685 |
env->fpscr |= 1 << FPSCR_FX;
|
686 |
if (fpscr_oe != 0) { |
687 |
/* XXX: should adjust the result */
|
688 |
/* Update the floating-point enabled exception summary */
|
689 |
env->fpscr |= 1 << FPSCR_FEX;
|
690 |
/* We must update the target FPR before raising the exception */
|
691 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
692 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; |
693 |
} else {
|
694 |
env->fpscr |= 1 << FPSCR_XX;
|
695 |
env->fpscr |= 1 << FPSCR_FI;
|
696 |
} |
697 |
} |
698 |
|
699 |
static always_inline void float_underflow_excp (void) |
700 |
{ |
701 |
env->fpscr |= 1 << FPSCR_UX;
|
702 |
/* Update the floating-point exception summary */
|
703 |
env->fpscr |= 1 << FPSCR_FX;
|
704 |
if (fpscr_ue != 0) { |
705 |
/* XXX: should adjust the result */
|
706 |
/* Update the floating-point enabled exception summary */
|
707 |
env->fpscr |= 1 << FPSCR_FEX;
|
708 |
/* We must update the target FPR before raising the exception */
|
709 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
710 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; |
711 |
} |
712 |
} |
713 |
|
714 |
static always_inline void float_inexact_excp (void) |
715 |
{ |
716 |
env->fpscr |= 1 << FPSCR_XX;
|
717 |
/* Update the floating-point exception summary */
|
718 |
env->fpscr |= 1 << FPSCR_FX;
|
719 |
if (fpscr_xe != 0) { |
720 |
/* Update the floating-point enabled exception summary */
|
721 |
env->fpscr |= 1 << FPSCR_FEX;
|
722 |
/* We must update the target FPR before raising the exception */
|
723 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
724 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; |
725 |
} |
726 |
} |
727 |
|
728 |
static always_inline void fpscr_set_rounding_mode (void) |
729 |
{ |
730 |
int rnd_type;
|
731 |
|
732 |
/* Set rounding mode */
|
733 |
switch (fpscr_rn) {
|
734 |
case 0: |
735 |
/* Best approximation (round to nearest) */
|
736 |
rnd_type = float_round_nearest_even; |
737 |
break;
|
738 |
case 1: |
739 |
/* Smaller magnitude (round toward zero) */
|
740 |
rnd_type = float_round_to_zero; |
741 |
break;
|
742 |
case 2: |
743 |
/* Round toward +infinite */
|
744 |
rnd_type = float_round_up; |
745 |
break;
|
746 |
default:
|
747 |
case 3: |
748 |
/* Round toward -infinite */
|
749 |
rnd_type = float_round_down; |
750 |
break;
|
751 |
} |
752 |
set_float_rounding_mode(rnd_type, &env->fp_status); |
753 |
} |
754 |
|
755 |
void do_fpscr_setbit (int bit) |
756 |
{ |
757 |
int prev;
|
758 |
|
759 |
prev = (env->fpscr >> bit) & 1;
|
760 |
env->fpscr |= 1 << bit;
|
761 |
if (prev == 0) { |
762 |
switch (bit) {
|
763 |
case FPSCR_VX:
|
764 |
env->fpscr |= 1 << FPSCR_FX;
|
765 |
if (fpscr_ve)
|
766 |
goto raise_ve;
|
767 |
case FPSCR_OX:
|
768 |
env->fpscr |= 1 << FPSCR_FX;
|
769 |
if (fpscr_oe)
|
770 |
goto raise_oe;
|
771 |
break;
|
772 |
case FPSCR_UX:
|
773 |
env->fpscr |= 1 << FPSCR_FX;
|
774 |
if (fpscr_ue)
|
775 |
goto raise_ue;
|
776 |
break;
|
777 |
case FPSCR_ZX:
|
778 |
env->fpscr |= 1 << FPSCR_FX;
|
779 |
if (fpscr_ze)
|
780 |
goto raise_ze;
|
781 |
break;
|
782 |
case FPSCR_XX:
|
783 |
env->fpscr |= 1 << FPSCR_FX;
|
784 |
if (fpscr_xe)
|
785 |
goto raise_xe;
|
786 |
break;
|
787 |
case FPSCR_VXSNAN:
|
788 |
case FPSCR_VXISI:
|
789 |
case FPSCR_VXIDI:
|
790 |
case FPSCR_VXZDZ:
|
791 |
case FPSCR_VXIMZ:
|
792 |
case FPSCR_VXVC:
|
793 |
case FPSCR_VXSOFT:
|
794 |
case FPSCR_VXSQRT:
|
795 |
case FPSCR_VXCVI:
|
796 |
env->fpscr |= 1 << FPSCR_VX;
|
797 |
env->fpscr |= 1 << FPSCR_FX;
|
798 |
if (fpscr_ve != 0) |
799 |
goto raise_ve;
|
800 |
break;
|
801 |
case FPSCR_VE:
|
802 |
if (fpscr_vx != 0) { |
803 |
raise_ve:
|
804 |
env->error_code = POWERPC_EXCP_FP; |
805 |
if (fpscr_vxsnan)
|
806 |
env->error_code |= POWERPC_EXCP_FP_VXSNAN; |
807 |
if (fpscr_vxisi)
|
808 |
env->error_code |= POWERPC_EXCP_FP_VXISI; |
809 |
if (fpscr_vxidi)
|
810 |
env->error_code |= POWERPC_EXCP_FP_VXIDI; |
811 |
if (fpscr_vxzdz)
|
812 |
env->error_code |= POWERPC_EXCP_FP_VXZDZ; |
813 |
if (fpscr_vximz)
|
814 |
env->error_code |= POWERPC_EXCP_FP_VXIMZ; |
815 |
if (fpscr_vxvc)
|
816 |
env->error_code |= POWERPC_EXCP_FP_VXVC; |
817 |
if (fpscr_vxsoft)
|
818 |
env->error_code |= POWERPC_EXCP_FP_VXSOFT; |
819 |
if (fpscr_vxsqrt)
|
820 |
env->error_code |= POWERPC_EXCP_FP_VXSQRT; |
821 |
if (fpscr_vxcvi)
|
822 |
env->error_code |= POWERPC_EXCP_FP_VXCVI; |
823 |
goto raise_excp;
|
824 |
} |
825 |
break;
|
826 |
case FPSCR_OE:
|
827 |
if (fpscr_ox != 0) { |
828 |
raise_oe:
|
829 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX; |
830 |
goto raise_excp;
|
831 |
} |
832 |
break;
|
833 |
case FPSCR_UE:
|
834 |
if (fpscr_ux != 0) { |
835 |
raise_ue:
|
836 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX; |
837 |
goto raise_excp;
|
838 |
} |
839 |
break;
|
840 |
case FPSCR_ZE:
|
841 |
if (fpscr_zx != 0) { |
842 |
raise_ze:
|
843 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX; |
844 |
goto raise_excp;
|
845 |
} |
846 |
break;
|
847 |
case FPSCR_XE:
|
848 |
if (fpscr_xx != 0) { |
849 |
raise_xe:
|
850 |
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX; |
851 |
goto raise_excp;
|
852 |
} |
853 |
break;
|
854 |
case FPSCR_RN1:
|
855 |
case FPSCR_RN:
|
856 |
fpscr_set_rounding_mode(); |
857 |
break;
|
858 |
default:
|
859 |
break;
|
860 |
raise_excp:
|
861 |
/* Update the floating-point enabled exception summary */
|
862 |
env->fpscr |= 1 << FPSCR_FEX;
|
863 |
/* We have to update Rc1 before raising the exception */
|
864 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
865 |
break;
|
866 |
} |
867 |
} |
868 |
} |
869 |
|
870 |
#if defined(WORDS_BIGENDIAN)
|
871 |
#define WORD0 0 |
872 |
#define WORD1 1 |
873 |
#else
|
874 |
#define WORD0 1 |
875 |
#define WORD1 0 |
876 |
#endif
|
877 |
void do_store_fpscr (uint32_t mask)
|
878 |
{ |
879 |
/*
|
880 |
* We use only the 32 LSB of the incoming fpr
|
881 |
*/
|
882 |
CPU_DoubleU u; |
883 |
uint32_t prev, new; |
884 |
int i;
|
885 |
|
886 |
u.d = FT0; |
887 |
prev = env->fpscr; |
888 |
new = u.l.lower; |
889 |
new &= ~0x90000000;
|
890 |
new |= prev & 0x90000000;
|
891 |
for (i = 0; i < 7; i++) { |
892 |
if (mask & (1 << i)) { |
893 |
env->fpscr &= ~(0xF << (4 * i)); |
894 |
env->fpscr |= new & (0xF << (4 * i)); |
895 |
} |
896 |
} |
897 |
/* Update VX and FEX */
|
898 |
if (fpscr_ix != 0) |
899 |
env->fpscr |= 1 << FPSCR_VX;
|
900 |
else
|
901 |
env->fpscr &= ~(1 << FPSCR_VX);
|
902 |
if ((fpscr_ex & fpscr_eex) != 0) { |
903 |
env->fpscr |= 1 << FPSCR_FEX;
|
904 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
905 |
/* XXX: we should compute it properly */
|
906 |
env->error_code = POWERPC_EXCP_FP; |
907 |
} |
908 |
else
|
909 |
env->fpscr &= ~(1 << FPSCR_FEX);
|
910 |
fpscr_set_rounding_mode(); |
911 |
} |
912 |
#undef WORD0
|
913 |
#undef WORD1
|
914 |
|
915 |
#ifdef CONFIG_SOFTFLOAT
|
916 |
void do_float_check_status (void) |
917 |
{ |
918 |
if (env->exception_index == POWERPC_EXCP_PROGRAM &&
|
919 |
(env->error_code & POWERPC_EXCP_FP)) { |
920 |
/* Differred floating-point exception after target FPR update */
|
921 |
if (msr_fe0 != 0 || msr_fe1 != 0) |
922 |
do_raise_exception_err(env->exception_index, env->error_code); |
923 |
} else if (env->fp_status.float_exception_flags & float_flag_overflow) { |
924 |
float_overflow_excp(); |
925 |
} else if (env->fp_status.float_exception_flags & float_flag_underflow) { |
926 |
float_underflow_excp(); |
927 |
} else if (env->fp_status.float_exception_flags & float_flag_inexact) { |
928 |
float_inexact_excp(); |
929 |
} |
930 |
} |
931 |
#endif
|
932 |
|
933 |
#if USE_PRECISE_EMULATION
|
934 |
void do_fadd (void) |
935 |
{ |
936 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
937 |
float64_is_signaling_nan(FT1))) { |
938 |
/* sNaN addition */
|
939 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
940 |
} else if (likely(isfinite(FT0) || isfinite(FT1) || |
941 |
fpisneg(FT0) == fpisneg(FT1))) { |
942 |
FT0 = float64_add(FT0, FT1, &env->fp_status); |
943 |
} else {
|
944 |
/* Magnitude subtraction of infinities */
|
945 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); |
946 |
} |
947 |
} |
948 |
|
949 |
void do_fsub (void) |
950 |
{ |
951 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
952 |
float64_is_signaling_nan(FT1))) { |
953 |
/* sNaN subtraction */
|
954 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
955 |
} else if (likely(isfinite(FT0) || isfinite(FT1) || |
956 |
fpisneg(FT0) != fpisneg(FT1))) { |
957 |
FT0 = float64_sub(FT0, FT1, &env->fp_status); |
958 |
} else {
|
959 |
/* Magnitude subtraction of infinities */
|
960 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI); |
961 |
} |
962 |
} |
963 |
|
964 |
void do_fmul (void) |
965 |
{ |
966 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
967 |
float64_is_signaling_nan(FT1))) { |
968 |
/* sNaN multiplication */
|
969 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
970 |
} else if (unlikely((isinfinity(FT0) && iszero(FT1)) || |
971 |
(iszero(FT0) && isinfinity(FT1)))) { |
972 |
/* Multiplication of zero by infinity */
|
973 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ); |
974 |
} else {
|
975 |
FT0 = float64_mul(FT0, FT1, &env->fp_status); |
976 |
} |
977 |
} |
978 |
|
979 |
void do_fdiv (void) |
980 |
{ |
981 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
982 |
float64_is_signaling_nan(FT1))) { |
983 |
/* sNaN division */
|
984 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
985 |
} else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) { |
986 |
/* Division of infinity by infinity */
|
987 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI); |
988 |
} else if (unlikely(iszero(FT1))) { |
989 |
if (iszero(FT0)) {
|
990 |
/* Division of zero by zero */
|
991 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ); |
992 |
} else {
|
993 |
/* Division by zero */
|
994 |
float_zero_divide_excp(); |
995 |
} |
996 |
} else {
|
997 |
FT0 = float64_div(FT0, FT1, &env->fp_status); |
998 |
} |
999 |
} |
1000 |
#endif /* USE_PRECISE_EMULATION */ |
1001 |
|
1002 |
void do_fctiw (void) |
1003 |
{ |
1004 |
CPU_DoubleU p; |
1005 |
|
1006 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1007 |
/* sNaN conversion */
|
1008 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
1009 |
} else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) { |
1010 |
/* qNan / infinity conversion */
|
1011 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1012 |
} else {
|
1013 |
p.ll = float64_to_int32(FT0, &env->fp_status); |
1014 |
#if USE_PRECISE_EMULATION
|
1015 |
/* XXX: higher bits are not supposed to be significant.
|
1016 |
* to make tests easier, return the same as a real PowerPC 750
|
1017 |
*/
|
1018 |
p.ll |= 0xFFF80000ULL << 32; |
1019 |
#endif
|
1020 |
FT0 = p.d; |
1021 |
} |
1022 |
} |
1023 |
|
1024 |
void do_fctiwz (void) |
1025 |
{ |
1026 |
CPU_DoubleU p; |
1027 |
|
1028 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1029 |
/* sNaN conversion */
|
1030 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
1031 |
} else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) { |
1032 |
/* qNan / infinity conversion */
|
1033 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1034 |
} else {
|
1035 |
p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status); |
1036 |
#if USE_PRECISE_EMULATION
|
1037 |
/* XXX: higher bits are not supposed to be significant.
|
1038 |
* to make tests easier, return the same as a real PowerPC 750
|
1039 |
*/
|
1040 |
p.ll |= 0xFFF80000ULL << 32; |
1041 |
#endif
|
1042 |
FT0 = p.d; |
1043 |
} |
1044 |
} |
1045 |
|
1046 |
#if defined(TARGET_PPC64)
|
1047 |
void do_fcfid (void) |
1048 |
{ |
1049 |
CPU_DoubleU p; |
1050 |
|
1051 |
p.d = FT0; |
1052 |
FT0 = int64_to_float64(p.ll, &env->fp_status); |
1053 |
} |
1054 |
|
1055 |
void do_fctid (void) |
1056 |
{ |
1057 |
CPU_DoubleU p; |
1058 |
|
1059 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1060 |
/* sNaN conversion */
|
1061 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
1062 |
} else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) { |
1063 |
/* qNan / infinity conversion */
|
1064 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1065 |
} else {
|
1066 |
p.ll = float64_to_int64(FT0, &env->fp_status); |
1067 |
FT0 = p.d; |
1068 |
} |
1069 |
} |
1070 |
|
1071 |
void do_fctidz (void) |
1072 |
{ |
1073 |
CPU_DoubleU p; |
1074 |
|
1075 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1076 |
/* sNaN conversion */
|
1077 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
1078 |
} else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) { |
1079 |
/* qNan / infinity conversion */
|
1080 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1081 |
} else {
|
1082 |
p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status); |
1083 |
FT0 = p.d; |
1084 |
} |
1085 |
} |
1086 |
|
1087 |
#endif
|
1088 |
|
1089 |
static always_inline void do_fri (int rounding_mode) |
1090 |
{ |
1091 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1092 |
/* sNaN round */
|
1093 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI); |
1094 |
} else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) { |
1095 |
/* qNan / infinity round */
|
1096 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI); |
1097 |
} else {
|
1098 |
set_float_rounding_mode(rounding_mode, &env->fp_status); |
1099 |
FT0 = float64_round_to_int(FT0, &env->fp_status); |
1100 |
/* Restore rounding mode from FPSCR */
|
1101 |
fpscr_set_rounding_mode(); |
1102 |
} |
1103 |
} |
1104 |
|
1105 |
void do_frin (void) |
1106 |
{ |
1107 |
do_fri(float_round_nearest_even); |
1108 |
} |
1109 |
|
1110 |
void do_friz (void) |
1111 |
{ |
1112 |
do_fri(float_round_to_zero); |
1113 |
} |
1114 |
|
1115 |
void do_frip (void) |
1116 |
{ |
1117 |
do_fri(float_round_up); |
1118 |
} |
1119 |
|
1120 |
void do_frim (void) |
1121 |
{ |
1122 |
do_fri(float_round_down); |
1123 |
} |
1124 |
|
1125 |
#if USE_PRECISE_EMULATION
|
1126 |
void do_fmadd (void) |
1127 |
{ |
1128 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
1129 |
float64_is_signaling_nan(FT1) || |
1130 |
float64_is_signaling_nan(FT2))) { |
1131 |
/* sNaN operation */
|
1132 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1133 |
} else {
|
1134 |
#ifdef FLOAT128
|
1135 |
/* This is the way the PowerPC specification defines it */
|
1136 |
float128 ft0_128, ft1_128; |
1137 |
|
1138 |
ft0_128 = float64_to_float128(FT0, &env->fp_status); |
1139 |
ft1_128 = float64_to_float128(FT1, &env->fp_status); |
1140 |
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
1141 |
ft1_128 = float64_to_float128(FT2, &env->fp_status); |
1142 |
ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); |
1143 |
FT0 = float128_to_float64(ft0_128, &env->fp_status); |
1144 |
#else
|
1145 |
/* This is OK on x86 hosts */
|
1146 |
FT0 = (FT0 * FT1) + FT2; |
1147 |
#endif
|
1148 |
} |
1149 |
} |
1150 |
|
1151 |
void do_fmsub (void) |
1152 |
{ |
1153 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
1154 |
float64_is_signaling_nan(FT1) || |
1155 |
float64_is_signaling_nan(FT2))) { |
1156 |
/* sNaN operation */
|
1157 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1158 |
} else {
|
1159 |
#ifdef FLOAT128
|
1160 |
/* This is the way the PowerPC specification defines it */
|
1161 |
float128 ft0_128, ft1_128; |
1162 |
|
1163 |
ft0_128 = float64_to_float128(FT0, &env->fp_status); |
1164 |
ft1_128 = float64_to_float128(FT1, &env->fp_status); |
1165 |
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
1166 |
ft1_128 = float64_to_float128(FT2, &env->fp_status); |
1167 |
ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); |
1168 |
FT0 = float128_to_float64(ft0_128, &env->fp_status); |
1169 |
#else
|
1170 |
/* This is OK on x86 hosts */
|
1171 |
FT0 = (FT0 * FT1) - FT2; |
1172 |
#endif
|
1173 |
} |
1174 |
} |
1175 |
#endif /* USE_PRECISE_EMULATION */ |
1176 |
|
1177 |
void do_fnmadd (void) |
1178 |
{ |
1179 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
1180 |
float64_is_signaling_nan(FT1) || |
1181 |
float64_is_signaling_nan(FT2))) { |
1182 |
/* sNaN operation */
|
1183 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1184 |
} else {
|
1185 |
#if USE_PRECISE_EMULATION
|
1186 |
#ifdef FLOAT128
|
1187 |
/* This is the way the PowerPC specification defines it */
|
1188 |
float128 ft0_128, ft1_128; |
1189 |
|
1190 |
ft0_128 = float64_to_float128(FT0, &env->fp_status); |
1191 |
ft1_128 = float64_to_float128(FT1, &env->fp_status); |
1192 |
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
1193 |
ft1_128 = float64_to_float128(FT2, &env->fp_status); |
1194 |
ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status); |
1195 |
FT0 = float128_to_float64(ft0_128, &env->fp_status); |
1196 |
#else
|
1197 |
/* This is OK on x86 hosts */
|
1198 |
FT0 = (FT0 * FT1) + FT2; |
1199 |
#endif
|
1200 |
#else
|
1201 |
FT0 = float64_mul(FT0, FT1, &env->fp_status); |
1202 |
FT0 = float64_add(FT0, FT2, &env->fp_status); |
1203 |
#endif
|
1204 |
if (likely(!isnan(FT0)))
|
1205 |
FT0 = float64_chs(FT0); |
1206 |
} |
1207 |
} |
1208 |
|
1209 |
void do_fnmsub (void) |
1210 |
{ |
1211 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
1212 |
float64_is_signaling_nan(FT1) || |
1213 |
float64_is_signaling_nan(FT2))) { |
1214 |
/* sNaN operation */
|
1215 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1216 |
} else {
|
1217 |
#if USE_PRECISE_EMULATION
|
1218 |
#ifdef FLOAT128
|
1219 |
/* This is the way the PowerPC specification defines it */
|
1220 |
float128 ft0_128, ft1_128; |
1221 |
|
1222 |
ft0_128 = float64_to_float128(FT0, &env->fp_status); |
1223 |
ft1_128 = float64_to_float128(FT1, &env->fp_status); |
1224 |
ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status); |
1225 |
ft1_128 = float64_to_float128(FT2, &env->fp_status); |
1226 |
ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status); |
1227 |
FT0 = float128_to_float64(ft0_128, &env->fp_status); |
1228 |
#else
|
1229 |
/* This is OK on x86 hosts */
|
1230 |
FT0 = (FT0 * FT1) - FT2; |
1231 |
#endif
|
1232 |
#else
|
1233 |
FT0 = float64_mul(FT0, FT1, &env->fp_status); |
1234 |
FT0 = float64_sub(FT0, FT2, &env->fp_status); |
1235 |
#endif
|
1236 |
if (likely(!isnan(FT0)))
|
1237 |
FT0 = float64_chs(FT0); |
1238 |
} |
1239 |
} |
1240 |
|
1241 |
#if USE_PRECISE_EMULATION
|
1242 |
void do_frsp (void) |
1243 |
{ |
1244 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1245 |
/* sNaN square root */
|
1246 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1247 |
} else {
|
1248 |
FT0 = float64_to_float32(FT0, &env->fp_status); |
1249 |
} |
1250 |
} |
1251 |
#endif /* USE_PRECISE_EMULATION */ |
1252 |
|
1253 |
void do_fsqrt (void) |
1254 |
{ |
1255 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1256 |
/* sNaN square root */
|
1257 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1258 |
} else if (unlikely(fpisneg(FT0) && !iszero(FT0))) { |
1259 |
/* Square root of a negative nonzero number */
|
1260 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT); |
1261 |
} else {
|
1262 |
FT0 = float64_sqrt(FT0, &env->fp_status); |
1263 |
} |
1264 |
} |
1265 |
|
1266 |
void do_fre (void) |
1267 |
{ |
1268 |
CPU_DoubleU p; |
1269 |
|
1270 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1271 |
/* sNaN reciprocal */
|
1272 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1273 |
} else if (unlikely(iszero(FT0))) { |
1274 |
/* Zero reciprocal */
|
1275 |
float_zero_divide_excp(); |
1276 |
} else if (likely(isnormal(FT0))) { |
1277 |
FT0 = float64_div(1.0, FT0, &env->fp_status); |
1278 |
} else {
|
1279 |
p.d = FT0; |
1280 |
if (p.ll == 0x8000000000000000ULL) { |
1281 |
p.ll = 0xFFF0000000000000ULL;
|
1282 |
} else if (p.ll == 0x0000000000000000ULL) { |
1283 |
p.ll = 0x7FF0000000000000ULL;
|
1284 |
} else if (isnan(FT0)) { |
1285 |
p.ll = 0x7FF8000000000000ULL;
|
1286 |
} else if (fpisneg(FT0)) { |
1287 |
p.ll = 0x8000000000000000ULL;
|
1288 |
} else {
|
1289 |
p.ll = 0x0000000000000000ULL;
|
1290 |
} |
1291 |
FT0 = p.d; |
1292 |
} |
1293 |
} |
1294 |
|
1295 |
void do_fres (void) |
1296 |
{ |
1297 |
CPU_DoubleU p; |
1298 |
|
1299 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1300 |
/* sNaN reciprocal */
|
1301 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1302 |
} else if (unlikely(iszero(FT0))) { |
1303 |
/* Zero reciprocal */
|
1304 |
float_zero_divide_excp(); |
1305 |
} else if (likely(isnormal(FT0))) { |
1306 |
#if USE_PRECISE_EMULATION
|
1307 |
FT0 = float64_div(1.0, FT0, &env->fp_status); |
1308 |
FT0 = float64_to_float32(FT0, &env->fp_status); |
1309 |
#else
|
1310 |
FT0 = float32_div(1.0, FT0, &env->fp_status); |
1311 |
#endif
|
1312 |
} else {
|
1313 |
p.d = FT0; |
1314 |
if (p.ll == 0x8000000000000000ULL) { |
1315 |
p.ll = 0xFFF0000000000000ULL;
|
1316 |
} else if (p.ll == 0x0000000000000000ULL) { |
1317 |
p.ll = 0x7FF0000000000000ULL;
|
1318 |
} else if (isnan(FT0)) { |
1319 |
p.ll = 0x7FF8000000000000ULL;
|
1320 |
} else if (fpisneg(FT0)) { |
1321 |
p.ll = 0x8000000000000000ULL;
|
1322 |
} else {
|
1323 |
p.ll = 0x0000000000000000ULL;
|
1324 |
} |
1325 |
FT0 = p.d; |
1326 |
} |
1327 |
} |
1328 |
|
1329 |
void do_frsqrte (void) |
1330 |
{ |
1331 |
CPU_DoubleU p; |
1332 |
|
1333 |
if (unlikely(float64_is_signaling_nan(FT0))) {
|
1334 |
/* sNaN reciprocal square root */
|
1335 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1336 |
} else if (unlikely(fpisneg(FT0) && !iszero(FT0))) { |
1337 |
/* Reciprocal square root of a negative nonzero number */
|
1338 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT); |
1339 |
} else if (likely(isnormal(FT0))) { |
1340 |
FT0 = float64_sqrt(FT0, &env->fp_status); |
1341 |
FT0 = float32_div(1.0, FT0, &env->fp_status); |
1342 |
} else {
|
1343 |
p.d = FT0; |
1344 |
if (p.ll == 0x8000000000000000ULL) { |
1345 |
p.ll = 0xFFF0000000000000ULL;
|
1346 |
} else if (p.ll == 0x0000000000000000ULL) { |
1347 |
p.ll = 0x7FF0000000000000ULL;
|
1348 |
} else if (isnan(FT0)) { |
1349 |
p.ll |= 0x000FFFFFFFFFFFFFULL;
|
1350 |
} else if (fpisneg(FT0)) { |
1351 |
p.ll = 0x7FF8000000000000ULL;
|
1352 |
} else {
|
1353 |
p.ll = 0x0000000000000000ULL;
|
1354 |
} |
1355 |
FT0 = p.d; |
1356 |
} |
1357 |
} |
1358 |
|
1359 |
void do_fsel (void) |
1360 |
{ |
1361 |
if (!fpisneg(FT0) || iszero(FT0))
|
1362 |
FT0 = FT1; |
1363 |
else
|
1364 |
FT0 = FT2; |
1365 |
} |
1366 |
|
1367 |
uint32_t helper_fcmpu (void)
|
1368 |
{ |
1369 |
uint32_t ret = 0;
|
1370 |
|
1371 |
if (unlikely(float64_is_signaling_nan(FT0) ||
|
1372 |
float64_is_signaling_nan(FT1))) { |
1373 |
/* sNaN comparison */
|
1374 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN); |
1375 |
} else {
|
1376 |
if (float64_lt(FT0, FT1, &env->fp_status)) {
|
1377 |
ret = 0x08UL;
|
1378 |
} else if (!float64_le(FT0, FT1, &env->fp_status)) { |
1379 |
ret = 0x04UL;
|
1380 |
} else {
|
1381 |
ret = 0x02UL;
|
1382 |
} |
1383 |
} |
1384 |
env->fpscr &= ~(0x0F << FPSCR_FPRF);
|
1385 |
env->fpscr |= ret << FPSCR_FPRF; |
1386 |
return ret;
|
1387 |
} |
1388 |
|
1389 |
uint32_t helper_fcmpo (void)
|
1390 |
{ |
1391 |
uint32_t ret = 0;
|
1392 |
|
1393 |
if (unlikely(float64_is_nan(FT0) ||
|
1394 |
float64_is_nan(FT1))) { |
1395 |
if (float64_is_signaling_nan(FT0) ||
|
1396 |
float64_is_signaling_nan(FT1)) { |
1397 |
/* sNaN comparison */
|
1398 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | |
1399 |
POWERPC_EXCP_FP_VXVC); |
1400 |
} else {
|
1401 |
/* qNaN comparison */
|
1402 |
fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC); |
1403 |
} |
1404 |
} else {
|
1405 |
if (float64_lt(FT0, FT1, &env->fp_status)) {
|
1406 |
ret = 0x08UL;
|
1407 |
} else if (!float64_le(FT0, FT1, &env->fp_status)) { |
1408 |
ret = 0x04UL;
|
1409 |
} else {
|
1410 |
ret = 0x02UL;
|
1411 |
} |
1412 |
} |
1413 |
env->fpscr &= ~(0x0F << FPSCR_FPRF);
|
1414 |
env->fpscr |= ret << FPSCR_FPRF; |
1415 |
return ret;
|
1416 |
} |
1417 |
|
1418 |
#if !defined (CONFIG_USER_ONLY)
|
1419 |
void cpu_dump_rfi (target_ulong RA, target_ulong msr);
|
1420 |
|
1421 |
void do_store_msr (void) |
1422 |
{ |
1423 |
T0 = hreg_store_msr(env, T0, 0);
|
1424 |
if (T0 != 0) { |
1425 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1426 |
do_raise_exception(T0); |
1427 |
} |
1428 |
} |
1429 |
|
1430 |
static always_inline void __do_rfi (target_ulong nip, target_ulong msr, |
1431 |
target_ulong msrm, int keep_msrh)
|
1432 |
{ |
1433 |
#if defined(TARGET_PPC64)
|
1434 |
if (msr & (1ULL << MSR_SF)) { |
1435 |
nip = (uint64_t)nip; |
1436 |
msr &= (uint64_t)msrm; |
1437 |
} else {
|
1438 |
nip = (uint32_t)nip; |
1439 |
msr = (uint32_t)(msr & msrm); |
1440 |
if (keep_msrh)
|
1441 |
msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
|
1442 |
} |
1443 |
#else
|
1444 |
nip = (uint32_t)nip; |
1445 |
msr &= (uint32_t)msrm; |
1446 |
#endif
|
1447 |
/* XXX: beware: this is false if VLE is supported */
|
1448 |
env->nip = nip & ~((target_ulong)0x00000003);
|
1449 |
hreg_store_msr(env, msr, 1);
|
1450 |
#if defined (DEBUG_OP)
|
1451 |
cpu_dump_rfi(env->nip, env->msr); |
1452 |
#endif
|
1453 |
/* No need to raise an exception here,
|
1454 |
* as rfi is always the last insn of a TB
|
1455 |
*/
|
1456 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1457 |
} |
1458 |
|
1459 |
void do_rfi (void) |
1460 |
{ |
1461 |
__do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
1462 |
~((target_ulong)0xFFFF0000), 1); |
1463 |
} |
1464 |
|
1465 |
#if defined(TARGET_PPC64)
|
1466 |
void do_rfid (void) |
1467 |
{ |
1468 |
__do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
1469 |
~((target_ulong)0xFFFF0000), 0); |
1470 |
} |
1471 |
|
1472 |
void do_hrfid (void) |
1473 |
{ |
1474 |
__do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1], |
1475 |
~((target_ulong)0xFFFF0000), 0); |
1476 |
} |
1477 |
#endif
|
1478 |
#endif
|
1479 |
|
1480 |
void do_tw (int flags) |
1481 |
{ |
1482 |
if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) || |
1483 |
((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
|
1484 |
((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
|
1485 |
((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
|
1486 |
((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
|
1487 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
1488 |
} |
1489 |
} |
1490 |
|
1491 |
#if defined(TARGET_PPC64)
|
1492 |
void do_td (int flags) |
1493 |
{ |
1494 |
if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) || |
1495 |
((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
|
1496 |
((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
|
1497 |
((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
|
1498 |
((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
|
1499 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
1500 |
} |
1501 |
#endif
|
1502 |
|
1503 |
/*****************************************************************************/
|
1504 |
/* PowerPC 601 specific instructions (POWER bridge) */
|
1505 |
void do_POWER_abso (void) |
1506 |
{ |
1507 |
if ((int32_t)T0 == INT32_MIN) {
|
1508 |
T0 = INT32_MAX; |
1509 |
env->xer |= (1 << XER_OV) | (1 << XER_SO); |
1510 |
} else if ((int32_t)T0 < 0) { |
1511 |
T0 = -T0; |
1512 |
env->xer &= ~(1 << XER_OV);
|
1513 |
} else {
|
1514 |
env->xer &= ~(1 << XER_OV);
|
1515 |
} |
1516 |
} |
1517 |
|
1518 |
void do_POWER_clcs (void) |
1519 |
{ |
1520 |
switch (T0) {
|
1521 |
case 0x0CUL: |
1522 |
/* Instruction cache line size */
|
1523 |
T0 = env->icache_line_size; |
1524 |
break;
|
1525 |
case 0x0DUL: |
1526 |
/* Data cache line size */
|
1527 |
T0 = env->dcache_line_size; |
1528 |
break;
|
1529 |
case 0x0EUL: |
1530 |
/* Minimum cache line size */
|
1531 |
T0 = env->icache_line_size < env->dcache_line_size ? |
1532 |
env->icache_line_size : env->dcache_line_size; |
1533 |
break;
|
1534 |
case 0x0FUL: |
1535 |
/* Maximum cache line size */
|
1536 |
T0 = env->icache_line_size > env->dcache_line_size ? |
1537 |
env->icache_line_size : env->dcache_line_size; |
1538 |
break;
|
1539 |
default:
|
1540 |
/* Undefined */
|
1541 |
break;
|
1542 |
} |
1543 |
} |
1544 |
|
1545 |
void do_POWER_div (void) |
1546 |
{ |
1547 |
uint64_t tmp; |
1548 |
|
1549 |
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) || |
1550 |
(int32_t)T1 == 0) {
|
1551 |
T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
|
1552 |
env->spr[SPR_MQ] = 0;
|
1553 |
} else {
|
1554 |
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
|
1555 |
env->spr[SPR_MQ] = tmp % T1; |
1556 |
T0 = tmp / (int32_t)T1; |
1557 |
} |
1558 |
} |
1559 |
|
1560 |
void do_POWER_divo (void) |
1561 |
{ |
1562 |
int64_t tmp; |
1563 |
|
1564 |
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) || |
1565 |
(int32_t)T1 == 0) {
|
1566 |
T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
|
1567 |
env->spr[SPR_MQ] = 0;
|
1568 |
env->xer |= (1 << XER_OV) | (1 << XER_SO); |
1569 |
} else {
|
1570 |
tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
|
1571 |
env->spr[SPR_MQ] = tmp % T1; |
1572 |
tmp /= (int32_t)T1; |
1573 |
if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
|
1574 |
env->xer |= (1 << XER_OV) | (1 << XER_SO); |
1575 |
} else {
|
1576 |
env->xer &= ~(1 << XER_OV);
|
1577 |
} |
1578 |
T0 = tmp; |
1579 |
} |
1580 |
} |
1581 |
|
1582 |
void do_POWER_divs (void) |
1583 |
{ |
1584 |
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) || |
1585 |
(int32_t)T1 == 0) {
|
1586 |
T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
|
1587 |
env->spr[SPR_MQ] = 0;
|
1588 |
} else {
|
1589 |
env->spr[SPR_MQ] = T0 % T1; |
1590 |
T0 = (int32_t)T0 / (int32_t)T1; |
1591 |
} |
1592 |
} |
1593 |
|
1594 |
void do_POWER_divso (void) |
1595 |
{ |
1596 |
if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) || |
1597 |
(int32_t)T1 == 0) {
|
1598 |
T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
|
1599 |
env->spr[SPR_MQ] = 0;
|
1600 |
env->xer |= (1 << XER_OV) | (1 << XER_SO); |
1601 |
} else {
|
1602 |
T0 = (int32_t)T0 / (int32_t)T1; |
1603 |
env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1; |
1604 |
env->xer &= ~(1 << XER_OV);
|
1605 |
} |
1606 |
} |
1607 |
|
1608 |
void do_POWER_dozo (void) |
1609 |
{ |
1610 |
if ((int32_t)T1 > (int32_t)T0) {
|
1611 |
T2 = T0; |
1612 |
T0 = T1 - T0; |
1613 |
if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
|
1614 |
((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) { |
1615 |
env->xer |= (1 << XER_OV) | (1 << XER_SO); |
1616 |
} else {
|
1617 |
env->xer &= ~(1 << XER_OV);
|
1618 |
} |
1619 |
} else {
|
1620 |
T0 = 0;
|
1621 |
env->xer &= ~(1 << XER_OV);
|
1622 |
} |
1623 |
} |
1624 |
|
1625 |
void do_POWER_maskg (void) |
1626 |
{ |
1627 |
uint32_t ret; |
1628 |
|
1629 |
if ((uint32_t)T0 == (uint32_t)(T1 + 1)) { |
1630 |
ret = UINT32_MAX; |
1631 |
} else {
|
1632 |
ret = (UINT32_MAX >> ((uint32_t)T0)) ^ |
1633 |
((UINT32_MAX >> ((uint32_t)T1)) >> 1);
|
1634 |
if ((uint32_t)T0 > (uint32_t)T1)
|
1635 |
ret = ~ret; |
1636 |
} |
1637 |
T0 = ret; |
1638 |
} |
1639 |
|
1640 |
void do_POWER_mulo (void) |
1641 |
{ |
1642 |
uint64_t tmp; |
1643 |
|
1644 |
tmp = (uint64_t)T0 * (uint64_t)T1; |
1645 |
env->spr[SPR_MQ] = tmp >> 32;
|
1646 |
T0 = tmp; |
1647 |
if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) { |
1648 |
env->xer |= (1 << XER_OV) | (1 << XER_SO); |
1649 |
} else {
|
1650 |
env->xer &= ~(1 << XER_OV);
|
1651 |
} |
1652 |
} |
1653 |
|
1654 |
#if !defined (CONFIG_USER_ONLY)
|
1655 |
void do_POWER_rac (void) |
1656 |
{ |
1657 |
mmu_ctx_t ctx; |
1658 |
int nb_BATs;
|
1659 |
|
1660 |
/* We don't have to generate many instances of this instruction,
|
1661 |
* as rac is supervisor only.
|
1662 |
*/
|
1663 |
/* XXX: FIX THIS: Pretend we have no BAT */
|
1664 |
nb_BATs = env->nb_BATs; |
1665 |
env->nb_BATs = 0;
|
1666 |
if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0) |
1667 |
T0 = ctx.raddr; |
1668 |
env->nb_BATs = nb_BATs; |
1669 |
} |
1670 |
|
1671 |
void do_POWER_rfsvc (void) |
1672 |
{ |
1673 |
__do_rfi(env->lr, env->ctr, 0x0000FFFF, 0); |
1674 |
} |
1675 |
|
1676 |
void do_store_hid0_601 (void) |
1677 |
{ |
1678 |
uint32_t hid0; |
1679 |
|
1680 |
hid0 = env->spr[SPR_HID0]; |
1681 |
if ((T0 ^ hid0) & 0x00000008) { |
1682 |
/* Change current endianness */
|
1683 |
env->hflags &= ~(1 << MSR_LE);
|
1684 |
env->hflags_nmsr &= ~(1 << MSR_LE);
|
1685 |
env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE); |
1686 |
env->hflags |= env->hflags_nmsr; |
1687 |
if (loglevel != 0) { |
1688 |
fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n", |
1689 |
__func__, T0 & 0x8 ? 'l' : 'b', env->hflags); |
1690 |
} |
1691 |
} |
1692 |
env->spr[SPR_HID0] = T0; |
1693 |
} |
1694 |
#endif
|
1695 |
|
1696 |
/*****************************************************************************/
|
1697 |
/* 602 specific instructions */
|
1698 |
/* mfrom is the most crazy instruction ever seen, imho ! */
|
1699 |
/* Real implementation uses a ROM table. Do the same */
|
1700 |
#define USE_MFROM_ROM_TABLE
|
1701 |
void do_op_602_mfrom (void) |
1702 |
{ |
1703 |
if (likely(T0 < 602)) { |
1704 |
#if defined(USE_MFROM_ROM_TABLE)
|
1705 |
#include "mfrom_table.c" |
1706 |
T0 = mfrom_ROM_table[T0]; |
1707 |
#else
|
1708 |
double d;
|
1709 |
/* Extremly decomposed:
|
1710 |
* -T0 / 256
|
1711 |
* T0 = 256 * log10(10 + 1.0) + 0.5
|
1712 |
*/
|
1713 |
d = T0; |
1714 |
d = float64_div(d, 256, &env->fp_status);
|
1715 |
d = float64_chs(d); |
1716 |
d = exp10(d); // XXX: use float emulation function
|
1717 |
d = float64_add(d, 1.0, &env->fp_status); |
1718 |
d = log10(d); // XXX: use float emulation function
|
1719 |
d = float64_mul(d, 256, &env->fp_status);
|
1720 |
d = float64_add(d, 0.5, &env->fp_status); |
1721 |
T0 = float64_round_to_int(d, &env->fp_status); |
1722 |
#endif
|
1723 |
} else {
|
1724 |
T0 = 0;
|
1725 |
} |
1726 |
} |
1727 |
|
1728 |
/*****************************************************************************/
|
1729 |
/* Embedded PowerPC specific helpers */
|
1730 |
void do_405_check_sat (void) |
1731 |
{ |
1732 |
if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) || |
1733 |
!(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
|
1734 |
/* Saturate result */
|
1735 |
if (T2 >> 31) { |
1736 |
T0 = INT32_MIN; |
1737 |
} else {
|
1738 |
T0 = INT32_MAX; |
1739 |
} |
1740 |
} |
1741 |
} |
1742 |
|
1743 |
/* XXX: to be improved to check access rights when in user-mode */
|
1744 |
void do_load_dcr (void) |
1745 |
{ |
1746 |
target_ulong val; |
1747 |
|
1748 |
if (unlikely(env->dcr_env == NULL)) { |
1749 |
if (loglevel != 0) { |
1750 |
fprintf(logfile, "No DCR environment\n");
|
1751 |
} |
1752 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1753 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
1754 |
} else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) { |
1755 |
if (loglevel != 0) { |
1756 |
fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0); |
1757 |
} |
1758 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1759 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
1760 |
} else {
|
1761 |
T0 = val; |
1762 |
} |
1763 |
} |
1764 |
|
1765 |
void do_store_dcr (void) |
1766 |
{ |
1767 |
if (unlikely(env->dcr_env == NULL)) { |
1768 |
if (loglevel != 0) { |
1769 |
fprintf(logfile, "No DCR environment\n");
|
1770 |
} |
1771 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1772 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
1773 |
} else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) { |
1774 |
if (loglevel != 0) { |
1775 |
fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0); |
1776 |
} |
1777 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
1778 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); |
1779 |
} |
1780 |
} |
1781 |
|
1782 |
#if !defined(CONFIG_USER_ONLY)
|
1783 |
void do_40x_rfci (void) |
1784 |
{ |
1785 |
__do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3], |
1786 |
~((target_ulong)0xFFFF0000), 0); |
1787 |
} |
1788 |
|
1789 |
void do_rfci (void) |
1790 |
{ |
1791 |
__do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1, |
1792 |
~((target_ulong)0x3FFF0000), 0); |
1793 |
} |
1794 |
|
1795 |
void do_rfdi (void) |
1796 |
{ |
1797 |
__do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1, |
1798 |
~((target_ulong)0x3FFF0000), 0); |
1799 |
} |
1800 |
|
1801 |
void do_rfmci (void) |
1802 |
{ |
1803 |
__do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1, |
1804 |
~((target_ulong)0x3FFF0000), 0); |
1805 |
} |
1806 |
|
1807 |
void do_load_403_pb (int num) |
1808 |
{ |
1809 |
T0 = env->pb[num]; |
1810 |
} |
1811 |
|
1812 |
void do_store_403_pb (int num) |
1813 |
{ |
1814 |
if (likely(env->pb[num] != T0)) {
|
1815 |
env->pb[num] = T0; |
1816 |
/* Should be optimized */
|
1817 |
tlb_flush(env, 1);
|
1818 |
} |
1819 |
} |
1820 |
#endif
|
1821 |
|
1822 |
/* 440 specific */
|
1823 |
void do_440_dlmzb (void) |
1824 |
{ |
1825 |
target_ulong mask; |
1826 |
int i;
|
1827 |
|
1828 |
i = 1;
|
1829 |
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) { |
1830 |
if ((T0 & mask) == 0) |
1831 |
goto done;
|
1832 |
i++; |
1833 |
} |
1834 |
for (mask = 0xFF000000; mask != 0; mask = mask >> 8) { |
1835 |
if ((T1 & mask) == 0) |
1836 |
break;
|
1837 |
i++; |
1838 |
} |
1839 |
done:
|
1840 |
T0 = i; |
1841 |
} |
1842 |
|
1843 |
/* SPE extension helpers */
|
1844 |
/* Use a table to make this quicker */
|
1845 |
static uint8_t hbrev[16] = { |
1846 |
0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, |
1847 |
0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF, |
1848 |
}; |
1849 |
|
1850 |
static always_inline uint8_t byte_reverse (uint8_t val)
|
1851 |
{ |
1852 |
return hbrev[val >> 4] | (hbrev[val & 0xF] << 4); |
1853 |
} |
1854 |
|
1855 |
static always_inline uint32_t word_reverse (uint32_t val)
|
1856 |
{ |
1857 |
return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) | |
1858 |
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24); |
1859 |
} |
1860 |
|
1861 |
#define MASKBITS 16 // Random value - to be fixed (implementation dependant) |
1862 |
void do_brinc (void) |
1863 |
{ |
1864 |
uint32_t a, b, d, mask; |
1865 |
|
1866 |
mask = UINT32_MAX >> (32 - MASKBITS);
|
1867 |
a = T0 & mask; |
1868 |
b = T1 & mask; |
1869 |
d = word_reverse(1 + word_reverse(a | ~b));
|
1870 |
T0 = (T0 & ~mask) | (d & b); |
1871 |
} |
1872 |
|
1873 |
#define DO_SPE_OP2(name) \
|
1874 |
void do_ev##name (void) \ |
1875 |
{ \ |
1876 |
T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \ |
1877 |
(uint64_t)_do_e##name(T0_64, T1_64); \ |
1878 |
} |
1879 |
|
1880 |
#define DO_SPE_OP1(name) \
|
1881 |
void do_ev##name (void) \ |
1882 |
{ \ |
1883 |
T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \ |
1884 |
(uint64_t)_do_e##name(T0_64); \ |
1885 |
} |
1886 |
|
1887 |
/* Fixed-point vector arithmetic */
|
1888 |
static always_inline uint32_t _do_eabs (uint32_t val)
|
1889 |
{ |
1890 |
if ((val & 0x80000000) && val != 0x80000000) |
1891 |
val -= val; |
1892 |
|
1893 |
return val;
|
1894 |
} |
1895 |
|
1896 |
static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
|
1897 |
{ |
1898 |
return op1 + op2;
|
1899 |
} |
1900 |
|
1901 |
static always_inline int _do_ecntlsw (uint32_t val) |
1902 |
{ |
1903 |
if (val & 0x80000000) |
1904 |
return clz32(~val);
|
1905 |
else
|
1906 |
return clz32(val);
|
1907 |
} |
1908 |
|
1909 |
static always_inline int _do_ecntlzw (uint32_t val) |
1910 |
{ |
1911 |
return clz32(val);
|
1912 |
} |
1913 |
|
1914 |
static always_inline uint32_t _do_eneg (uint32_t val)
|
1915 |
{ |
1916 |
if (val != 0x80000000) |
1917 |
val -= val; |
1918 |
|
1919 |
return val;
|
1920 |
} |
1921 |
|
1922 |
static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
|
1923 |
{ |
1924 |
return rotl32(op1, op2);
|
1925 |
} |
1926 |
|
1927 |
static always_inline uint32_t _do_erndw (uint32_t val)
|
1928 |
{ |
1929 |
return (val + 0x000080000000) & 0xFFFF0000; |
1930 |
} |
1931 |
|
1932 |
static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
|
1933 |
{ |
1934 |
/* No error here: 6 bits are used */
|
1935 |
return op1 << (op2 & 0x3F); |
1936 |
} |
1937 |
|
1938 |
static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
|
1939 |
{ |
1940 |
/* No error here: 6 bits are used */
|
1941 |
return op1 >> (op2 & 0x3F); |
1942 |
} |
1943 |
|
1944 |
static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
|
1945 |
{ |
1946 |
/* No error here: 6 bits are used */
|
1947 |
return op1 >> (op2 & 0x3F); |
1948 |
} |
1949 |
|
1950 |
static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
|
1951 |
{ |
1952 |
return op2 - op1;
|
1953 |
} |
1954 |
|
1955 |
/* evabs */
|
1956 |
DO_SPE_OP1(abs); |
1957 |
/* evaddw */
|
1958 |
DO_SPE_OP2(addw); |
1959 |
/* evcntlsw */
|
1960 |
DO_SPE_OP1(cntlsw); |
1961 |
/* evcntlzw */
|
1962 |
DO_SPE_OP1(cntlzw); |
1963 |
/* evneg */
|
1964 |
DO_SPE_OP1(neg); |
1965 |
/* evrlw */
|
1966 |
DO_SPE_OP2(rlw); |
1967 |
/* evrnd */
|
1968 |
DO_SPE_OP1(rndw); |
1969 |
/* evslw */
|
1970 |
DO_SPE_OP2(slw); |
1971 |
/* evsrws */
|
1972 |
DO_SPE_OP2(srws); |
1973 |
/* evsrwu */
|
1974 |
DO_SPE_OP2(srwu); |
1975 |
/* evsubfw */
|
1976 |
DO_SPE_OP2(subfw); |
1977 |
|
1978 |
/* evsel is a little bit more complicated... */
|
1979 |
static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n) |
1980 |
{ |
1981 |
if (n)
|
1982 |
return op1;
|
1983 |
else
|
1984 |
return op2;
|
1985 |
} |
1986 |
|
1987 |
void do_evsel (void) |
1988 |
{ |
1989 |
T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) | |
1990 |
(uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1); |
1991 |
} |
1992 |
|
1993 |
/* Fixed-point vector comparisons */
|
1994 |
#define DO_SPE_CMP(name) \
|
1995 |
void do_ev##name (void) \ |
1996 |
{ \ |
1997 |
T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \ |
1998 |
T1_64 >> 32) << 32, \ |
1999 |
_do_e##name(T0_64, T1_64)); \ |
2000 |
} |
2001 |
|
2002 |
static always_inline uint32_t _do_evcmp_merge (int t0, int t1) |
2003 |
{ |
2004 |
return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1); |
2005 |
} |
2006 |
static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2) |
2007 |
{ |
2008 |
return op1 == op2 ? 1 : 0; |
2009 |
} |
2010 |
|
2011 |
static always_inline int _do_ecmpgts (int32_t op1, int32_t op2) |
2012 |
{ |
2013 |
return op1 > op2 ? 1 : 0; |
2014 |
} |
2015 |
|
2016 |
static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2) |
2017 |
{ |
2018 |
return op1 > op2 ? 1 : 0; |
2019 |
} |
2020 |
|
2021 |
static always_inline int _do_ecmplts (int32_t op1, int32_t op2) |
2022 |
{ |
2023 |
return op1 < op2 ? 1 : 0; |
2024 |
} |
2025 |
|
2026 |
static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2) |
2027 |
{ |
2028 |
return op1 < op2 ? 1 : 0; |
2029 |
} |
2030 |
|
2031 |
/* evcmpeq */
|
2032 |
DO_SPE_CMP(cmpeq); |
2033 |
/* evcmpgts */
|
2034 |
DO_SPE_CMP(cmpgts); |
2035 |
/* evcmpgtu */
|
2036 |
DO_SPE_CMP(cmpgtu); |
2037 |
/* evcmplts */
|
2038 |
DO_SPE_CMP(cmplts); |
2039 |
/* evcmpltu */
|
2040 |
DO_SPE_CMP(cmpltu); |
2041 |
|
2042 |
/* Single precision floating-point conversions from/to integer */
|
2043 |
static always_inline uint32_t _do_efscfsi (int32_t val)
|
2044 |
{ |
2045 |
CPU_FloatU u; |
2046 |
|
2047 |
u.f = int32_to_float32(val, &env->spe_status); |
2048 |
|
2049 |
return u.l;
|
2050 |
} |
2051 |
|
2052 |
static always_inline uint32_t _do_efscfui (uint32_t val)
|
2053 |
{ |
2054 |
CPU_FloatU u; |
2055 |
|
2056 |
u.f = uint32_to_float32(val, &env->spe_status); |
2057 |
|
2058 |
return u.l;
|
2059 |
} |
2060 |
|
2061 |
static always_inline int32_t _do_efsctsi (uint32_t val)
|
2062 |
{ |
2063 |
CPU_FloatU u; |
2064 |
|
2065 |
u.l = val; |
2066 |
/* NaN are not treated the same way IEEE 754 does */
|
2067 |
if (unlikely(isnan(u.f)))
|
2068 |
return 0; |
2069 |
|
2070 |
return float32_to_int32(u.f, &env->spe_status);
|
2071 |
} |
2072 |
|
2073 |
static always_inline uint32_t _do_efsctui (uint32_t val)
|
2074 |
{ |
2075 |
CPU_FloatU u; |
2076 |
|
2077 |
u.l = val; |
2078 |
/* NaN are not treated the same way IEEE 754 does */
|
2079 |
if (unlikely(isnan(u.f)))
|
2080 |
return 0; |
2081 |
|
2082 |
return float32_to_uint32(u.f, &env->spe_status);
|
2083 |
} |
2084 |
|
2085 |
static always_inline int32_t _do_efsctsiz (uint32_t val)
|
2086 |
{ |
2087 |
CPU_FloatU u; |
2088 |
|
2089 |
u.l = val; |
2090 |
/* NaN are not treated the same way IEEE 754 does */
|
2091 |
if (unlikely(isnan(u.f)))
|
2092 |
return 0; |
2093 |
|
2094 |
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
|
2095 |
} |
2096 |
|
2097 |
static always_inline uint32_t _do_efsctuiz (uint32_t val)
|
2098 |
{ |
2099 |
CPU_FloatU u; |
2100 |
|
2101 |
u.l = val; |
2102 |
/* NaN are not treated the same way IEEE 754 does */
|
2103 |
if (unlikely(isnan(u.f)))
|
2104 |
return 0; |
2105 |
|
2106 |
return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
|
2107 |
} |
2108 |
|
2109 |
void do_efscfsi (void) |
2110 |
{ |
2111 |
T0_64 = _do_efscfsi(T0_64); |
2112 |
} |
2113 |
|
2114 |
void do_efscfui (void) |
2115 |
{ |
2116 |
T0_64 = _do_efscfui(T0_64); |
2117 |
} |
2118 |
|
2119 |
void do_efsctsi (void) |
2120 |
{ |
2121 |
T0_64 = _do_efsctsi(T0_64); |
2122 |
} |
2123 |
|
2124 |
void do_efsctui (void) |
2125 |
{ |
2126 |
T0_64 = _do_efsctui(T0_64); |
2127 |
} |
2128 |
|
2129 |
void do_efsctsiz (void) |
2130 |
{ |
2131 |
T0_64 = _do_efsctsiz(T0_64); |
2132 |
} |
2133 |
|
2134 |
void do_efsctuiz (void) |
2135 |
{ |
2136 |
T0_64 = _do_efsctuiz(T0_64); |
2137 |
} |
2138 |
|
2139 |
/* Single precision floating-point conversion to/from fractional */
|
2140 |
static always_inline uint32_t _do_efscfsf (uint32_t val)
|
2141 |
{ |
2142 |
CPU_FloatU u; |
2143 |
float32 tmp; |
2144 |
|
2145 |
u.f = int32_to_float32(val, &env->spe_status); |
2146 |
tmp = int64_to_float32(1ULL << 32, &env->spe_status); |
2147 |
u.f = float32_div(u.f, tmp, &env->spe_status); |
2148 |
|
2149 |
return u.l;
|
2150 |
} |
2151 |
|
2152 |
static always_inline uint32_t _do_efscfuf (uint32_t val)
|
2153 |
{ |
2154 |
CPU_FloatU u; |
2155 |
float32 tmp; |
2156 |
|
2157 |
u.f = uint32_to_float32(val, &env->spe_status); |
2158 |
tmp = uint64_to_float32(1ULL << 32, &env->spe_status); |
2159 |
u.f = float32_div(u.f, tmp, &env->spe_status); |
2160 |
|
2161 |
return u.l;
|
2162 |
} |
2163 |
|
2164 |
static always_inline int32_t _do_efsctsf (uint32_t val)
|
2165 |
{ |
2166 |
CPU_FloatU u; |
2167 |
float32 tmp; |
2168 |
|
2169 |
u.l = val; |
2170 |
/* NaN are not treated the same way IEEE 754 does */
|
2171 |
if (unlikely(isnan(u.f)))
|
2172 |
return 0; |
2173 |
tmp = uint64_to_float32(1ULL << 32, &env->spe_status); |
2174 |
u.f = float32_mul(u.f, tmp, &env->spe_status); |
2175 |
|
2176 |
return float32_to_int32(u.f, &env->spe_status);
|
2177 |
} |
2178 |
|
2179 |
static always_inline uint32_t _do_efsctuf (uint32_t val)
|
2180 |
{ |
2181 |
CPU_FloatU u; |
2182 |
float32 tmp; |
2183 |
|
2184 |
u.l = val; |
2185 |
/* NaN are not treated the same way IEEE 754 does */
|
2186 |
if (unlikely(isnan(u.f)))
|
2187 |
return 0; |
2188 |
tmp = uint64_to_float32(1ULL << 32, &env->spe_status); |
2189 |
u.f = float32_mul(u.f, tmp, &env->spe_status); |
2190 |
|
2191 |
return float32_to_uint32(u.f, &env->spe_status);
|
2192 |
} |
2193 |
|
2194 |
static always_inline int32_t _do_efsctsfz (uint32_t val)
|
2195 |
{ |
2196 |
CPU_FloatU u; |
2197 |
float32 tmp; |
2198 |
|
2199 |
u.l = val; |
2200 |
/* NaN are not treated the same way IEEE 754 does */
|
2201 |
if (unlikely(isnan(u.f)))
|
2202 |
return 0; |
2203 |
tmp = uint64_to_float32(1ULL << 32, &env->spe_status); |
2204 |
u.f = float32_mul(u.f, tmp, &env->spe_status); |
2205 |
|
2206 |
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
|
2207 |
} |
2208 |
|
2209 |
static always_inline uint32_t _do_efsctufz (uint32_t val)
|
2210 |
{ |
2211 |
CPU_FloatU u; |
2212 |
float32 tmp; |
2213 |
|
2214 |
u.l = val; |
2215 |
/* NaN are not treated the same way IEEE 754 does */
|
2216 |
if (unlikely(isnan(u.f)))
|
2217 |
return 0; |
2218 |
tmp = uint64_to_float32(1ULL << 32, &env->spe_status); |
2219 |
u.f = float32_mul(u.f, tmp, &env->spe_status); |
2220 |
|
2221 |
return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
|
2222 |
} |
2223 |
|
2224 |
void do_efscfsf (void) |
2225 |
{ |
2226 |
T0_64 = _do_efscfsf(T0_64); |
2227 |
} |
2228 |
|
2229 |
void do_efscfuf (void) |
2230 |
{ |
2231 |
T0_64 = _do_efscfuf(T0_64); |
2232 |
} |
2233 |
|
2234 |
void do_efsctsf (void) |
2235 |
{ |
2236 |
T0_64 = _do_efsctsf(T0_64); |
2237 |
} |
2238 |
|
2239 |
void do_efsctuf (void) |
2240 |
{ |
2241 |
T0_64 = _do_efsctuf(T0_64); |
2242 |
} |
2243 |
|
2244 |
void do_efsctsfz (void) |
2245 |
{ |
2246 |
T0_64 = _do_efsctsfz(T0_64); |
2247 |
} |
2248 |
|
2249 |
void do_efsctufz (void) |
2250 |
{ |
2251 |
T0_64 = _do_efsctufz(T0_64); |
2252 |
} |
2253 |
|
2254 |
/* Double precision floating point helpers */
|
2255 |
static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2) |
2256 |
{ |
2257 |
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
2258 |
return _do_efdtstlt(op1, op2);
|
2259 |
} |
2260 |
|
2261 |
static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2) |
2262 |
{ |
2263 |
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
2264 |
return _do_efdtstgt(op1, op2);
|
2265 |
} |
2266 |
|
2267 |
static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2) |
2268 |
{ |
2269 |
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
2270 |
return _do_efdtsteq(op1, op2);
|
2271 |
} |
2272 |
|
2273 |
void do_efdcmplt (void) |
2274 |
{ |
2275 |
T0 = _do_efdcmplt(T0_64, T1_64); |
2276 |
} |
2277 |
|
2278 |
void do_efdcmpgt (void) |
2279 |
{ |
2280 |
T0 = _do_efdcmpgt(T0_64, T1_64); |
2281 |
} |
2282 |
|
2283 |
void do_efdcmpeq (void) |
2284 |
{ |
2285 |
T0 = _do_efdcmpeq(T0_64, T1_64); |
2286 |
} |
2287 |
|
2288 |
/* Double precision floating-point conversion to/from integer */
|
2289 |
static always_inline uint64_t _do_efdcfsi (int64_t val)
|
2290 |
{ |
2291 |
CPU_DoubleU u; |
2292 |
|
2293 |
u.d = int64_to_float64(val, &env->spe_status); |
2294 |
|
2295 |
return u.ll;
|
2296 |
} |
2297 |
|
2298 |
static always_inline uint64_t _do_efdcfui (uint64_t val)
|
2299 |
{ |
2300 |
CPU_DoubleU u; |
2301 |
|
2302 |
u.d = uint64_to_float64(val, &env->spe_status); |
2303 |
|
2304 |
return u.ll;
|
2305 |
} |
2306 |
|
2307 |
static always_inline int64_t _do_efdctsi (uint64_t val)
|
2308 |
{ |
2309 |
CPU_DoubleU u; |
2310 |
|
2311 |
u.ll = val; |
2312 |
/* NaN are not treated the same way IEEE 754 does */
|
2313 |
if (unlikely(isnan(u.d)))
|
2314 |
return 0; |
2315 |
|
2316 |
return float64_to_int64(u.d, &env->spe_status);
|
2317 |
} |
2318 |
|
2319 |
static always_inline uint64_t _do_efdctui (uint64_t val)
|
2320 |
{ |
2321 |
CPU_DoubleU u; |
2322 |
|
2323 |
u.ll = val; |
2324 |
/* NaN are not treated the same way IEEE 754 does */
|
2325 |
if (unlikely(isnan(u.d)))
|
2326 |
return 0; |
2327 |
|
2328 |
return float64_to_uint64(u.d, &env->spe_status);
|
2329 |
} |
2330 |
|
2331 |
static always_inline int64_t _do_efdctsiz (uint64_t val)
|
2332 |
{ |
2333 |
CPU_DoubleU u; |
2334 |
|
2335 |
u.ll = val; |
2336 |
/* NaN are not treated the same way IEEE 754 does */
|
2337 |
if (unlikely(isnan(u.d)))
|
2338 |
return 0; |
2339 |
|
2340 |
return float64_to_int64_round_to_zero(u.d, &env->spe_status);
|
2341 |
} |
2342 |
|
2343 |
static always_inline uint64_t _do_efdctuiz (uint64_t val)
|
2344 |
{ |
2345 |
CPU_DoubleU u; |
2346 |
|
2347 |
u.ll = val; |
2348 |
/* NaN are not treated the same way IEEE 754 does */
|
2349 |
if (unlikely(isnan(u.d)))
|
2350 |
return 0; |
2351 |
|
2352 |
return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
|
2353 |
} |
2354 |
|
2355 |
void do_efdcfsi (void) |
2356 |
{ |
2357 |
T0_64 = _do_efdcfsi(T0_64); |
2358 |
} |
2359 |
|
2360 |
void do_efdcfui (void) |
2361 |
{ |
2362 |
T0_64 = _do_efdcfui(T0_64); |
2363 |
} |
2364 |
|
2365 |
void do_efdctsi (void) |
2366 |
{ |
2367 |
T0_64 = _do_efdctsi(T0_64); |
2368 |
} |
2369 |
|
2370 |
void do_efdctui (void) |
2371 |
{ |
2372 |
T0_64 = _do_efdctui(T0_64); |
2373 |
} |
2374 |
|
2375 |
void do_efdctsiz (void) |
2376 |
{ |
2377 |
T0_64 = _do_efdctsiz(T0_64); |
2378 |
} |
2379 |
|
2380 |
void do_efdctuiz (void) |
2381 |
{ |
2382 |
T0_64 = _do_efdctuiz(T0_64); |
2383 |
} |
2384 |
|
2385 |
/* Double precision floating-point conversion to/from fractional */
|
2386 |
static always_inline uint64_t _do_efdcfsf (int64_t val)
|
2387 |
{ |
2388 |
CPU_DoubleU u; |
2389 |
float64 tmp; |
2390 |
|
2391 |
u.d = int32_to_float64(val, &env->spe_status); |
2392 |
tmp = int64_to_float64(1ULL << 32, &env->spe_status); |
2393 |
u.d = float64_div(u.d, tmp, &env->spe_status); |
2394 |
|
2395 |
return u.ll;
|
2396 |
} |
2397 |
|
2398 |
static always_inline uint64_t _do_efdcfuf (uint64_t val)
|
2399 |
{ |
2400 |
CPU_DoubleU u; |
2401 |
float64 tmp; |
2402 |
|
2403 |
u.d = uint32_to_float64(val, &env->spe_status); |
2404 |
tmp = int64_to_float64(1ULL << 32, &env->spe_status); |
2405 |
u.d = float64_div(u.d, tmp, &env->spe_status); |
2406 |
|
2407 |
return u.ll;
|
2408 |
} |
2409 |
|
2410 |
static always_inline int64_t _do_efdctsf (uint64_t val)
|
2411 |
{ |
2412 |
CPU_DoubleU u; |
2413 |
float64 tmp; |
2414 |
|
2415 |
u.ll = val; |
2416 |
/* NaN are not treated the same way IEEE 754 does */
|
2417 |
if (unlikely(isnan(u.d)))
|
2418 |
return 0; |
2419 |
tmp = uint64_to_float64(1ULL << 32, &env->spe_status); |
2420 |
u.d = float64_mul(u.d, tmp, &env->spe_status); |
2421 |
|
2422 |
return float64_to_int32(u.d, &env->spe_status);
|
2423 |
} |
2424 |
|
2425 |
static always_inline uint64_t _do_efdctuf (uint64_t val)
|
2426 |
{ |
2427 |
CPU_DoubleU u; |
2428 |
float64 tmp; |
2429 |
|
2430 |
u.ll = val; |
2431 |
/* NaN are not treated the same way IEEE 754 does */
|
2432 |
if (unlikely(isnan(u.d)))
|
2433 |
return 0; |
2434 |
tmp = uint64_to_float64(1ULL << 32, &env->spe_status); |
2435 |
u.d = float64_mul(u.d, tmp, &env->spe_status); |
2436 |
|
2437 |
return float64_to_uint32(u.d, &env->spe_status);
|
2438 |
} |
2439 |
|
2440 |
static always_inline int64_t _do_efdctsfz (uint64_t val)
|
2441 |
{ |
2442 |
CPU_DoubleU u; |
2443 |
float64 tmp; |
2444 |
|
2445 |
u.ll = val; |
2446 |
/* NaN are not treated the same way IEEE 754 does */
|
2447 |
if (unlikely(isnan(u.d)))
|
2448 |
return 0; |
2449 |
tmp = uint64_to_float64(1ULL << 32, &env->spe_status); |
2450 |
u.d = float64_mul(u.d, tmp, &env->spe_status); |
2451 |
|
2452 |
return float64_to_int32_round_to_zero(u.d, &env->spe_status);
|
2453 |
} |
2454 |
|
2455 |
static always_inline uint64_t _do_efdctufz (uint64_t val)
|
2456 |
{ |
2457 |
CPU_DoubleU u; |
2458 |
float64 tmp; |
2459 |
|
2460 |
u.ll = val; |
2461 |
/* NaN are not treated the same way IEEE 754 does */
|
2462 |
if (unlikely(isnan(u.d)))
|
2463 |
return 0; |
2464 |
tmp = uint64_to_float64(1ULL << 32, &env->spe_status); |
2465 |
u.d = float64_mul(u.d, tmp, &env->spe_status); |
2466 |
|
2467 |
return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
|
2468 |
} |
2469 |
|
2470 |
void do_efdcfsf (void) |
2471 |
{ |
2472 |
T0_64 = _do_efdcfsf(T0_64); |
2473 |
} |
2474 |
|
2475 |
void do_efdcfuf (void) |
2476 |
{ |
2477 |
T0_64 = _do_efdcfuf(T0_64); |
2478 |
} |
2479 |
|
2480 |
void do_efdctsf (void) |
2481 |
{ |
2482 |
T0_64 = _do_efdctsf(T0_64); |
2483 |
} |
2484 |
|
2485 |
void do_efdctuf (void) |
2486 |
{ |
2487 |
T0_64 = _do_efdctuf(T0_64); |
2488 |
} |
2489 |
|
2490 |
void do_efdctsfz (void) |
2491 |
{ |
2492 |
T0_64 = _do_efdctsfz(T0_64); |
2493 |
} |
2494 |
|
2495 |
void do_efdctufz (void) |
2496 |
{ |
2497 |
T0_64 = _do_efdctufz(T0_64); |
2498 |
} |
2499 |
|
2500 |
/* Floating point conversion between single and double precision */
|
2501 |
static always_inline uint32_t _do_efscfd (uint64_t val)
|
2502 |
{ |
2503 |
CPU_DoubleU u1; |
2504 |
CPU_FloatU u2; |
2505 |
|
2506 |
u1.ll = val; |
2507 |
u2.f = float64_to_float32(u1.d, &env->spe_status); |
2508 |
|
2509 |
return u2.l;
|
2510 |
} |
2511 |
|
2512 |
static always_inline uint64_t _do_efdcfs (uint32_t val)
|
2513 |
{ |
2514 |
CPU_DoubleU u2; |
2515 |
CPU_FloatU u1; |
2516 |
|
2517 |
u1.l = val; |
2518 |
u2.d = float32_to_float64(u1.f, &env->spe_status); |
2519 |
|
2520 |
return u2.ll;
|
2521 |
} |
2522 |
|
2523 |
void do_efscfd (void) |
2524 |
{ |
2525 |
T0_64 = _do_efscfd(T0_64); |
2526 |
} |
2527 |
|
2528 |
void do_efdcfs (void) |
2529 |
{ |
2530 |
T0_64 = _do_efdcfs(T0_64); |
2531 |
} |
2532 |
|
2533 |
/* Single precision fixed-point vector arithmetic */
|
2534 |
/* evfsabs */
|
2535 |
DO_SPE_OP1(fsabs); |
2536 |
/* evfsnabs */
|
2537 |
DO_SPE_OP1(fsnabs); |
2538 |
/* evfsneg */
|
2539 |
DO_SPE_OP1(fsneg); |
2540 |
/* evfsadd */
|
2541 |
DO_SPE_OP2(fsadd); |
2542 |
/* evfssub */
|
2543 |
DO_SPE_OP2(fssub); |
2544 |
/* evfsmul */
|
2545 |
DO_SPE_OP2(fsmul); |
2546 |
/* evfsdiv */
|
2547 |
DO_SPE_OP2(fsdiv); |
2548 |
|
2549 |
/* Single-precision floating-point comparisons */
|
2550 |
static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2) |
2551 |
{ |
2552 |
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
2553 |
return _do_efststlt(op1, op2);
|
2554 |
} |
2555 |
|
2556 |
static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2) |
2557 |
{ |
2558 |
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
2559 |
return _do_efststgt(op1, op2);
|
2560 |
} |
2561 |
|
2562 |
static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2) |
2563 |
{ |
2564 |
/* XXX: TODO: test special values (NaN, infinites, ...) */
|
2565 |
return _do_efststeq(op1, op2);
|
2566 |
} |
2567 |
|
2568 |
void do_efscmplt (void) |
2569 |
{ |
2570 |
T0 = _do_efscmplt(T0_64, T1_64); |
2571 |
} |
2572 |
|
2573 |
void do_efscmpgt (void) |
2574 |
{ |
2575 |
T0 = _do_efscmpgt(T0_64, T1_64); |
2576 |
} |
2577 |
|
2578 |
void do_efscmpeq (void) |
2579 |
{ |
2580 |
T0 = _do_efscmpeq(T0_64, T1_64); |
2581 |
} |
2582 |
|
2583 |
/* Single-precision floating-point vector comparisons */
|
2584 |
/* evfscmplt */
|
2585 |
DO_SPE_CMP(fscmplt); |
2586 |
/* evfscmpgt */
|
2587 |
DO_SPE_CMP(fscmpgt); |
2588 |
/* evfscmpeq */
|
2589 |
DO_SPE_CMP(fscmpeq); |
2590 |
/* evfststlt */
|
2591 |
DO_SPE_CMP(fststlt); |
2592 |
/* evfststgt */
|
2593 |
DO_SPE_CMP(fststgt); |
2594 |
/* evfststeq */
|
2595 |
DO_SPE_CMP(fststeq); |
2596 |
|
2597 |
/* Single-precision floating-point vector conversions */
|
2598 |
/* evfscfsi */
|
2599 |
DO_SPE_OP1(fscfsi); |
2600 |
/* evfscfui */
|
2601 |
DO_SPE_OP1(fscfui); |
2602 |
/* evfscfuf */
|
2603 |
DO_SPE_OP1(fscfuf); |
2604 |
/* evfscfsf */
|
2605 |
DO_SPE_OP1(fscfsf); |
2606 |
/* evfsctsi */
|
2607 |
DO_SPE_OP1(fsctsi); |
2608 |
/* evfsctui */
|
2609 |
DO_SPE_OP1(fsctui); |
2610 |
/* evfsctsiz */
|
2611 |
DO_SPE_OP1(fsctsiz); |
2612 |
/* evfsctuiz */
|
2613 |
DO_SPE_OP1(fsctuiz); |
2614 |
/* evfsctsf */
|
2615 |
DO_SPE_OP1(fsctsf); |
2616 |
/* evfsctuf */
|
2617 |
DO_SPE_OP1(fsctuf); |
2618 |
|
2619 |
/*****************************************************************************/
|
2620 |
/* Softmmu support */
|
2621 |
#if !defined (CONFIG_USER_ONLY)
|
2622 |
|
2623 |
#define MMUSUFFIX _mmu
|
2624 |
|
2625 |
#define SHIFT 0 |
2626 |
#include "softmmu_template.h" |
2627 |
|
2628 |
#define SHIFT 1 |
2629 |
#include "softmmu_template.h" |
2630 |
|
2631 |
#define SHIFT 2 |
2632 |
#include "softmmu_template.h" |
2633 |
|
2634 |
#define SHIFT 3 |
2635 |
#include "softmmu_template.h" |
2636 |
|
2637 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
2638 |
NULL, it means that the function was called in C code (i.e. not
|
2639 |
from generated code or from helper.c) */
|
2640 |
/* XXX: fix it to restore all registers */
|
2641 |
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
2642 |
{ |
2643 |
TranslationBlock *tb; |
2644 |
CPUState *saved_env; |
2645 |
unsigned long pc; |
2646 |
int ret;
|
2647 |
|
2648 |
/* XXX: hack to restore env in all cases, even if not called from
|
2649 |
generated code */
|
2650 |
saved_env = env; |
2651 |
env = cpu_single_env; |
2652 |
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
2653 |
if (unlikely(ret != 0)) { |
2654 |
if (likely(retaddr)) {
|
2655 |
/* now we have a real cpu fault */
|
2656 |
pc = (unsigned long)retaddr; |
2657 |
tb = tb_find_pc(pc); |
2658 |
if (likely(tb)) {
|
2659 |
/* the PC is inside the translated code. It means that we have
|
2660 |
a virtual CPU fault */
|
2661 |
cpu_restore_state(tb, env, pc, NULL);
|
2662 |
} |
2663 |
} |
2664 |
do_raise_exception_err(env->exception_index, env->error_code); |
2665 |
} |
2666 |
env = saved_env; |
2667 |
} |
2668 |
|
2669 |
/* Software driven TLBs management */
|
2670 |
/* PowerPC 602/603 software TLB load instructions helpers */
|
2671 |
void do_load_6xx_tlb (int is_code) |
2672 |
{ |
2673 |
target_ulong RPN, CMP, EPN; |
2674 |
int way;
|
2675 |
|
2676 |
RPN = env->spr[SPR_RPA]; |
2677 |
if (is_code) {
|
2678 |
CMP = env->spr[SPR_ICMP]; |
2679 |
EPN = env->spr[SPR_IMISS]; |
2680 |
} else {
|
2681 |
CMP = env->spr[SPR_DCMP]; |
2682 |
EPN = env->spr[SPR_DMISS]; |
2683 |
} |
2684 |
way = (env->spr[SPR_SRR1] >> 17) & 1; |
2685 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2686 |
if (loglevel != 0) { |
2687 |
fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX |
2688 |
" PTE1 " ADDRX " way %d\n", |
2689 |
__func__, T0, EPN, CMP, RPN, way); |
2690 |
} |
2691 |
#endif
|
2692 |
/* Store this TLB */
|
2693 |
ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK), |
2694 |
way, is_code, CMP, RPN); |
2695 |
} |
2696 |
|
2697 |
void do_load_74xx_tlb (int is_code) |
2698 |
{ |
2699 |
target_ulong RPN, CMP, EPN; |
2700 |
int way;
|
2701 |
|
2702 |
RPN = env->spr[SPR_PTELO]; |
2703 |
CMP = env->spr[SPR_PTEHI]; |
2704 |
EPN = env->spr[SPR_TLBMISS] & ~0x3;
|
2705 |
way = env->spr[SPR_TLBMISS] & 0x3;
|
2706 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2707 |
if (loglevel != 0) { |
2708 |
fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX |
2709 |
" PTE1 " ADDRX " way %d\n", |
2710 |
__func__, T0, EPN, CMP, RPN, way); |
2711 |
} |
2712 |
#endif
|
2713 |
/* Store this TLB */
|
2714 |
ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK), |
2715 |
way, is_code, CMP, RPN); |
2716 |
} |
2717 |
|
2718 |
static always_inline target_ulong booke_tlb_to_page_size (int size) |
2719 |
{ |
2720 |
return 1024 << (2 * size); |
2721 |
} |
2722 |
|
2723 |
static always_inline int booke_page_size_to_tlb (target_ulong page_size) |
2724 |
{ |
2725 |
int size;
|
2726 |
|
2727 |
switch (page_size) {
|
2728 |
case 0x00000400UL: |
2729 |
size = 0x0;
|
2730 |
break;
|
2731 |
case 0x00001000UL: |
2732 |
size = 0x1;
|
2733 |
break;
|
2734 |
case 0x00004000UL: |
2735 |
size = 0x2;
|
2736 |
break;
|
2737 |
case 0x00010000UL: |
2738 |
size = 0x3;
|
2739 |
break;
|
2740 |
case 0x00040000UL: |
2741 |
size = 0x4;
|
2742 |
break;
|
2743 |
case 0x00100000UL: |
2744 |
size = 0x5;
|
2745 |
break;
|
2746 |
case 0x00400000UL: |
2747 |
size = 0x6;
|
2748 |
break;
|
2749 |
case 0x01000000UL: |
2750 |
size = 0x7;
|
2751 |
break;
|
2752 |
case 0x04000000UL: |
2753 |
size = 0x8;
|
2754 |
break;
|
2755 |
case 0x10000000UL: |
2756 |
size = 0x9;
|
2757 |
break;
|
2758 |
case 0x40000000UL: |
2759 |
size = 0xA;
|
2760 |
break;
|
2761 |
#if defined (TARGET_PPC64)
|
2762 |
case 0x000100000000ULL: |
2763 |
size = 0xB;
|
2764 |
break;
|
2765 |
case 0x000400000000ULL: |
2766 |
size = 0xC;
|
2767 |
break;
|
2768 |
case 0x001000000000ULL: |
2769 |
size = 0xD;
|
2770 |
break;
|
2771 |
case 0x004000000000ULL: |
2772 |
size = 0xE;
|
2773 |
break;
|
2774 |
case 0x010000000000ULL: |
2775 |
size = 0xF;
|
2776 |
break;
|
2777 |
#endif
|
2778 |
default:
|
2779 |
size = -1;
|
2780 |
break;
|
2781 |
} |
2782 |
|
2783 |
return size;
|
2784 |
} |
2785 |
|
2786 |
/* Helpers for 4xx TLB management */
|
2787 |
void do_4xx_tlbre_lo (void) |
2788 |
{ |
2789 |
ppcemb_tlb_t *tlb; |
2790 |
int size;
|
2791 |
|
2792 |
T0 &= 0x3F;
|
2793 |
tlb = &env->tlb[T0].tlbe; |
2794 |
T0 = tlb->EPN; |
2795 |
if (tlb->prot & PAGE_VALID)
|
2796 |
T0 |= 0x400;
|
2797 |
size = booke_page_size_to_tlb(tlb->size); |
2798 |
if (size < 0 || size > 0x7) |
2799 |
size = 1;
|
2800 |
T0 |= size << 7;
|
2801 |
env->spr[SPR_40x_PID] = tlb->PID; |
2802 |
} |
2803 |
|
2804 |
void do_4xx_tlbre_hi (void) |
2805 |
{ |
2806 |
ppcemb_tlb_t *tlb; |
2807 |
|
2808 |
T0 &= 0x3F;
|
2809 |
tlb = &env->tlb[T0].tlbe; |
2810 |
T0 = tlb->RPN; |
2811 |
if (tlb->prot & PAGE_EXEC)
|
2812 |
T0 |= 0x200;
|
2813 |
if (tlb->prot & PAGE_WRITE)
|
2814 |
T0 |= 0x100;
|
2815 |
} |
2816 |
|
2817 |
void do_4xx_tlbwe_hi (void) |
2818 |
{ |
2819 |
ppcemb_tlb_t *tlb; |
2820 |
target_ulong page, end; |
2821 |
|
2822 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2823 |
if (loglevel != 0) { |
2824 |
fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1); |
2825 |
} |
2826 |
#endif
|
2827 |
T0 &= 0x3F;
|
2828 |
tlb = &env->tlb[T0].tlbe; |
2829 |
/* Invalidate previous TLB (if it's valid) */
|
2830 |
if (tlb->prot & PAGE_VALID) {
|
2831 |
end = tlb->EPN + tlb->size; |
2832 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2833 |
if (loglevel != 0) { |
2834 |
fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
|
2835 |
" end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end); |
2836 |
} |
2837 |
#endif
|
2838 |
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
2839 |
tlb_flush_page(env, page); |
2840 |
} |
2841 |
tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7); |
2842 |
/* We cannot handle TLB size < TARGET_PAGE_SIZE.
|
2843 |
* If this ever occurs, one should use the ppcemb target instead
|
2844 |
* of the ppc or ppc64 one
|
2845 |
*/
|
2846 |
if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) { |
2847 |
cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u " |
2848 |
"are not supported (%d)\n",
|
2849 |
tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7)); |
2850 |
} |
2851 |
tlb->EPN = T1 & ~(tlb->size - 1);
|
2852 |
if (T1 & 0x40) |
2853 |
tlb->prot |= PAGE_VALID; |
2854 |
else
|
2855 |
tlb->prot &= ~PAGE_VALID; |
2856 |
if (T1 & 0x20) { |
2857 |
/* XXX: TO BE FIXED */
|
2858 |
cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
|
2859 |
} |
2860 |
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
|
2861 |
tlb->attr = T1 & 0xFF;
|
2862 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2863 |
if (loglevel != 0) { |
2864 |
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX |
2865 |
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__, |
2866 |
(int)T0, tlb->RPN, tlb->EPN, tlb->size,
|
2867 |
tlb->prot & PAGE_READ ? 'r' : '-', |
2868 |
tlb->prot & PAGE_WRITE ? 'w' : '-', |
2869 |
tlb->prot & PAGE_EXEC ? 'x' : '-', |
2870 |
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); |
2871 |
} |
2872 |
#endif
|
2873 |
/* Invalidate new TLB (if valid) */
|
2874 |
if (tlb->prot & PAGE_VALID) {
|
2875 |
end = tlb->EPN + tlb->size; |
2876 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2877 |
if (loglevel != 0) { |
2878 |
fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
|
2879 |
" end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end); |
2880 |
} |
2881 |
#endif
|
2882 |
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
2883 |
tlb_flush_page(env, page); |
2884 |
} |
2885 |
} |
2886 |
|
2887 |
void do_4xx_tlbwe_lo (void) |
2888 |
{ |
2889 |
ppcemb_tlb_t *tlb; |
2890 |
|
2891 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2892 |
if (loglevel != 0) { |
2893 |
fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1); |
2894 |
} |
2895 |
#endif
|
2896 |
T0 &= 0x3F;
|
2897 |
tlb = &env->tlb[T0].tlbe; |
2898 |
tlb->RPN = T1 & 0xFFFFFC00;
|
2899 |
tlb->prot = PAGE_READ; |
2900 |
if (T1 & 0x200) |
2901 |
tlb->prot |= PAGE_EXEC; |
2902 |
if (T1 & 0x100) |
2903 |
tlb->prot |= PAGE_WRITE; |
2904 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2905 |
if (loglevel != 0) { |
2906 |
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX |
2907 |
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__, |
2908 |
(int)T0, tlb->RPN, tlb->EPN, tlb->size,
|
2909 |
tlb->prot & PAGE_READ ? 'r' : '-', |
2910 |
tlb->prot & PAGE_WRITE ? 'w' : '-', |
2911 |
tlb->prot & PAGE_EXEC ? 'x' : '-', |
2912 |
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); |
2913 |
} |
2914 |
#endif
|
2915 |
} |
2916 |
|
2917 |
/* PowerPC 440 TLB management */
|
2918 |
void do_440_tlbwe (int word) |
2919 |
{ |
2920 |
ppcemb_tlb_t *tlb; |
2921 |
target_ulong EPN, RPN, size; |
2922 |
int do_flush_tlbs;
|
2923 |
|
2924 |
#if defined (DEBUG_SOFTWARE_TLB)
|
2925 |
if (loglevel != 0) { |
2926 |
fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n", |
2927 |
__func__, word, T0, T1); |
2928 |
} |
2929 |
#endif
|
2930 |
do_flush_tlbs = 0;
|
2931 |
T0 &= 0x3F;
|
2932 |
tlb = &env->tlb[T0].tlbe; |
2933 |
switch (word) {
|
2934 |
default:
|
2935 |
/* Just here to please gcc */
|
2936 |
case 0: |
2937 |
EPN = T1 & 0xFFFFFC00;
|
2938 |
if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
|
2939 |
do_flush_tlbs = 1;
|
2940 |
tlb->EPN = EPN; |
2941 |
size = booke_tlb_to_page_size((T1 >> 4) & 0xF); |
2942 |
if ((tlb->prot & PAGE_VALID) && tlb->size < size)
|
2943 |
do_flush_tlbs = 1;
|
2944 |
tlb->size = size; |
2945 |
tlb->attr &= ~0x1;
|
2946 |
tlb->attr |= (T1 >> 8) & 1; |
2947 |
if (T1 & 0x200) { |
2948 |
tlb->prot |= PAGE_VALID; |
2949 |
} else {
|
2950 |
if (tlb->prot & PAGE_VALID) {
|
2951 |
tlb->prot &= ~PAGE_VALID; |
2952 |
do_flush_tlbs = 1;
|
2953 |
} |
2954 |
} |
2955 |
tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
|
2956 |
if (do_flush_tlbs)
|
2957 |
tlb_flush(env, 1);
|
2958 |
break;
|
2959 |
case 1: |
2960 |
RPN = T1 & 0xFFFFFC0F;
|
2961 |
if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
|
2962 |
tlb_flush(env, 1);
|
2963 |
tlb->RPN = RPN; |
2964 |
break;
|
2965 |
case 2: |
2966 |
tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00); |
2967 |
tlb->prot = tlb->prot & PAGE_VALID; |
2968 |
if (T1 & 0x1) |
2969 |
tlb->prot |= PAGE_READ << 4;
|
2970 |
if (T1 & 0x2) |
2971 |
tlb->prot |= PAGE_WRITE << 4;
|
2972 |
if (T1 & 0x4) |
2973 |
tlb->prot |= PAGE_EXEC << 4;
|
2974 |
if (T1 & 0x8) |
2975 |
tlb->prot |= PAGE_READ; |
2976 |
if (T1 & 0x10) |
2977 |
tlb->prot |= PAGE_WRITE; |
2978 |
if (T1 & 0x20) |
2979 |
tlb->prot |= PAGE_EXEC; |
2980 |
break;
|
2981 |
} |
2982 |
} |
2983 |
|
2984 |
void do_440_tlbre (int word) |
2985 |
{ |
2986 |
ppcemb_tlb_t *tlb; |
2987 |
int size;
|
2988 |
|
2989 |
T0 &= 0x3F;
|
2990 |
tlb = &env->tlb[T0].tlbe; |
2991 |
switch (word) {
|
2992 |
default:
|
2993 |
/* Just here to please gcc */
|
2994 |
case 0: |
2995 |
T0 = tlb->EPN; |
2996 |
size = booke_page_size_to_tlb(tlb->size); |
2997 |
if (size < 0 || size > 0xF) |
2998 |
size = 1;
|
2999 |
T0 |= size << 4;
|
3000 |
if (tlb->attr & 0x1) |
3001 |
T0 |= 0x100;
|
3002 |
if (tlb->prot & PAGE_VALID)
|
3003 |
T0 |= 0x200;
|
3004 |
env->spr[SPR_440_MMUCR] &= ~0x000000FF;
|
3005 |
env->spr[SPR_440_MMUCR] |= tlb->PID; |
3006 |
break;
|
3007 |
case 1: |
3008 |
T0 = tlb->RPN; |
3009 |
break;
|
3010 |
case 2: |
3011 |
T0 = tlb->attr & ~0x1;
|
3012 |
if (tlb->prot & (PAGE_READ << 4)) |
3013 |
T0 |= 0x1;
|
3014 |
if (tlb->prot & (PAGE_WRITE << 4)) |
3015 |
T0 |= 0x2;
|
3016 |
if (tlb->prot & (PAGE_EXEC << 4)) |
3017 |
T0 |= 0x4;
|
3018 |
if (tlb->prot & PAGE_READ)
|
3019 |
T0 |= 0x8;
|
3020 |
if (tlb->prot & PAGE_WRITE)
|
3021 |
T0 |= 0x10;
|
3022 |
if (tlb->prot & PAGE_EXEC)
|
3023 |
T0 |= 0x20;
|
3024 |
break;
|
3025 |
} |
3026 |
} |
3027 |
#endif /* !CONFIG_USER_ONLY */ |