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1 | 81fdc5f8 | ths | /*
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2 | 81fdc5f8 | ths | * CRIS virtual CPU header
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3 | 81fdc5f8 | ths | *
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4 | 81fdc5f8 | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 81fdc5f8 | ths | * Written by Edgar E. Iglesias
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6 | 81fdc5f8 | ths | *
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7 | 81fdc5f8 | ths | * This library is free software; you can redistribute it and/or
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8 | 81fdc5f8 | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 81fdc5f8 | ths | * License as published by the Free Software Foundation; either
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10 | 81fdc5f8 | ths | * version 2 of the License, or (at your option) any later version.
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11 | 81fdc5f8 | ths | *
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12 | 81fdc5f8 | ths | * This library is distributed in the hope that it will be useful,
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13 | 81fdc5f8 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 81fdc5f8 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 81fdc5f8 | ths | * General Public License for more details.
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16 | 81fdc5f8 | ths | *
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17 | 81fdc5f8 | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 81fdc5f8 | ths | * License along with this library; if not, write to the Free Software
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19 | 81fdc5f8 | ths | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 81fdc5f8 | ths | */
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21 | 81fdc5f8 | ths | #ifndef CPU_CRIS_H
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22 | 81fdc5f8 | ths | #define CPU_CRIS_H
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23 | 81fdc5f8 | ths | |
24 | 81fdc5f8 | ths | #define TARGET_LONG_BITS 32 |
25 | 81fdc5f8 | ths | |
26 | 81fdc5f8 | ths | #include "cpu-defs.h" |
27 | 81fdc5f8 | ths | |
28 | 81fdc5f8 | ths | #define TARGET_HAS_ICE 1 |
29 | 81fdc5f8 | ths | |
30 | 81fdc5f8 | ths | #define ELF_MACHINE EM_CRIS
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31 | 81fdc5f8 | ths | |
32 | 1b1a38b0 | edgar_igl | #define EXCP_NMI 1 |
33 | 1b1a38b0 | edgar_igl | #define EXCP_GURU 2 |
34 | 1b1a38b0 | edgar_igl | #define EXCP_BUSFAULT 3 |
35 | 1b1a38b0 | edgar_igl | #define EXCP_IRQ 4 |
36 | 1b1a38b0 | edgar_igl | #define EXCP_BREAK 5 |
37 | 81fdc5f8 | ths | |
38 | b41f7df0 | edgar_igl | /* Register aliases. R0 - R15 */
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39 | b41f7df0 | edgar_igl | #define R_FP 8 |
40 | b41f7df0 | edgar_igl | #define R_SP 14 |
41 | b41f7df0 | edgar_igl | #define R_ACR 15 |
42 | b41f7df0 | edgar_igl | |
43 | b41f7df0 | edgar_igl | /* Support regs, P0 - P15 */
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44 | b41f7df0 | edgar_igl | #define PR_BZ 0 |
45 | b41f7df0 | edgar_igl | #define PR_VR 1 |
46 | b41f7df0 | edgar_igl | #define PR_PID 2 |
47 | b41f7df0 | edgar_igl | #define PR_SRS 3 |
48 | b41f7df0 | edgar_igl | #define PR_WZ 4 |
49 | b41f7df0 | edgar_igl | #define PR_EXS 5 |
50 | b41f7df0 | edgar_igl | #define PR_EDA 6 |
51 | b41f7df0 | edgar_igl | #define PR_MOF 7 |
52 | b41f7df0 | edgar_igl | #define PR_DZ 8 |
53 | b41f7df0 | edgar_igl | #define PR_EBP 9 |
54 | b41f7df0 | edgar_igl | #define PR_ERP 10 |
55 | b41f7df0 | edgar_igl | #define PR_SRP 11 |
56 | 1b1a38b0 | edgar_igl | #define PR_NRP 12 |
57 | b41f7df0 | edgar_igl | #define PR_CCS 13 |
58 | b41f7df0 | edgar_igl | #define PR_USP 14 |
59 | b41f7df0 | edgar_igl | #define PR_SPC 15 |
60 | b41f7df0 | edgar_igl | |
61 | 81fdc5f8 | ths | /* CPU flags. */
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62 | 1b1a38b0 | edgar_igl | #define Q_FLAG 0x80000000 |
63 | 1b1a38b0 | edgar_igl | #define M_FLAG 0x40000000 |
64 | 81fdc5f8 | ths | #define S_FLAG 0x200 |
65 | 81fdc5f8 | ths | #define R_FLAG 0x100 |
66 | 81fdc5f8 | ths | #define P_FLAG 0x80 |
67 | 81fdc5f8 | ths | #define U_FLAG 0x40 |
68 | 81fdc5f8 | ths | #define P_FLAG 0x80 |
69 | 81fdc5f8 | ths | #define U_FLAG 0x40 |
70 | 81fdc5f8 | ths | #define I_FLAG 0x20 |
71 | 81fdc5f8 | ths | #define X_FLAG 0x10 |
72 | 81fdc5f8 | ths | #define N_FLAG 0x08 |
73 | 81fdc5f8 | ths | #define Z_FLAG 0x04 |
74 | 81fdc5f8 | ths | #define V_FLAG 0x02 |
75 | 81fdc5f8 | ths | #define C_FLAG 0x01 |
76 | 81fdc5f8 | ths | #define ALU_FLAGS 0x1F |
77 | 81fdc5f8 | ths | |
78 | 81fdc5f8 | ths | /* Condition codes. */
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79 | 81fdc5f8 | ths | #define CC_CC 0 |
80 | 81fdc5f8 | ths | #define CC_CS 1 |
81 | 81fdc5f8 | ths | #define CC_NE 2 |
82 | 81fdc5f8 | ths | #define CC_EQ 3 |
83 | 81fdc5f8 | ths | #define CC_VC 4 |
84 | 81fdc5f8 | ths | #define CC_VS 5 |
85 | 81fdc5f8 | ths | #define CC_PL 6 |
86 | 81fdc5f8 | ths | #define CC_MI 7 |
87 | 81fdc5f8 | ths | #define CC_LS 8 |
88 | 81fdc5f8 | ths | #define CC_HI 9 |
89 | 81fdc5f8 | ths | #define CC_GE 10 |
90 | 81fdc5f8 | ths | #define CC_LT 11 |
91 | 81fdc5f8 | ths | #define CC_GT 12 |
92 | 81fdc5f8 | ths | #define CC_LE 13 |
93 | 81fdc5f8 | ths | #define CC_A 14 |
94 | 81fdc5f8 | ths | #define CC_P 15 |
95 | 81fdc5f8 | ths | |
96 | 81fdc5f8 | ths | /* Internal flags for the implementation. */
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97 | 81fdc5f8 | ths | #define F_DELAYSLOT 1 |
98 | 81fdc5f8 | ths | |
99 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
100 | 6ebbf390 | j_mayer | |
101 | 81fdc5f8 | ths | typedef struct CPUCRISState { |
102 | 81fdc5f8 | ths | uint32_t regs[16];
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103 | b41f7df0 | edgar_igl | /* P0 - P15 are referred to as special registers in the docs. */
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104 | 81fdc5f8 | ths | uint32_t pregs[16];
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105 | b41f7df0 | edgar_igl | |
106 | b41f7df0 | edgar_igl | /* Pseudo register for the PC. Not directly accessable on CRIS. */
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107 | 81fdc5f8 | ths | uint32_t pc; |
108 | 81fdc5f8 | ths | |
109 | b41f7df0 | edgar_igl | /* Pseudo register for the kernel stack. */
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110 | b41f7df0 | edgar_igl | uint32_t ksp; |
111 | b41f7df0 | edgar_igl | |
112 | cf1d97f0 | edgar_igl | /* Branch. */
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113 | cf1d97f0 | edgar_igl | int dslot;
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114 | 81fdc5f8 | ths | int btaken;
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115 | cf1d97f0 | edgar_igl | uint32_t btarget; |
116 | 81fdc5f8 | ths | |
117 | 81fdc5f8 | ths | /* Condition flag tracking. */
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118 | 81fdc5f8 | ths | uint32_t cc_op; |
119 | 81fdc5f8 | ths | uint32_t cc_mask; |
120 | 81fdc5f8 | ths | uint32_t cc_dest; |
121 | 81fdc5f8 | ths | uint32_t cc_src; |
122 | 81fdc5f8 | ths | uint32_t cc_result; |
123 | 81fdc5f8 | ths | /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
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124 | 81fdc5f8 | ths | int cc_size;
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125 | 30abcfc7 | edgar_igl | /* X flag at the time of cc snapshot. */
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126 | 81fdc5f8 | ths | int cc_x;
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127 | 81fdc5f8 | ths | |
128 | 786c02f1 | edgar_igl | int interrupt_vector;
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129 | 786c02f1 | edgar_igl | int fault_vector;
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130 | 786c02f1 | edgar_igl | int trap_vector;
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131 | 786c02f1 | edgar_igl | |
132 | b41f7df0 | edgar_igl | /* FIXME: add a check in the translator to avoid writing to support
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133 | b41f7df0 | edgar_igl | register sets beyond the 4th. The ISA allows up to 256! but in
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134 | b41f7df0 | edgar_igl | practice there is no core that implements more than 4.
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135 | b41f7df0 | edgar_igl | |
136 | b41f7df0 | edgar_igl | Support function registers are used to control units close to the
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137 | b41f7df0 | edgar_igl | core. Accesses do not pass down the normal hierarchy.
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138 | b41f7df0 | edgar_igl | */
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139 | b41f7df0 | edgar_igl | uint32_t sregs[4][16]; |
140 | b41f7df0 | edgar_igl | |
141 | 44cd42ee | edgar_igl | /* Linear feedback shift reg in the mmu. Used to provide pseudo
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142 | 44cd42ee | edgar_igl | randomness for the 'hint' the mmu gives to sw for chosing valid
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143 | 44cd42ee | edgar_igl | sets on TLB refills. */
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144 | 44cd42ee | edgar_igl | uint32_t mmu_rand_lfsr; |
145 | 44cd42ee | edgar_igl | |
146 | b41f7df0 | edgar_igl | /*
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147 | b41f7df0 | edgar_igl | * We just store the stores to the tlbset here for later evaluation
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148 | b41f7df0 | edgar_igl | * when the hw needs access to them.
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149 | b41f7df0 | edgar_igl | *
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150 | b41f7df0 | edgar_igl | * One for I and another for D.
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151 | b41f7df0 | edgar_igl | */
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152 | b41f7df0 | edgar_igl | struct
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153 | b41f7df0 | edgar_igl | { |
154 | b41f7df0 | edgar_igl | uint32_t hi; |
155 | b41f7df0 | edgar_igl | uint32_t lo; |
156 | b41f7df0 | edgar_igl | } tlbsets[2][4][16]; |
157 | b41f7df0 | edgar_igl | |
158 | 81fdc5f8 | ths | CPU_COMMON |
159 | 81fdc5f8 | ths | } CPUCRISState; |
160 | 81fdc5f8 | ths | |
161 | aaed909a | bellard | CPUCRISState *cpu_cris_init(const char *cpu_model); |
162 | 81fdc5f8 | ths | int cpu_cris_exec(CPUCRISState *s);
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163 | 81fdc5f8 | ths | void cpu_cris_close(CPUCRISState *s);
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164 | 81fdc5f8 | ths | void do_interrupt(CPUCRISState *env);
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165 | 81fdc5f8 | ths | /* you can call this signal handler from your SIGBUS and SIGSEGV
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166 | 81fdc5f8 | ths | signal handlers to inform the virtual CPU of exceptions. non zero
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167 | 81fdc5f8 | ths | is returned if the signal was handled by the virtual CPU. */
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168 | 81fdc5f8 | ths | int cpu_cris_signal_handler(int host_signum, void *pinfo, |
169 | 81fdc5f8 | ths | void *puc);
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170 | 81fdc5f8 | ths | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
171 | e18231a3 | blueswir1 | int is_asi, int size); |
172 | 81fdc5f8 | ths | |
173 | 81fdc5f8 | ths | enum {
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174 | 81fdc5f8 | ths | CC_OP_DYNAMIC, /* Use env->cc_op */
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175 | 81fdc5f8 | ths | CC_OP_FLAGS, |
176 | 81fdc5f8 | ths | CC_OP_CMP, |
177 | 81fdc5f8 | ths | CC_OP_MOVE, |
178 | 81fdc5f8 | ths | CC_OP_ADD, |
179 | 81fdc5f8 | ths | CC_OP_ADDC, |
180 | 81fdc5f8 | ths | CC_OP_MCP, |
181 | 81fdc5f8 | ths | CC_OP_ADDU, |
182 | 81fdc5f8 | ths | CC_OP_SUB, |
183 | 81fdc5f8 | ths | CC_OP_SUBU, |
184 | 81fdc5f8 | ths | CC_OP_NEG, |
185 | 81fdc5f8 | ths | CC_OP_BTST, |
186 | 81fdc5f8 | ths | CC_OP_MULS, |
187 | 81fdc5f8 | ths | CC_OP_MULU, |
188 | 81fdc5f8 | ths | CC_OP_DSTEP, |
189 | 81fdc5f8 | ths | CC_OP_BOUND, |
190 | 81fdc5f8 | ths | |
191 | 81fdc5f8 | ths | CC_OP_OR, |
192 | 81fdc5f8 | ths | CC_OP_AND, |
193 | 81fdc5f8 | ths | CC_OP_XOR, |
194 | 81fdc5f8 | ths | CC_OP_LSL, |
195 | 81fdc5f8 | ths | CC_OP_LSR, |
196 | 81fdc5f8 | ths | CC_OP_ASR, |
197 | 81fdc5f8 | ths | CC_OP_LZ |
198 | 81fdc5f8 | ths | }; |
199 | 81fdc5f8 | ths | |
200 | 81fdc5f8 | ths | /* CRIS uses 8k pages. */
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201 | 81fdc5f8 | ths | #define TARGET_PAGE_BITS 13 |
202 | bb7ec043 | pbrook | #define MMAP_SHIFT TARGET_PAGE_BITS
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203 | 81fdc5f8 | ths | |
204 | 81fdc5f8 | ths | #define CPUState CPUCRISState
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205 | 81fdc5f8 | ths | #define cpu_init cpu_cris_init
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206 | 81fdc5f8 | ths | #define cpu_exec cpu_cris_exec
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207 | 81fdc5f8 | ths | #define cpu_gen_code cpu_cris_gen_code
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208 | 81fdc5f8 | ths | #define cpu_signal_handler cpu_cris_signal_handler
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209 | 81fdc5f8 | ths | |
210 | b3c7724c | pbrook | #define CPU_SAVE_VERSION 1 |
211 | b3c7724c | pbrook | |
212 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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213 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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214 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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215 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
216 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
217 | 6ebbf390 | j_mayer | { |
218 | b41f7df0 | edgar_igl | return !!(env->pregs[PR_CCS] & U_FLAG);
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219 | 6ebbf390 | j_mayer | } |
220 | 6ebbf390 | j_mayer | |
221 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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222 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
223 | 6e68e076 | pbrook | { |
224 | f8ed7070 | pbrook | if (newsp)
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225 | 6e68e076 | pbrook | env->regs[14] = newsp;
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226 | 6e68e076 | pbrook | env->regs[10] = 0; |
227 | 6e68e076 | pbrook | } |
228 | 6e68e076 | pbrook | #endif
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229 | 6e68e076 | pbrook | |
230 | 9004627f | edgar_igl | /* Support function regs. */
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231 | 81fdc5f8 | ths | #define SFR_RW_GC_CFG 0][0 |
232 | b41f7df0 | edgar_igl | #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0 |
233 | b41f7df0 | edgar_igl | #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1 |
234 | b41f7df0 | edgar_igl | #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2 |
235 | b41f7df0 | edgar_igl | #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3 |
236 | b41f7df0 | edgar_igl | #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4 |
237 | b41f7df0 | edgar_igl | #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 |
238 | b41f7df0 | edgar_igl | #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 |
239 | 81fdc5f8 | ths | |
240 | 2e70f6ef | pbrook | #define CPU_PC_FROM_TB(env, tb) env->pc = tb->pc
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241 | 2e70f6ef | pbrook | |
242 | b41f7df0 | edgar_igl | #include "cpu-all.h" |
243 | 81fdc5f8 | ths | #endif |