Revision e1833e1f target-ppc/cpu.h
| b/target-ppc/cpu.h | ||
|---|---|---|
| 149 | 149 |
}; |
| 150 | 150 |
|
| 151 | 151 |
/*****************************************************************************/ |
| 152 |
/* Exception vectors definitions */ |
|
| 153 |
enum {
|
|
| 154 |
POWERPC_EXCP_NONE = -1, |
|
| 155 |
/* The 64 first entries are used by the PowerPC embedded specification */ |
|
| 156 |
POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
|
| 157 |
POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
|
| 158 |
POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
|
| 159 |
POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
|
| 160 |
POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
|
| 161 |
POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
|
| 162 |
POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
|
| 163 |
POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
|
| 164 |
POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
|
| 165 |
POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
|
| 166 |
POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
|
| 167 |
POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
|
| 168 |
POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
|
| 169 |
POWERPC_EXCP_DTLB = 13, /* Data TLB error */ |
|
| 170 |
POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */ |
|
| 171 |
POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
|
| 172 |
/* Vectors 16 to 31 are reserved */ |
|
| 173 |
#if defined(TARGET_PPCEMB) |
|
| 174 |
POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
|
| 175 |
POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
|
| 176 |
POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
|
| 177 |
POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
|
| 178 |
POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
|
| 179 |
POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
|
| 180 |
#endif /* defined(TARGET_PPCEMB) */ |
|
| 181 |
/* Vectors 38 to 63 are reserved */ |
|
| 182 |
/* Exceptions defined in the PowerPC server specification */ |
|
| 183 |
POWERPC_EXCP_RESET = 64, /* System reset exception */ |
|
| 184 |
#if defined(TARGET_PPC64) /* PowerPC 64 */ |
|
| 185 |
POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
|
| 186 |
POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
|
| 187 |
#endif /* defined(TARGET_PPC64) */ |
|
| 188 |
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
|
| 189 |
POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
|
| 190 |
#endif /* defined(TARGET_PPC64H) */ |
|
| 191 |
POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
|
| 192 |
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
|
| 193 |
POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
|
| 194 |
POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
|
| 195 |
POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
|
| 196 |
POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
|
| 197 |
#endif /* defined(TARGET_PPC64H) */ |
|
| 198 |
POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
|
| 199 |
/* 40x specific exceptions */ |
|
| 200 |
POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
|
| 201 |
/* 601 specific exceptions */ |
|
| 202 |
POWERPC_EXCP_IO = 75, /* IO error exception */ |
|
| 203 |
POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
|
| 204 |
/* 602 specific exceptions */ |
|
| 205 |
POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
|
| 206 |
/* 602/603 specific exceptions */ |
|
| 207 |
POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */ |
|
| 208 |
POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
|
| 209 |
POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
|
| 210 |
/* Exceptions available on most PowerPC */ |
|
| 211 |
POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
|
| 212 |
POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */ |
|
| 213 |
POWERPC_EXCP_SMI = 83, /* System management interrupt */ |
|
| 214 |
POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */ |
|
| 215 |
/* 7xx/74xx specific exceptions */ |
|
| 216 |
POWERPC_EXCP_THERM = 85, /* Thermal interrupt */ |
|
| 217 |
/* 74xx specific exceptions */ |
|
| 218 |
POWERPC_EXCP_VPUA = 86, /* Vector assist exception */ |
|
| 219 |
/* 970FX specific exceptions */ |
|
| 220 |
POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */ |
|
| 221 |
POWERPC_EXCP_MAINT = 88, /* Maintenance exception */ |
|
| 222 |
/* EOL */ |
|
| 223 |
POWERPC_EXCP_NB = 96, |
|
| 224 |
/* Qemu exceptions: used internally during code translation */ |
|
| 225 |
POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
|
| 226 |
POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
|
| 227 |
/* Qemu exceptions: special cases we want to stop translation */ |
|
| 228 |
POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
|
| 229 |
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
|
| 230 |
}; |
|
| 231 |
|
|
| 232 |
|
|
| 233 |
/* Exceptions error codes */ |
|
| 234 |
enum {
|
|
| 235 |
/* Exception subtypes for POWERPC_EXCP_ALIGN */ |
|
| 236 |
POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
|
| 237 |
POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
|
| 238 |
POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
|
| 239 |
POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
|
| 240 |
POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
|
| 241 |
POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
|
| 242 |
/* Exception subtypes for POWERPC_EXCP_PROGRAM */ |
|
| 243 |
/* FP exceptions */ |
|
| 244 |
POWERPC_EXCP_FP = 0x10, |
|
| 245 |
POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
|
| 246 |
POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
|
| 247 |
POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
|
| 248 |
POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
|
| 249 |
POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
|
| 250 |
POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
|
| 251 |
POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
|
| 252 |
POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
|
| 253 |
POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
|
| 254 |
POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
|
| 255 |
POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
|
| 256 |
POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
|
| 257 |
POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
|
| 258 |
/* Invalid instruction */ |
|
| 259 |
POWERPC_EXCP_INVAL = 0x20, |
|
| 260 |
POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
|
| 261 |
POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
|
| 262 |
POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
|
| 263 |
POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
|
| 264 |
/* Privileged instruction */ |
|
| 265 |
POWERPC_EXCP_PRIV = 0x30, |
|
| 266 |
POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
|
| 267 |
POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
|
| 268 |
/* Trap */ |
|
| 269 |
POWERPC_EXCP_TRAP = 0x40, |
|
| 270 |
}; |
|
| 271 |
|
|
| 272 |
/*****************************************************************************/ |
|
| 152 | 273 |
/* Input pins model */ |
| 153 | 274 |
enum {
|
| 154 | 275 |
PPC_FLAGS_INPUT_UNKNOWN = 0, |
| ... | ... | |
| 411 | 532 |
*/ |
| 412 | 533 |
uint32_t irq_input_state; |
| 413 | 534 |
void **irq_inputs; |
| 535 |
/* Exception vectors */ |
|
| 536 |
target_ulong excp_vectors[POWERPC_EXCP_NB]; |
|
| 537 |
target_ulong excp_prefix; |
|
| 538 |
target_ulong ivor_mask; |
|
| 539 |
target_ulong ivpr_mask; |
|
| 414 | 540 |
#endif |
| 415 | 541 |
|
| 416 | 542 |
/* Those resources are used only during code translation */ |
| ... | ... | |
| 634 | 760 |
#define SPR_BOOKE_IAC1 (0x138) |
| 635 | 761 |
#define SPR_HRMOR (0x139) |
| 636 | 762 |
#define SPR_BOOKE_IAC2 (0x139) |
| 637 |
#define SPR_HSSR0 (0x13A)
|
|
| 763 |
#define SPR_HSRR0 (0x13A)
|
|
| 638 | 764 |
#define SPR_BOOKE_IAC3 (0x13A) |
| 639 |
#define SPR_HSSR1 (0x13B)
|
|
| 765 |
#define SPR_HSRR1 (0x13B)
|
|
| 640 | 766 |
#define SPR_BOOKE_IAC4 (0x13B) |
| 641 | 767 |
#define SPR_LPCR (0x13C) |
| 642 | 768 |
#define SPR_BOOKE_DAC1 (0x13C) |
| ... | ... | |
| 948 | 1074 |
ACCESS_CACHE = 0x60, /* Cache manipulation */ |
| 949 | 1075 |
}; |
| 950 | 1076 |
|
| 951 |
/*****************************************************************************/ |
|
| 952 |
/* Exceptions */ |
|
| 953 |
#define EXCP_NONE -1 |
|
| 954 |
/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */ |
|
| 955 |
#define EXCP_RESET 0x0100 /* System reset */ |
|
| 956 |
#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */ |
|
| 957 |
#define EXCP_DSI 0x0300 /* Data storage exception */ |
|
| 958 |
#define EXCP_DSEG 0x0380 /* Data segment exception */ |
|
| 959 |
#define EXCP_ISI 0x0400 /* Instruction storage exception */ |
|
| 960 |
#define EXCP_ISEG 0x0480 /* Instruction segment exception */ |
|
| 961 |
#define EXCP_EXTERNAL 0x0500 /* External interruption */ |
|
| 962 |
#define EXCP_ALIGN 0x0600 /* Alignment exception */ |
|
| 963 |
#define EXCP_PROGRAM 0x0700 /* Program exception */ |
|
| 964 |
#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */ |
|
| 965 |
#define EXCP_DECR 0x0900 /* Decrementer exception */ |
|
| 966 |
#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */ |
|
| 967 |
#define EXCP_SYSCALL 0x0C00 /* System call */ |
|
| 968 |
#define EXCP_TRACE 0x0D00 /* Trace exception */ |
|
| 969 |
#define EXCP_PERF 0x0F00 /* Performance monitor exception */ |
|
| 970 |
/* Exceptions defined in PowerPC 32 bits programming environment manual */ |
|
| 971 |
#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */ |
|
| 972 |
/* Implementation specific exceptions */ |
|
| 973 |
/* 40x exceptions */ |
|
| 974 |
#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */ |
|
| 975 |
#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */ |
|
| 976 |
#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */ |
|
| 977 |
#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */ |
|
| 978 |
#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */ |
|
| 979 |
#define EXCP_40x_DEBUG 0x2000 /* Debug exception */ |
|
| 980 |
/* 405 specific exceptions */ |
|
| 981 |
#define EXCP_405_APU 0x0F20 /* APU unavailable exception */ |
|
| 982 |
/* 440 specific exceptions */ |
|
| 983 |
#define EXCP_440_CRIT 0x0100 /* Critical interrupt */ |
|
| 984 |
#define EXCP_440_SPEU 0x1600 /* SPE unavailable exception */ |
|
| 985 |
#define EXCP_440_SPED 0x1700 /* SPE floating-point data exception */ |
|
| 986 |
#define EXCP_440_SPER 0x1800 /* SPE floating-point round exception */ |
|
| 987 |
/* TLB assist exceptions (602/603) */ |
|
| 988 |
#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */ |
|
| 989 |
#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */ |
|
| 990 |
#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */ |
|
| 991 |
/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */ |
|
| 992 |
#define EXCP_IABR 0x1300 /* Instruction address breakpoint */ |
|
| 993 |
#define EXCP_SMI 0x1400 /* System management interrupt */ |
|
| 994 |
/* Altivec related exceptions */ |
|
| 995 |
#define EXCP_VPU 0x0F20 /* VPU unavailable exception */ |
|
| 996 |
/* 601 specific exceptions */ |
|
| 997 |
#define EXCP_601_IO 0x0A00 /* IO error exception */ |
|
| 998 |
#define EXCP_601_RUNM 0x2000 /* Run mode exception */ |
|
| 999 |
/* 602 specific exceptions */ |
|
| 1000 |
#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */ |
|
| 1001 |
#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */ |
|
| 1002 |
/* G2 specific exceptions */ |
|
| 1003 |
#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */ |
|
| 1004 |
/* MPC740/745/750 & IBM 750 specific exceptions */ |
|
| 1005 |
#define EXCP_THRM 0x1700 /* Thermal management interrupt */ |
|
| 1006 |
/* 74xx specific exceptions */ |
|
| 1007 |
#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */ |
|
| 1008 |
/* 970FX specific exceptions */ |
|
| 1009 |
#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */ |
|
| 1010 |
#define EXCP_970_MAINT 0x1600 /* Maintenance exception */ |
|
| 1011 |
#define EXCP_970_THRM 0x1800 /* Thermal exception */ |
|
| 1012 |
#define EXCP_970_VPUA 0x1700 /* VPU assist exception */ |
|
| 1013 |
/* SPE related exceptions */ |
|
| 1014 |
#define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */ |
|
| 1015 |
/* End of exception vectors area */ |
|
| 1016 |
#define EXCP_PPC_MAX 0x4000 |
|
| 1017 |
/* Qemu exceptions: special cases we want to stop translation */ |
|
| 1018 |
#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */ |
|
| 1019 |
/* may change privilege level */ |
|
| 1020 |
#define EXCP_BRANCH 0x11001 /* branch instruction */ |
|
| 1021 |
#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */ |
|
| 1022 |
|
|
| 1023 |
/* Error codes */ |
|
| 1024 |
enum {
|
|
| 1025 |
/* Exception subtypes for EXCP_ALIGN */ |
|
| 1026 |
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
|
| 1027 |
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
|
| 1028 |
EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
|
| 1029 |
EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
|
| 1030 |
EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
|
| 1031 |
EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
|
| 1032 |
/* Exception subtypes for EXCP_PROGRAM */ |
|
| 1033 |
/* FP exceptions */ |
|
| 1034 |
EXCP_FP = 0x10, |
|
| 1035 |
EXCP_FP_OX = 0x01, /* FP overflow */ |
|
| 1036 |
EXCP_FP_UX = 0x02, /* FP underflow */ |
|
| 1037 |
EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
|
| 1038 |
EXCP_FP_XX = 0x04, /* FP inexact */ |
|
| 1039 |
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
|
| 1040 |
EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
|
| 1041 |
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
|
| 1042 |
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
|
| 1043 |
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
|
| 1044 |
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
|
| 1045 |
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
|
| 1046 |
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
|
| 1047 |
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
|
| 1048 |
/* Invalid instruction */ |
|
| 1049 |
EXCP_INVAL = 0x20, |
|
| 1050 |
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
|
| 1051 |
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
|
| 1052 |
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
|
| 1053 |
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
|
| 1054 |
/* Privileged instruction */ |
|
| 1055 |
EXCP_PRIV = 0x30, |
|
| 1056 |
EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
|
| 1057 |
EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
|
| 1058 |
/* Trap */ |
|
| 1059 |
EXCP_TRAP = 0x40, |
|
| 1060 |
}; |
|
| 1061 |
|
|
| 1062 | 1077 |
/* Hardware interruption sources: |
| 1063 | 1078 |
* all those exception can be raised simulteaneously |
| 1064 | 1079 |
*/ |
| ... | ... | |
| 1130 | 1145 |
/* Hardware exceptions definitions */ |
| 1131 | 1146 |
enum {
|
| 1132 | 1147 |
/* External hardware exception sources */ |
| 1133 |
PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
|
| 1134 |
PPC_INTERRUPT_MCK = 1, /* Machine check exception */ |
|
| 1135 |
PPC_INTERRUPT_EXT = 2, /* External interrupt */ |
|
| 1136 |
PPC_INTERRUPT_SMI = 3, /* System management interrupt */ |
|
| 1137 |
PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */ |
|
| 1138 |
PPC_INTERRUPT_DEBUG = 5, /* External debug exception */ |
|
| 1139 |
PPC_INTERRUPT_THERM = 6, /* Thermal exception */ |
|
| 1148 |
PPC_INTERRUPT_RESET = 0, /* Reset exception */
|
|
| 1149 |
PPC_INTERRUPT_MCK = 1, /* Machine check exception */
|
|
| 1150 |
PPC_INTERRUPT_EXT = 2, /* External interrupt */
|
|
| 1151 |
PPC_INTERRUPT_SMI = 3, /* System management interrupt */
|
|
| 1152 |
PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
|
|
| 1153 |
PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
|
|
| 1154 |
PPC_INTERRUPT_THERM = 6, /* Thermal exception */
|
|
| 1140 | 1155 |
/* Internal hardware exception sources */ |
| 1141 |
PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
|
| 1142 |
PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ |
|
| 1143 |
PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ |
|
| 1144 |
PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ |
|
| 1145 |
PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ |
|
| 1156 |
PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
|
| 1157 |
PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ |
|
| 1158 |
PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ |
|
| 1159 |
PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ |
|
| 1160 |
PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ |
|
| 1161 |
PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt */ |
|
| 1162 |
PPC_INTERRUPT_DOORBELL = 13, /* Doorbell interrupt */ |
|
| 1163 |
PPC_INTERRUPT_PERFM = 14, /* Performance monitor interrupt */ |
|
| 1146 | 1164 |
}; |
| 1147 | 1165 |
|
| 1148 | 1166 |
/*****************************************************************************/ |
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