Revision e1833e1f target-ppc/op_mem.h
| b/target-ppc/op_mem.h | ||
|---|---|---|
| 296 | 296 |
if (likely(T1 != 0)) {
|
| 297 | 297 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) || |
| 298 | 298 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
|
| 299 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
|
| 299 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
|
| 300 |
POWERPC_EXCP_INVAL | |
|
| 301 |
POWERPC_EXCP_INVAL_LSWX); |
|
| 300 | 302 |
} else {
|
| 301 | 303 |
glue(do_lsw, MEMSUFFIX)(PARAM1); |
| 302 | 304 |
} |
| ... | ... | |
| 311 | 313 |
if (likely(T1 != 0)) {
|
| 312 | 314 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) || |
| 313 | 315 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
|
| 314 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
|
| 316 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
|
| 317 |
POWERPC_EXCP_INVAL | |
|
| 318 |
POWERPC_EXCP_INVAL_LSWX); |
|
| 315 | 319 |
} else {
|
| 316 | 320 |
glue(do_lsw_64, MEMSUFFIX)(PARAM1); |
| 317 | 321 |
} |
| ... | ... | |
| 326 | 330 |
if (likely(T1 != 0)) {
|
| 327 | 331 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) || |
| 328 | 332 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
|
| 329 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
|
| 333 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
|
| 334 |
POWERPC_EXCP_INVAL | |
|
| 335 |
POWERPC_EXCP_INVAL_LSWX); |
|
| 330 | 336 |
} else {
|
| 331 | 337 |
glue(do_lsw_le, MEMSUFFIX)(PARAM1); |
| 332 | 338 |
} |
| ... | ... | |
| 341 | 347 |
if (likely(T1 != 0)) {
|
| 342 | 348 |
if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) || |
| 343 | 349 |
(PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
|
| 344 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX); |
|
| 350 |
do_raise_exception_err(POWERPC_EXCP_PROGRAM, |
|
| 351 |
POWERPC_EXCP_INVAL | |
|
| 352 |
POWERPC_EXCP_INVAL_LSWX); |
|
| 345 | 353 |
} else {
|
| 346 | 354 |
glue(do_lsw_le_64, MEMSUFFIX)(PARAM1); |
| 347 | 355 |
} |
| ... | ... | |
| 514 | 522 |
void OPPROTO glue(op_lwarx, MEMSUFFIX) (void) |
| 515 | 523 |
{
|
| 516 | 524 |
if (unlikely(T0 & 0x03)) {
|
| 517 |
do_raise_exception(EXCP_ALIGN); |
|
| 525 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 518 | 526 |
} else {
|
| 519 | 527 |
T1 = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
| 520 | 528 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 526 | 534 |
void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void) |
| 527 | 535 |
{
|
| 528 | 536 |
if (unlikely(T0 & 0x03)) {
|
| 529 |
do_raise_exception(EXCP_ALIGN); |
|
| 537 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 530 | 538 |
} else {
|
| 531 | 539 |
T1 = glue(ldl, MEMSUFFIX)((uint64_t)T0); |
| 532 | 540 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 537 | 545 |
void OPPROTO glue(op_ldarx, MEMSUFFIX) (void) |
| 538 | 546 |
{
|
| 539 | 547 |
if (unlikely(T0 & 0x03)) {
|
| 540 |
do_raise_exception(EXCP_ALIGN); |
|
| 548 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 541 | 549 |
} else {
|
| 542 | 550 |
T1 = glue(ldq, MEMSUFFIX)((uint32_t)T0); |
| 543 | 551 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 548 | 556 |
void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void) |
| 549 | 557 |
{
|
| 550 | 558 |
if (unlikely(T0 & 0x03)) {
|
| 551 |
do_raise_exception(EXCP_ALIGN); |
|
| 559 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 552 | 560 |
} else {
|
| 553 | 561 |
T1 = glue(ldq, MEMSUFFIX)((uint64_t)T0); |
| 554 | 562 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 560 | 568 |
void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void) |
| 561 | 569 |
{
|
| 562 | 570 |
if (unlikely(T0 & 0x03)) {
|
| 563 |
do_raise_exception(EXCP_ALIGN); |
|
| 571 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 564 | 572 |
} else {
|
| 565 | 573 |
T1 = glue(ld32r, MEMSUFFIX)((uint32_t)T0); |
| 566 | 574 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 572 | 580 |
void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void) |
| 573 | 581 |
{
|
| 574 | 582 |
if (unlikely(T0 & 0x03)) {
|
| 575 |
do_raise_exception(EXCP_ALIGN); |
|
| 583 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 576 | 584 |
} else {
|
| 577 | 585 |
T1 = glue(ld32r, MEMSUFFIX)((uint64_t)T0); |
| 578 | 586 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 583 | 591 |
void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void) |
| 584 | 592 |
{
|
| 585 | 593 |
if (unlikely(T0 & 0x03)) {
|
| 586 |
do_raise_exception(EXCP_ALIGN); |
|
| 594 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 587 | 595 |
} else {
|
| 588 | 596 |
T1 = glue(ld64r, MEMSUFFIX)((uint32_t)T0); |
| 589 | 597 |
env->reserve = (uint32_t)T0; |
| ... | ... | |
| 594 | 602 |
void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void) |
| 595 | 603 |
{
|
| 596 | 604 |
if (unlikely(T0 & 0x03)) {
|
| 597 |
do_raise_exception(EXCP_ALIGN); |
|
| 605 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 598 | 606 |
} else {
|
| 599 | 607 |
T1 = glue(ld64r, MEMSUFFIX)((uint64_t)T0); |
| 600 | 608 |
env->reserve = (uint64_t)T0; |
| ... | ... | |
| 607 | 615 |
void OPPROTO glue(op_stwcx, MEMSUFFIX) (void) |
| 608 | 616 |
{
|
| 609 | 617 |
if (unlikely(T0 & 0x03)) {
|
| 610 |
do_raise_exception(EXCP_ALIGN); |
|
| 618 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 611 | 619 |
} else {
|
| 612 | 620 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 613 | 621 |
env->crf[0] = xer_so; |
| ... | ... | |
| 624 | 632 |
void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void) |
| 625 | 633 |
{
|
| 626 | 634 |
if (unlikely(T0 & 0x03)) {
|
| 627 |
do_raise_exception(EXCP_ALIGN); |
|
| 635 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 628 | 636 |
} else {
|
| 629 | 637 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 630 | 638 |
env->crf[0] = xer_so; |
| ... | ... | |
| 640 | 648 |
void OPPROTO glue(op_stdcx, MEMSUFFIX) (void) |
| 641 | 649 |
{
|
| 642 | 650 |
if (unlikely(T0 & 0x03)) {
|
| 643 |
do_raise_exception(EXCP_ALIGN); |
|
| 651 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 644 | 652 |
} else {
|
| 645 | 653 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 646 | 654 |
env->crf[0] = xer_so; |
| ... | ... | |
| 656 | 664 |
void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void) |
| 657 | 665 |
{
|
| 658 | 666 |
if (unlikely(T0 & 0x03)) {
|
| 659 |
do_raise_exception(EXCP_ALIGN); |
|
| 667 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 660 | 668 |
} else {
|
| 661 | 669 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 662 | 670 |
env->crf[0] = xer_so; |
| ... | ... | |
| 673 | 681 |
void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void) |
| 674 | 682 |
{
|
| 675 | 683 |
if (unlikely(T0 & 0x03)) {
|
| 676 |
do_raise_exception(EXCP_ALIGN); |
|
| 684 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 677 | 685 |
} else {
|
| 678 | 686 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 679 | 687 |
env->crf[0] = xer_so; |
| ... | ... | |
| 690 | 698 |
void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void) |
| 691 | 699 |
{
|
| 692 | 700 |
if (unlikely(T0 & 0x03)) {
|
| 693 |
do_raise_exception(EXCP_ALIGN); |
|
| 701 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 694 | 702 |
} else {
|
| 695 | 703 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 696 | 704 |
env->crf[0] = xer_so; |
| ... | ... | |
| 706 | 714 |
void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void) |
| 707 | 715 |
{
|
| 708 | 716 |
if (unlikely(T0 & 0x03)) {
|
| 709 |
do_raise_exception(EXCP_ALIGN); |
|
| 717 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 710 | 718 |
} else {
|
| 711 | 719 |
if (unlikely(env->reserve != (uint32_t)T0)) {
|
| 712 | 720 |
env->crf[0] = xer_so; |
| ... | ... | |
| 722 | 730 |
void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void) |
| 723 | 731 |
{
|
| 724 | 732 |
if (unlikely(T0 & 0x03)) {
|
| 725 |
do_raise_exception(EXCP_ALIGN); |
|
| 733 |
do_raise_exception(POWERPC_EXCP_ALIGN);
|
|
| 726 | 734 |
} else {
|
| 727 | 735 |
if (unlikely(env->reserve != (uint64_t)T0)) {
|
| 728 | 736 |
env->crf[0] = xer_so; |
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