Revision e1833e1f target-ppc/translate.c

b/target-ppc/translate.c
207 207
        gen_op_update_nip(nip);
208 208
}
209 209

  
210
#define RET_EXCP(ctx, excp, error)                                            \
210
#define GEN_EXCP(ctx, excp, error)                                            \
211 211
do {                                                                          \
212
    if ((ctx)->exception == EXCP_NONE) {                                      \
212
    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
213 213
        gen_update_nip(ctx, (ctx)->nip);                                      \
214 214
    }                                                                         \
215 215
    gen_op_raise_exception_err((excp), (error));                              \
216 216
    ctx->exception = (excp);                                                  \
217 217
} while (0)
218 218

  
219
#define RET_INVAL(ctx)                                                        \
220
RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
219
#define GEN_EXCP_INVAL(ctx)                                                   \
220
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
221
         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
221 222

  
222
#define RET_PRIVOPC(ctx)                                                      \
223
RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
223
#define GEN_EXCP_PRIVOPC(ctx)                                                 \
224
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
225
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
224 226

  
225
#define RET_PRIVREG(ctx)                                                      \
226
RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
227
#define GEN_EXCP_PRIVREG(ctx)                                                 \
228
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
229
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
230

  
231
#define GEN_EXCP_NO_FP(ctx)                                                   \
232
GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
233

  
234
#define GEN_EXCP_NO_AP(ctx)                                                   \
235
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
227 236

  
228 237
/* Stop translation */
229
static inline void RET_STOP (DisasContext *ctx)
238
static inline void GEN_STOP (DisasContext *ctx)
230 239
{
231 240
    gen_update_nip(ctx, ctx->nip);
232
    ctx->exception = EXCP_MTMSR;
241
    ctx->exception = POWERPC_EXCP_STOP;
233 242
}
234 243

  
235 244
/* No need to update nip here, as execution flow will change */
236
static inline void RET_CHG_FLOW (DisasContext *ctx)
245
static inline void GEN_SYNC (DisasContext *ctx)
237 246
{
238
    ctx->exception = EXCP_MTMSR;
247
    ctx->exception = POWERPC_EXCP_SYNC;
239 248
}
240 249

  
241 250
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
......
535 544
/* Invalid instruction */
536 545
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
537 546
{
538
    RET_INVAL(ctx);
547
    GEN_EXCP_INVAL(ctx);
539 548
}
540 549

  
541 550
static opc_handler_t invalid_handler = {
......
1550 1559
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
1551 1560
{                                                                             \
1552 1561
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1553
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1562
        GEN_EXCP_NO_FP(ctx);                                                  \
1554 1563
        return;                                                               \
1555 1564
    }                                                                         \
1556 1565
    gen_op_reset_scrfx();                                                     \
......
1574 1583
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
1575 1584
{                                                                             \
1576 1585
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1577
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1586
        GEN_EXCP_NO_FP(ctx);                                                  \
1578 1587
        return;                                                               \
1579 1588
    }                                                                         \
1580 1589
    gen_op_reset_scrfx();                                                     \
......
1596 1605
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
1597 1606
{                                                                             \
1598 1607
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1599
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1608
        GEN_EXCP_NO_FP(ctx);                                                  \
1600 1609
        return;                                                               \
1601 1610
    }                                                                         \
1602 1611
    gen_op_reset_scrfx();                                                     \
......
1618 1627
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
1619 1628
{                                                                             \
1620 1629
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1621
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1630
        GEN_EXCP_NO_FP(ctx);                                                  \
1622 1631
        return;                                                               \
1623 1632
    }                                                                         \
1624 1633
    gen_op_reset_scrfx();                                                     \
......
1633 1642
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
1634 1643
{                                                                             \
1635 1644
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1636
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
1645
        GEN_EXCP_NO_FP(ctx);                                                  \
1637 1646
        return;                                                               \
1638 1647
    }                                                                         \
1639 1648
    gen_op_reset_scrfx();                                                     \
......
1666 1675
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1667 1676
{
1668 1677
    if (unlikely(!ctx->fpu_enabled)) {
1669
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1678
        GEN_EXCP_NO_FP(ctx);
1670 1679
        return;
1671 1680
    }
1672 1681
    gen_op_reset_scrfx();
......
1680 1689
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1681 1690
{
1682 1691
    if (unlikely(!ctx->fpu_enabled)) {
1683
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1692
        GEN_EXCP_NO_FP(ctx);
1684 1693
        return;
1685 1694
    }
1686 1695
    gen_op_reset_scrfx();
......
1723 1732
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1724 1733
{
1725 1734
    if (unlikely(!ctx->fpu_enabled)) {
1726
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1735
        GEN_EXCP_NO_FP(ctx);
1727 1736
        return;
1728 1737
    }
1729 1738
    gen_op_reset_scrfx();
......
1737 1746
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1738 1747
{
1739 1748
    if (unlikely(!ctx->fpu_enabled)) {
1740
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1749
        GEN_EXCP_NO_FP(ctx);
1741 1750
        return;
1742 1751
    }
1743 1752
    gen_op_reset_scrfx();
......
1755 1764
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1756 1765
{
1757 1766
    if (unlikely(!ctx->fpu_enabled)) {
1758
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1767
        GEN_EXCP_NO_FP(ctx);
1759 1768
        return;
1760 1769
    }
1761 1770
    gen_op_reset_scrfx();
......
1775 1784
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1776 1785
{
1777 1786
    if (unlikely(!ctx->fpu_enabled)) {
1778
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1787
        GEN_EXCP_NO_FP(ctx);
1779 1788
        return;
1780 1789
    }
1781 1790
    gen_op_load_fpscr_T0(crfS(ctx->opcode));
......
1787 1796
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1788 1797
{
1789 1798
    if (unlikely(!ctx->fpu_enabled)) {
1790
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1799
        GEN_EXCP_NO_FP(ctx);
1791 1800
        return;
1792 1801
    }
1793 1802
    gen_op_load_fpscr();
......
1802 1811
    uint8_t crb;
1803 1812

  
1804 1813
    if (unlikely(!ctx->fpu_enabled)) {
1805
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1814
        GEN_EXCP_NO_FP(ctx);
1806 1815
        return;
1807 1816
    }
1808 1817
    crb = crbD(ctx->opcode) >> 2;
......
1819 1828
    uint8_t crb;
1820 1829

  
1821 1830
    if (unlikely(!ctx->fpu_enabled)) {
1822
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1831
        GEN_EXCP_NO_FP(ctx);
1823 1832
        return;
1824 1833
    }
1825 1834
    crb = crbD(ctx->opcode) >> 2;
......
1834 1843
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1835 1844
{
1836 1845
    if (unlikely(!ctx->fpu_enabled)) {
1837
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1846
        GEN_EXCP_NO_FP(ctx);
1838 1847
        return;
1839 1848
    }
1840 1849
    gen_op_load_fpr_FT0(rB(ctx->opcode));
......
1847 1856
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1848 1857
{
1849 1858
    if (unlikely(!ctx->fpu_enabled)) {
1850
        RET_EXCP(ctx, EXCP_NO_FP, 0);
1859
        GEN_EXCP_NO_FP(ctx);
1851 1860
        return;
1852 1861
    }
1853 1862
    gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
......
2002 2011
{                                                                             \
2003 2012
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2004 2013
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2005
        RET_INVAL(ctx);                                                       \
2014
        GEN_EXCP_INVAL(ctx);                                                  \
2006 2015
        return;                                                               \
2007 2016
    }                                                                         \
2008 2017
    if (type == PPC_64B)                                                      \
......
2019 2028
{                                                                             \
2020 2029
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2021 2030
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2022
        RET_INVAL(ctx);                                                       \
2031
        GEN_EXCP_INVAL(ctx);                                                  \
2023 2032
        return;                                                               \
2024 2033
    }                                                                         \
2025 2034
    gen_addr_reg_index(ctx);                                                  \
......
2067 2076
    if (Rc(ctx->opcode)) {
2068 2077
        if (unlikely(rA(ctx->opcode) == 0 ||
2069 2078
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2070
            RET_INVAL(ctx);
2079
            GEN_EXCP_INVAL(ctx);
2071 2080
            return;
2072 2081
        }
2073 2082
    }
......
2098 2107
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2099 2108
{                                                                             \
2100 2109
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2101
        RET_INVAL(ctx);                                                       \
2110
        GEN_EXCP_INVAL(ctx);                                                  \
2102 2111
        return;                                                               \
2103 2112
    }                                                                         \
2104 2113
    if (type == PPC_64B)                                                      \
......
2114 2123
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
2115 2124
{                                                                             \
2116 2125
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2117
        RET_INVAL(ctx);                                                       \
2126
        GEN_EXCP_INVAL(ctx);                                                  \
2118 2127
        return;                                                               \
2119 2128
    }                                                                         \
2120 2129
    gen_addr_reg_index(ctx);                                                  \
......
2152 2161
{
2153 2162
    if (Rc(ctx->opcode)) {
2154 2163
        if (unlikely(rA(ctx->opcode) == 0)) {
2155
            RET_INVAL(ctx);
2164
            GEN_EXCP_INVAL(ctx);
2156 2165
            return;
2157 2166
        }
2158 2167
    }
......
2367 2376
    if (unlikely(((start + nr) > 32  &&
2368 2377
                  start <= ra && (start + nr - 32) > ra) ||
2369 2378
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2370
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
2379
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2380
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2371 2381
        return;
2372 2382
    }
2373 2383
    /* NIP cannot be restored if the memory exception comes from an helper */
......
2426 2436
/* isync */
2427 2437
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FF0801, PPC_MEM)
2428 2438
{
2439
    GEN_STOP(ctx);
2429 2440
}
2430 2441

  
2431 2442
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
......
2574 2585
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                 \
2575 2586
{                                                                             \
2576 2587
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2577
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2588
        GEN_EXCP_NO_FP(ctx);                                                  \
2578 2589
        return;                                                               \
2579 2590
    }                                                                         \
2580 2591
    gen_addr_imm_index(ctx, 0);                                               \
......
2586 2597
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)              \
2587 2598
{                                                                             \
2588 2599
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2589
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2600
        GEN_EXCP_NO_FP(ctx);                                                  \
2590 2601
        return;                                                               \
2591 2602
    }                                                                         \
2592 2603
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2593
        RET_INVAL(ctx);                                                       \
2604
        GEN_EXCP_INVAL(ctx);                                                  \
2594 2605
        return;                                                               \
2595 2606
    }                                                                         \
2596 2607
    gen_addr_imm_index(ctx, 0);                                               \
......
2603 2614
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)             \
2604 2615
{                                                                             \
2605 2616
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2606
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2617
        GEN_EXCP_NO_FP(ctx);                                                  \
2607 2618
        return;                                                               \
2608 2619
    }                                                                         \
2609 2620
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2610
        RET_INVAL(ctx);                                                       \
2621
        GEN_EXCP_INVAL(ctx);                                                  \
2611 2622
        return;                                                               \
2612 2623
    }                                                                         \
2613 2624
    gen_addr_reg_index(ctx);                                                  \
......
2620 2631
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)             \
2621 2632
{                                                                             \
2622 2633
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2623
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2634
        GEN_EXCP_NO_FP(ctx);                                                  \
2624 2635
        return;                                                               \
2625 2636
    }                                                                         \
2626 2637
    gen_addr_reg_index(ctx);                                                  \
......
2645 2656
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)                \
2646 2657
{                                                                             \
2647 2658
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2648
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2659
        GEN_EXCP_NO_FP(ctx);                                                  \
2649 2660
        return;                                                               \
2650 2661
    }                                                                         \
2651 2662
    gen_addr_imm_index(ctx, 0);                                               \
......
2657 2668
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT)             \
2658 2669
{                                                                             \
2659 2670
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2660
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2671
        GEN_EXCP_NO_FP(ctx);                                                  \
2661 2672
        return;                                                               \
2662 2673
    }                                                                         \
2663 2674
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2664
        RET_INVAL(ctx);                                                       \
2675
        GEN_EXCP_INVAL(ctx);                                                  \
2665 2676
        return;                                                               \
2666 2677
    }                                                                         \
2667 2678
    gen_addr_imm_index(ctx, 0);                                               \
......
2674 2685
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_FLOAT)            \
2675 2686
{                                                                             \
2676 2687
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2677
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2688
        GEN_EXCP_NO_FP(ctx);                                                  \
2678 2689
        return;                                                               \
2679 2690
    }                                                                         \
2680 2691
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2681
        RET_INVAL(ctx);                                                       \
2692
        GEN_EXCP_INVAL(ctx);                                                  \
2682 2693
        return;                                                               \
2683 2694
    }                                                                         \
2684 2695
    gen_addr_reg_index(ctx);                                                  \
......
2691 2702
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_FLOAT)            \
2692 2703
{                                                                             \
2693 2704
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2694
        RET_EXCP(ctx, EXCP_NO_FP, 0);                                         \
2705
        GEN_EXCP_NO_FP(ctx);                                                  \
2695 2706
        return;                                                               \
2696 2707
    }                                                                         \
2697 2708
    gen_addr_reg_index(ctx);                                                  \
......
2716 2727
GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT_STFIWX)
2717 2728
{
2718 2729
    if (unlikely(!ctx->fpu_enabled)) {
2719
        RET_EXCP(ctx, EXCP_NO_FP, 0);
2730
        GEN_EXCP_NO_FP(ctx);
2720 2731
        return;
2721 2732
    }
2722 2733
    gen_addr_reg_index(ctx);
2723 2734
    /* XXX: TODO: memcpy low order 32 bits of FRP(rs) into memory */
2724
    RET_INVAL(ctx);
2735
    GEN_EXCP_INVAL(ctx);
2725 2736
}
2726 2737

  
2727 2738
/***                                Branch                                 ***/
......
2760 2771
    }
2761 2772
}
2762 2773

  
2774
static inline void gen_setlr (DisasContext *ctx, target_ulong nip)
2775
{
2776
#if defined(TARGET_PPC64)
2777
    if (ctx->sf_mode != 0 && (nip >> 32))
2778
        gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2779
    else
2780
#endif
2781
        gen_op_setlr(ctx->nip);
2782
}
2783

  
2763 2784
/* b ba bl bla */
2764 2785
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2765 2786
{
......
2776 2797
        target = ctx->nip + li - 4;
2777 2798
    else
2778 2799
        target = li;
2779
    if (LK(ctx->opcode)) {
2780 2800
#if defined(TARGET_PPC64)
2781
        if (ctx->sf_mode)
2782
            gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2783
        else
2801
    if (!ctx->sf_mode)
2802
        target = (uint32_t)target;
2784 2803
#endif
2785
            gen_op_setlr(ctx->nip);
2786
    }
2804
    if (LK(ctx->opcode))
2805
        gen_setlr(ctx, ctx->nip);
2787 2806
    gen_goto_tb(ctx, 0, target);
2788
    ctx->exception = EXCP_BRANCH;
2807
    ctx->exception = POWERPC_EXCP_BRANCH;
2789 2808
}
2790 2809

  
2791 2810
#define BCOND_IM  0
......
2810 2829
        } else {
2811 2830
            target = li;
2812 2831
        }
2832
#if defined(TARGET_PPC64)
2833
        if (!ctx->sf_mode)
2834
            target = (uint32_t)target;
2835
#endif
2813 2836
        break;
2814 2837
    case BCOND_CTR:
2815 2838
        gen_op_movl_T1_ctr();
......
2819 2842
        gen_op_movl_T1_lr();
2820 2843
        break;
2821 2844
    }
2822
    if (LK(ctx->opcode)) {
2823
#if defined(TARGET_PPC64)
2824
        if (ctx->sf_mode)
2825
            gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2826
        else
2827
#endif
2828
            gen_op_setlr(ctx->nip);
2829
    }
2845
    if (LK(ctx->opcode))
2846
        gen_setlr(ctx, ctx->nip);
2830 2847
    if (bo & 0x10) {
2831 2848
        /* No CR condition */
2832 2849
        switch (bo & 0x6) {
......
2934 2951
            gen_op_debug();
2935 2952
        gen_op_exit_tb();
2936 2953
    }
2937
    ctx->exception = EXCP_BRANCH;
2954
    ctx->exception = POWERPC_EXCP_BRANCH;
2938 2955
}
2939 2956

  
2940 2957
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
......
2995 3012
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
2996 3013
{
2997 3014
#if defined(CONFIG_USER_ONLY)
2998
    RET_PRIVOPC(ctx);
3015
    GEN_EXCP_PRIVOPC(ctx);
2999 3016
#else
3000 3017
    /* Restore CPU state */
3001 3018
    if (unlikely(!ctx->supervisor)) {
3002
        RET_PRIVOPC(ctx);
3019
        GEN_EXCP_PRIVOPC(ctx);
3003 3020
        return;
3004 3021
    }
3005 3022
    gen_op_rfi();
3006
    RET_CHG_FLOW(ctx);
3023
    GEN_SYNC(ctx);
3007 3024
#endif
3008 3025
}
3009 3026

  
......
3011 3028
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3012 3029
{
3013 3030
#if defined(CONFIG_USER_ONLY)
3014
    RET_PRIVOPC(ctx);
3031
    GEN_EXCP_PRIVOPC(ctx);
3015 3032
#else
3016 3033
    /* Restore CPU state */
3017 3034
    if (unlikely(!ctx->supervisor)) {
3018
        RET_PRIVOPC(ctx);
3035
        GEN_EXCP_PRIVOPC(ctx);
3019 3036
        return;
3020 3037
    }
3021 3038
    gen_op_rfid();
3022
    RET_CHG_FLOW(ctx);
3039
    GEN_SYNC(ctx);
3023 3040
#endif
3024 3041
}
3025 3042
#endif
3026 3043

  
3027 3044
/* sc */
3028
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
3045
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3029 3046
{
3047
    uint32_t lev;
3048

  
3049
    lev = (ctx->opcode >> 5) & 0x7F;
3030 3050
#if defined(CONFIG_USER_ONLY)
3031
    RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
3051
    GEN_EXCP(ctx, POWERPC_EXCP_SYSCALL_USER, lev);
3032 3052
#else
3033
    RET_EXCP(ctx, EXCP_SYSCALL, 0);
3053
    GEN_EXCP(ctx, POWERPC_EXCP_SYSCALL, lev);
3034 3054
#endif
3035 3055
}
3036 3056

  
......
3108 3128
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3109 3129
{
3110 3130
#if defined(CONFIG_USER_ONLY)
3111
    RET_PRIVREG(ctx);
3131
    GEN_EXCP_PRIVREG(ctx);
3112 3132
#else
3113 3133
    if (unlikely(!ctx->supervisor)) {
3114
        RET_PRIVREG(ctx);
3134
        GEN_EXCP_PRIVREG(ctx);
3115 3135
        return;
3116 3136
    }
3117 3137
    gen_op_load_msr();
......
3153 3173
                        sprn, sprn);
3154 3174
            }
3155 3175
            printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3156
            RET_PRIVREG(ctx);
3176
            GEN_EXCP_PRIVREG(ctx);
3157 3177
        }
3158 3178
    } else {
3159 3179
        /* Not defined */
......
3162 3182
                    sprn, sprn);
3163 3183
        }
3164 3184
        printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3165
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
3185
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3186
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3166 3187
    }
3167 3188
}
3168 3189

  
......
3199 3220
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001FF801, PPC_64B)
3200 3221
{
3201 3222
#if defined(CONFIG_USER_ONLY)
3202
    RET_PRIVREG(ctx);
3223
    GEN_EXCP_PRIVREG(ctx);
3203 3224
#else
3204 3225
    if (unlikely(!ctx->supervisor)) {
3205
        RET_PRIVREG(ctx);
3226
        GEN_EXCP_PRIVREG(ctx);
3206 3227
        return;
3207 3228
    }
3208 3229
    gen_update_nip(ctx, ctx->nip);
3209 3230
    gen_op_load_gpr_T0(rS(ctx->opcode));
3210 3231
    gen_op_store_msr();
3211 3232
    /* Must stop the translation as machine state (may have) changed */
3212
    RET_CHG_FLOW(ctx);
3233
    GEN_SYNC(ctx);
3213 3234
#endif
3214 3235
}
3215 3236
#endif
......
3217 3238
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3218 3239
{
3219 3240
#if defined(CONFIG_USER_ONLY)
3220
    RET_PRIVREG(ctx);
3241
    GEN_EXCP_PRIVREG(ctx);
3221 3242
#else
3222 3243
    if (unlikely(!ctx->supervisor)) {
3223
        RET_PRIVREG(ctx);
3244
        GEN_EXCP_PRIVREG(ctx);
3224 3245
        return;
3225 3246
    }
3226 3247
    gen_update_nip(ctx, ctx->nip);
......
3232 3253
#endif
3233 3254
        gen_op_store_msr();
3234 3255
    /* Must stop the translation as machine state (may have) changed */
3235
    RET_CHG_FLOW(ctx);
3256
    GEN_SYNC(ctx);
3236 3257
#endif
3237 3258
}
3238 3259

  
......
3259 3280
                        sprn, sprn);
3260 3281
            }
3261 3282
            printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3262
            RET_PRIVREG(ctx);
3283
            GEN_EXCP_PRIVREG(ctx);
3263 3284
        }
3264 3285
    } else {
3265 3286
        /* Not defined */
......
3268 3289
                    sprn, sprn);
3269 3290
        }
3270 3291
        printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
3271
        RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
3292
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3293
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3272 3294
    }
3273 3295
}
3274 3296

  
......
3288 3310
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3289 3311
{
3290 3312
#if defined(CONFIG_USER_ONLY)
3291
    RET_PRIVOPC(ctx);
3313
    GEN_EXCP_PRIVOPC(ctx);
3292 3314
#else
3293 3315
    if (unlikely(!ctx->supervisor)) {
3294
        RET_PRIVOPC(ctx);
3316
        GEN_EXCP_PRIVOPC(ctx);
3295 3317
        return;
3296 3318
    }
3297 3319
    gen_addr_reg_index(ctx);
......
3407 3429
};
3408 3430
#endif
3409 3431
#endif
3432

  
3410 3433
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3411 3434
{
3412
    /* NIP cannot be restored if the memory exception comes from an helper */
3413
    gen_update_nip(ctx, ctx->nip - 4);
3414 3435
    gen_addr_reg_index(ctx);
3415 3436
    op_icbi();
3416
    RET_STOP(ctx);
3417 3437
}
3418 3438

  
3419 3439
/* Optional: */
......
3428 3448
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3429 3449
{
3430 3450
#if defined(CONFIG_USER_ONLY)
3431
    RET_PRIVREG(ctx);
3451
    GEN_EXCP_PRIVREG(ctx);
3432 3452
#else
3433 3453
    if (unlikely(!ctx->supervisor)) {
3434
        RET_PRIVREG(ctx);
3454
        GEN_EXCP_PRIVREG(ctx);
3435 3455
        return;
3436 3456
    }
3437 3457
    gen_op_set_T1(SR(ctx->opcode));
......
3444 3464
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3445 3465
{
3446 3466
#if defined(CONFIG_USER_ONLY)
3447
    RET_PRIVREG(ctx);
3467
    GEN_EXCP_PRIVREG(ctx);
3448 3468
#else
3449 3469
    if (unlikely(!ctx->supervisor)) {
3450
        RET_PRIVREG(ctx);
3470
        GEN_EXCP_PRIVREG(ctx);
3451 3471
        return;
3452 3472
    }
3453 3473
    gen_op_load_gpr_T1(rB(ctx->opcode));
......
3461 3481
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3462 3482
{
3463 3483
#if defined(CONFIG_USER_ONLY)
3464
    RET_PRIVREG(ctx);
3484
    GEN_EXCP_PRIVREG(ctx);
3465 3485
#else
3466 3486
    if (unlikely(!ctx->supervisor)) {
3467
        RET_PRIVREG(ctx);
3487
        GEN_EXCP_PRIVREG(ctx);
3468 3488
        return;
3469 3489
    }
3470 3490
    gen_op_load_gpr_T0(rS(ctx->opcode));
3471 3491
    gen_op_set_T1(SR(ctx->opcode));
3472 3492
    gen_op_store_sr();
3473
    RET_STOP(ctx);
3474 3493
#endif
3475 3494
}
3476 3495

  
......
3478 3497
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3479 3498
{
3480 3499
#if defined(CONFIG_USER_ONLY)
3481
    RET_PRIVREG(ctx);
3500
    GEN_EXCP_PRIVREG(ctx);
3482 3501
#else
3483 3502
    if (unlikely(!ctx->supervisor)) {
3484
        RET_PRIVREG(ctx);
3503
        GEN_EXCP_PRIVREG(ctx);
3485 3504
        return;
3486 3505
    }
3487 3506
    gen_op_load_gpr_T0(rS(ctx->opcode));
3488 3507
    gen_op_load_gpr_T1(rB(ctx->opcode));
3489 3508
    gen_op_srli_T1(28);
3490 3509
    gen_op_store_sr();
3491
    RET_STOP(ctx);
3492 3510
#endif
3493 3511
}
3494 3512

  
......
3498 3516
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
3499 3517
{
3500 3518
#if defined(CONFIG_USER_ONLY)
3501
    RET_PRIVOPC(ctx);
3519
    GEN_EXCP_PRIVOPC(ctx);
3502 3520
#else
3503 3521
    if (unlikely(!ctx->supervisor)) {
3504 3522
        if (loglevel != 0)
3505 3523
            fprintf(logfile, "%s: ! supervisor\n", __func__);
3506
        RET_PRIVOPC(ctx);
3524
        GEN_EXCP_PRIVOPC(ctx);
3507 3525
        return;
3508 3526
    }
3509 3527
    gen_op_tlbia();
3510
    RET_STOP(ctx);
3511 3528
#endif
3512 3529
}
3513 3530

  
......
3515 3532
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
3516 3533
{
3517 3534
#if defined(CONFIG_USER_ONLY)
3518
    RET_PRIVOPC(ctx);
3535
    GEN_EXCP_PRIVOPC(ctx);
3519 3536
#else
3520 3537
    if (unlikely(!ctx->supervisor)) {
3521
        RET_PRIVOPC(ctx);
3538
        GEN_EXCP_PRIVOPC(ctx);
3522 3539
        return;
3523 3540
    }
3524 3541
    gen_op_load_gpr_T0(rB(ctx->opcode));
......
3528 3545
    else
3529 3546
#endif
3530 3547
        gen_op_tlbie();
3531
    RET_STOP(ctx);
3532 3548
#endif
3533 3549
}
3534 3550

  
......
3536 3552
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
3537 3553
{
3538 3554
#if defined(CONFIG_USER_ONLY)
3539
    RET_PRIVOPC(ctx);
3555
    GEN_EXCP_PRIVOPC(ctx);
3540 3556
#else
3541 3557
    if (unlikely(!ctx->supervisor)) {
3542
        RET_PRIVOPC(ctx);
3558
        GEN_EXCP_PRIVOPC(ctx);
3543 3559
        return;
3544 3560
    }
3545 3561
    /* This has no effect: it should ensure that all previous
3546 3562
     * tlbie have completed
3547 3563
     */
3548
    RET_STOP(ctx);
3564
    GEN_STOP(ctx);
3549 3565
#endif
3550 3566
}
3551 3567

  
......
3554 3570
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3555 3571
{
3556 3572
#if defined(CONFIG_USER_ONLY)
3557
    RET_PRIVOPC(ctx);
3573
    GEN_EXCP_PRIVOPC(ctx);
3558 3574
#else
3559 3575
    if (unlikely(!ctx->supervisor)) {
3560 3576
        if (loglevel != 0)
3561 3577
            fprintf(logfile, "%s: ! supervisor\n", __func__);
3562
        RET_PRIVOPC(ctx);
3578
        GEN_EXCP_PRIVOPC(ctx);
3563 3579
        return;
3564 3580
    }
3565 3581
    gen_op_slbia();
3566
    RET_STOP(ctx);
3567 3582
#endif
3568 3583
}
3569 3584

  
......
3571 3586
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3572 3587
{
3573 3588
#if defined(CONFIG_USER_ONLY)
3574
    RET_PRIVOPC(ctx);
3589
    GEN_EXCP_PRIVOPC(ctx);
3575 3590
#else
3576 3591
    if (unlikely(!ctx->supervisor)) {
3577
        RET_PRIVOPC(ctx);
3592
        GEN_EXCP_PRIVOPC(ctx);
3578 3593
        return;
3579 3594
    }
3580 3595
    gen_op_load_gpr_T0(rB(ctx->opcode));
3581 3596
    gen_op_slbie();
3582
    RET_STOP(ctx);
3583 3597
#endif
3584 3598
}
3585 3599
#endif
......
4073 4087
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4074 4088
{
4075 4089
    /* XXX: TODO */
4076
    RET_INVAL(ctx);
4090
    GEN_EXCP_INVAL(ctx);
4077 4091
}
4078 4092

  
4079 4093
/* esa */
4080 4094
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4081 4095
{
4082 4096
    /* XXX: TODO */
4083
    RET_INVAL(ctx);
4097
    GEN_EXCP_INVAL(ctx);
4084 4098
}
4085 4099

  
4086 4100
/* mfrom */
4087 4101
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4088 4102
{
4089 4103
#if defined(CONFIG_USER_ONLY)
4090
    RET_PRIVOPC(ctx);
4104
    GEN_EXCP_PRIVOPC(ctx);
4091 4105
#else
4092 4106
    if (unlikely(!ctx->supervisor)) {
4093
        RET_PRIVOPC(ctx);
4107
        GEN_EXCP_PRIVOPC(ctx);
4094 4108
        return;
4095 4109
    }
4096 4110
    gen_op_load_gpr_T0(rA(ctx->opcode));
......
4104 4118
GEN_HANDLER(tlbld, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4105 4119
{
4106 4120
#if defined(CONFIG_USER_ONLY)
4107
    RET_PRIVOPC(ctx);
4121
    GEN_EXCP_PRIVOPC(ctx);
4108 4122
#else
4109 4123
    if (unlikely(!ctx->supervisor)) {
4110
        RET_PRIVOPC(ctx);
4124
        GEN_EXCP_PRIVOPC(ctx);
4111 4125
        return;
4112 4126
    }
4113 4127
    gen_op_load_gpr_T0(rB(ctx->opcode));
4114 4128
    gen_op_6xx_tlbld();
4115
    RET_STOP(ctx);
4116 4129
#endif
4117 4130
}
4118 4131

  
......
4120 4133
GEN_HANDLER(tlbli, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4121 4134
{
4122 4135
#if defined(CONFIG_USER_ONLY)
4123
    RET_PRIVOPC(ctx);
4136
    GEN_EXCP_PRIVOPC(ctx);
4124 4137
#else
4125 4138
    if (unlikely(!ctx->supervisor)) {
4126
        RET_PRIVOPC(ctx);
4139
        GEN_EXCP_PRIVOPC(ctx);
4127 4140
        return;
4128 4141
    }
4129 4142
    gen_op_load_gpr_T0(rB(ctx->opcode));
4130 4143
    gen_op_6xx_tlbli();
4131
    RET_STOP(ctx);
4132 4144
#endif
4133 4145
}
4134 4146

  
......
4144 4156
{
4145 4157
    /* Cache line invalidate: privileged and treated as no-op */
4146 4158
#if defined(CONFIG_USER_ONLY)
4147
    RET_PRIVOPC(ctx);
4159
    GEN_EXCP_PRIVOPC(ctx);
4148 4160
#else
4149 4161
    if (unlikely(!ctx->supervisor)) {
4150
        RET_PRIVOPC(ctx);
4162
        GEN_EXCP_PRIVOPC(ctx);
4151 4163
        return;
4152 4164
    }
4153 4165
#endif
......
4162 4174
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4163 4175
{
4164 4176
#if defined(CONFIG_USER_ONLY)
4165
    RET_PRIVOPC(ctx);
4177
    GEN_EXCP_PRIVOPC(ctx);
4166 4178
#else
4167 4179
    if (unlikely(!ctx->supervisor)) {
4168
        RET_PRIVOPC(ctx);
4180
        GEN_EXCP_PRIVOPC(ctx);
4169 4181
        return;
4170 4182
    }
4171 4183
    int ra = rA(ctx->opcode);
......
4182 4194
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4183 4195
{
4184 4196
#if defined(CONFIG_USER_ONLY)
4185
    RET_PRIVOPC(ctx);
4197
    GEN_EXCP_PRIVOPC(ctx);
4186 4198
#else
4187 4199
    if (unlikely(!ctx->supervisor)) {
4188
        RET_PRIVOPC(ctx);
4200
        GEN_EXCP_PRIVOPC(ctx);
4189 4201
        return;
4190 4202
    }
4191 4203
    gen_addr_reg_index(ctx);
......
4197 4209
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4198 4210
{
4199 4211
#if defined(CONFIG_USER_ONLY)
4200
    RET_PRIVOPC(ctx);
4212
    GEN_EXCP_PRIVOPC(ctx);
4201 4213
#else
4202 4214
    if (unlikely(!ctx->supervisor)) {
4203
        RET_PRIVOPC(ctx);
4215
        GEN_EXCP_PRIVOPC(ctx);
4204 4216
        return;
4205 4217
    }
4206 4218
    gen_op_POWER_rfsvc();
4207
    RET_CHG_FLOW(ctx);
4219
    GEN_SYNC(ctx);
4208 4220
#endif
4209 4221
}
4210 4222

  
......
4347 4359
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
4348 4360
{
4349 4361
    /* XXX: TODO */
4350
    RET_INVAL(ctx);
4362
    GEN_EXCP_INVAL(ctx);
4351 4363
}
4352 4364

  
4353 4365
/* XXX: not implemented on 440 ? */
4354 4366
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
4355 4367
{
4356 4368
#if defined(CONFIG_USER_ONLY)
4357
    RET_PRIVOPC(ctx);
4369
    GEN_EXCP_PRIVOPC(ctx);
4358 4370
#else
4359 4371
    if (unlikely(!ctx->supervisor)) {
4360
        RET_PRIVOPC(ctx);
4372
        GEN_EXCP_PRIVOPC(ctx);
4361 4373
        return;
4362 4374
    }
4363 4375
    gen_addr_reg_index(ctx);
......
4368 4380
    else
4369 4381
#endif
4370 4382
        gen_op_tlbie();
4371
    RET_STOP(ctx);
4372 4383
#endif
4373 4384
}
4374 4385

  
......
4550 4561
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
4551 4562
{
4552 4563
#if defined(CONFIG_USER_ONLY)
4553
    RET_PRIVREG(ctx);
4564
    GEN_EXCP_PRIVREG(ctx);
4554 4565
#else
4555 4566
    uint32_t dcrn = SPR(ctx->opcode);
4556 4567

  
4557 4568
    if (unlikely(!ctx->supervisor)) {
4558
        RET_PRIVREG(ctx);
4569
        GEN_EXCP_PRIVREG(ctx);
4559 4570
        return;
4560 4571
    }
4561 4572
    gen_op_set_T0(dcrn);
......
4568 4579
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
4569 4580
{
4570 4581
#if defined(CONFIG_USER_ONLY)
4571
    RET_PRIVREG(ctx);
4582
    GEN_EXCP_PRIVREG(ctx);
4572 4583
#else
4573 4584
    uint32_t dcrn = SPR(ctx->opcode);
4574 4585

  
4575 4586
    if (unlikely(!ctx->supervisor)) {
4576
        RET_PRIVREG(ctx);
4587
        GEN_EXCP_PRIVREG(ctx);
4577 4588
        return;
4578 4589
    }
4579 4590
    gen_op_set_T0(dcrn);
......
4587 4598
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
4588 4599
{
4589 4600
#if defined(CONFIG_USER_ONLY)
4590
    RET_PRIVREG(ctx);
4601
    GEN_EXCP_PRIVREG(ctx);
4591 4602
#else
4592 4603
    if (unlikely(!ctx->supervisor)) {
4593
        RET_PRIVREG(ctx);
4604
        GEN_EXCP_PRIVREG(ctx);
4594 4605
        return;
4595 4606
    }
4596 4607
    gen_op_load_gpr_T0(rA(ctx->opcode));
......
4605 4616
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
4606 4617
{
4607 4618
#if defined(CONFIG_USER_ONLY)
4608
    RET_PRIVREG(ctx);
4619
    GEN_EXCP_PRIVREG(ctx);
4609 4620
#else
4610 4621
    if (unlikely(!ctx->supervisor)) {
4611
        RET_PRIVREG(ctx);
4622
        GEN_EXCP_PRIVREG(ctx);
4612 4623
        return;
4613 4624
    }
4614 4625
    gen_op_load_gpr_T0(rA(ctx->opcode));
......
4640 4651
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4641 4652
{
4642 4653
#if defined(CONFIG_USER_ONLY)
4643
    RET_PRIVOPC(ctx);
4654
    GEN_EXCP_PRIVOPC(ctx);
4644 4655
#else
4645 4656
    if (unlikely(!ctx->supervisor)) {
4646
        RET_PRIVOPC(ctx);
4657
        GEN_EXCP_PRIVOPC(ctx);
4647 4658
        return;
4648 4659
    }
4649 4660
    /* interpreted as no-op */
......
4654 4665
GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4655 4666
{
4656 4667
#if defined(CONFIG_USER_ONLY)
4657
    RET_PRIVOPC(ctx);
4668
    GEN_EXCP_PRIVOPC(ctx);
4658 4669
#else
4659 4670
    if (unlikely(!ctx->supervisor)) {
4660
        RET_PRIVOPC(ctx);
4671
        GEN_EXCP_PRIVOPC(ctx);
4661 4672
        return;
4662 4673
    }
4663 4674
    gen_addr_reg_index(ctx);
......
4679 4690
GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4680 4691
{
4681 4692
#if defined(CONFIG_USER_ONLY)
4682
    RET_PRIVOPC(ctx);
4693
    GEN_EXCP_PRIVOPC(ctx);
4683 4694
#else
4684 4695
    if (unlikely(!ctx->supervisor)) {
4685
        RET_PRIVOPC(ctx);
4696
        GEN_EXCP_PRIVOPC(ctx);
4686 4697
        return;
4687 4698
    }
4688 4699
    /* interpreted as no-op */
......
4693 4704
GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4694 4705
{
4695 4706
#if defined(CONFIG_USER_ONLY)
4696
    RET_PRIVOPC(ctx);
4707
    GEN_EXCP_PRIVOPC(ctx);
4697 4708
#else
4698 4709
    if (unlikely(!ctx->supervisor)) {
4699
        RET_PRIVOPC(ctx);
4710
        GEN_EXCP_PRIVOPC(ctx);
4700 4711
        return;
4701 4712
    }
4702 4713
    /* interpreted as no-op */
......
4707 4718
GEN_HANDLER(rfci_40x, 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
4708 4719
{
4709 4720
#if defined(CONFIG_USER_ONLY)
4710
    RET_PRIVOPC(ctx);
4721
    GEN_EXCP_PRIVOPC(ctx);
4711 4722
#else
4712 4723
    if (unlikely(!ctx->supervisor)) {
4713
        RET_PRIVOPC(ctx);
4724
        GEN_EXCP_PRIVOPC(ctx);
4714 4725
        return;
4715 4726
    }
4716 4727
    /* Restore CPU state */
4717 4728
    gen_op_40x_rfci();
4718
    RET_CHG_FLOW(ctx);
4729
    GEN_SYNC(ctx);
4719 4730
#endif
4720 4731
}
4721 4732

  
4722 4733
GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4723 4734
{
4724 4735
#if defined(CONFIG_USER_ONLY)
4725
    RET_PRIVOPC(ctx);
4736
    GEN_EXCP_PRIVOPC(ctx);
4726 4737
#else
4727 4738
    if (unlikely(!ctx->supervisor)) {
4728
        RET_PRIVOPC(ctx);
4739
        GEN_EXCP_PRIVOPC(ctx);
4729 4740
        return;
4730 4741
    }
4731 4742
    /* Restore CPU state */
4732 4743
    gen_op_rfci();
4733
    RET_CHG_FLOW(ctx);
4744
    GEN_SYNC(ctx);
4734 4745
#endif
4735 4746
}
4736 4747

  
......
4739 4750
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
4740 4751
{
4741 4752
#if defined(CONFIG_USER_ONLY)
4742
    RET_PRIVOPC(ctx);
4753
    GEN_EXCP_PRIVOPC(ctx);
4743 4754
#else
4744 4755
    if (unlikely(!ctx->supervisor)) {
4745
        RET_PRIVOPC(ctx);
4756
        GEN_EXCP_PRIVOPC(ctx);
4746 4757
        return;
4747 4758
    }
4748 4759
    /* Restore CPU state */
4749 4760
    gen_op_rfdi();
4750
    RET_CHG_FLOW(ctx);
4761
    GEN_SYNC(ctx);
4751 4762
#endif
4752 4763
}
4753 4764

  
......
4755 4766
GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
4756 4767
{
4757 4768
#if defined(CONFIG_USER_ONLY)
4758
    RET_PRIVOPC(ctx);
4769
    GEN_EXCP_PRIVOPC(ctx);
4759 4770
#else
4760 4771
    if (unlikely(!ctx->supervisor)) {
4761
        RET_PRIVOPC(ctx);
4772
        GEN_EXCP_PRIVOPC(ctx);
4762 4773
        return;
4763 4774
    }
4764 4775
    /* Restore CPU state */
4765 4776
    gen_op_rfmci();
4766
    RET_CHG_FLOW(ctx);
4777
    GEN_SYNC(ctx);
4767 4778
#endif
4768 4779
}
4769 4780

  
......
4772 4783
GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
4773 4784
{
4774 4785
#if defined(CONFIG_USER_ONLY)
4775
    RET_PRIVOPC(ctx);
4786
    GEN_EXCP_PRIVOPC(ctx);
4776 4787
#else
4777 4788
    if (unlikely(!ctx->supervisor)) {
4778
        RET_PRIVOPC(ctx);
4789
        GEN_EXCP_PRIVOPC(ctx);
4779 4790
        return;
4780 4791
    }
4781 4792
    switch (rB(ctx->opcode)) {
......
4790 4801
        gen_op_store_T0_gpr(rD(ctx->opcode));
4791 4802
        break;
4792 4803
    default:
4793
        RET_INVAL(ctx);
4804
        GEN_EXCP_INVAL(ctx);
4794 4805
        break;
4795 4806
    }
4796 4807
#endif
......
4800 4811
GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
4801 4812
{
4802 4813
#if defined(CONFIG_USER_ONLY)
4803
    RET_PRIVOPC(ctx);
4814
    GEN_EXCP_PRIVOPC(ctx);
4804 4815
#else
4805 4816
    if (unlikely(!ctx->supervisor)) {
4806
        RET_PRIVOPC(ctx);
4817
        GEN_EXCP_PRIVOPC(ctx);
4807 4818
        return;
4808 4819
    }
4809 4820
    gen_addr_reg_index(ctx);
......
4819 4830
GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
4820 4831
{
4821 4832
#if defined(CONFIG_USER_ONLY)
4822
    RET_PRIVOPC(ctx);
4833
    GEN_EXCP_PRIVOPC(ctx);
4823 4834
#else
4824 4835
    if (unlikely(!ctx->supervisor)) {
4825
        RET_PRIVOPC(ctx);
4836
        GEN_EXCP_PRIVOPC(ctx);
4826 4837
        return;
4827 4838
    }
4828 4839
    switch (rB(ctx->opcode)) {
......
4837 4848
        gen_op_4xx_tlbwe_lo();
4838 4849
        break;
4839 4850
    default:
4840
        RET_INVAL(ctx);
4851
        GEN_EXCP_INVAL(ctx);
4841 4852
        break;
4842 4853
    }
4843 4854
#endif
......
4848 4859
GEN_HANDLER(tlbre_440, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
4849 4860
{
4850 4861
#if defined(CONFIG_USER_ONLY)
4851
    RET_PRIVOPC(ctx);
4862
    GEN_EXCP_PRIVOPC(ctx);
4852 4863
#else
4853 4864
    if (unlikely(!ctx->supervisor)) {
4854
        RET_PRIVOPC(ctx);
4865
        GEN_EXCP_PRIVOPC(ctx);
4855 4866
        return;
4856 4867
    }
4857 4868
    switch (rB(ctx->opcode)) {
......
4863 4874
        gen_op_store_T0_gpr(rD(ctx->opcode));
4864 4875
        break;
4865 4876
    default:
4866
        RET_INVAL(ctx);
4877
        GEN_EXCP_INVAL(ctx);
4867 4878
        break;
4868 4879
    }
4869 4880
#endif
......
4873 4884
GEN_HANDLER(tlbsx_440, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
4874 4885
{
4875 4886
#if defined(CONFIG_USER_ONLY)
4876
    RET_PRIVOPC(ctx);
4887
    GEN_EXCP_PRIVOPC(ctx);
4877 4888
#else
4878 4889
    if (unlikely(!ctx->supervisor)) {
4879
        RET_PRIVOPC(ctx);
4890
        GEN_EXCP_PRIVOPC(ctx);
4880 4891
        return;
4881 4892
    }
4882 4893
    gen_addr_reg_index(ctx);
......
4892 4903
GEN_HANDLER(tlbwe_440, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
4893 4904
{
4894 4905
#if defined(CONFIG_USER_ONLY)
4895
    RET_PRIVOPC(ctx);
4906
    GEN_EXCP_PRIVOPC(ctx);
4896 4907
#else
4897 4908
    if (unlikely(!ctx->supervisor)) {
4898
        RET_PRIVOPC(ctx);
4909
        GEN_EXCP_PRIVOPC(ctx);
4899 4910
        return;
4900 4911
    }
4901 4912
    switch (rB(ctx->opcode)) {
......
4907 4918
        gen_op_440_tlbwe(rB(ctx->opcode));
4908 4919
        break;
4909 4920
    default:
4910
        RET_INVAL(ctx);
4921
        GEN_EXCP_INVAL(ctx);
4911 4922
        break;
4912 4923
    }
4913 4924
#endif
......
4917 4928
GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
4918 4929
{
4919 4930
#if defined(CONFIG_USER_ONLY)
4920
    RET_PRIVOPC(ctx);
4931
    GEN_EXCP_PRIVOPC(ctx);
4921 4932
#else
4922 4933
    if (unlikely(!ctx->supervisor)) {
4923
        RET_PRIVOPC(ctx);
4934
        GEN_EXCP_PRIVOPC(ctx);
4924 4935
        return;
4925 4936
    }
4926 4937
    gen_op_load_gpr_T0(rD(ctx->opcode));
4927 4938
    gen_op_wrte();
4928
    RET_EXCP(ctx, EXCP_MTMSR, 0);
4939
    GEN_STOP(ctx);
4929 4940
#endif
4930 4941
}
4931 4942

  
......
4933 4944
GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
4934 4945
{
4935 4946
#if defined(CONFIG_USER_ONLY)
4936
    RET_PRIVOPC(ctx);
4947
    GEN_EXCP_PRIVOPC(ctx);
4937 4948
#else
4938 4949
    if (unlikely(!ctx->supervisor)) {
4939
        RET_PRIVOPC(ctx);
4950
        GEN_EXCP_PRIVOPC(ctx);
4940 4951
        return;
4941 4952
    }
4942 4953
    gen_op_set_T0(ctx->opcode & 0x00010000);
4943 4954
    gen_op_wrte();
4944
    RET_EXCP(ctx, EXCP_MTMSR, 0);
4955
    GEN_STOP(ctx);
4945 4956
#endif
4946 4957
}
4947 4958

  
......
5009 5020
/* Handler for undefined SPE opcodes */
5010 5021
static inline void gen_speundef (DisasContext *ctx)
5011 5022
{
5012
    RET_INVAL(ctx);
5023
    GEN_EXCP_INVAL(ctx);
5013 5024
}
5014 5025

  
5015 5026
/* SPE load and stores */
......
5101 5112
static inline void gen_evl##name (DisasContext *ctx)                          \
5102 5113
{                                                                             \
5103 5114
    if (unlikely(!ctx->spe_enabled)) {                                        \
5104
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5115
        GEN_EXCP_NO_AP(ctx);                                                  \
5105 5116
        return;                                                               \
5106 5117
    }                                                                         \
5107 5118
    gen_addr_spe_imm_index(ctx, sh);                                          \
......
5113 5124
static inline void gen_evl##name##x (DisasContext *ctx)                       \
5114 5125
{                                                                             \
5115 5126
    if (unlikely(!ctx->spe_enabled)) {                                        \
5116
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5127
        GEN_EXCP_NO_AP(ctx);                                                  \
5117 5128
        return;                                                               \
5118 5129
    }                                                                         \
5119 5130
    gen_addr_reg_index(ctx);                                                  \
......
5130 5141
static inline void gen_evst##name (DisasContext *ctx)                         \
5131 5142
{                                                                             \
5132 5143
    if (unlikely(!ctx->spe_enabled)) {                                        \
5133
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5144
        GEN_EXCP_NO_AP(ctx);                                                  \
5134 5145
        return;                                                               \
5135 5146
    }                                                                         \
5136 5147
    gen_addr_spe_imm_index(ctx, sh);                                          \
......
5142 5153
static inline void gen_evst##name##x (DisasContext *ctx)                      \
5143 5154
{                                                                             \
5144 5155
    if (unlikely(!ctx->spe_enabled)) {                                        \
5145
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5156
        GEN_EXCP_NO_AP(ctx);                                                  \
5146 5157
        return;                                                               \
5147 5158
    }                                                                         \
5148 5159
    gen_addr_reg_index(ctx);                                                  \
......
5164 5175
static inline void gen_##name (DisasContext *ctx)                             \
5165 5176
{                                                                             \
5166 5177
    if (unlikely(!ctx->spe_enabled)) {                                        \
5167
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5178
        GEN_EXCP_NO_AP(ctx);                                                  \
5168 5179
        return;                                                               \
5169 5180
    }                                                                         \
5170 5181
    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
......
5177 5188
static inline void gen_##name (DisasContext *ctx)                             \
5178 5189
{                                                                             \
5179 5190
    if (unlikely(!ctx->spe_enabled)) {                                        \
5180
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5191
        GEN_EXCP_NO_AP(ctx);                                                  \
5181 5192
        return;                                                               \
5182 5193
    }                                                                         \
5183 5194
    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
......
5189 5200
static inline void gen_##name (DisasContext *ctx)                             \
5190 5201
{                                                                             \
5191 5202
    if (unlikely(!ctx->spe_enabled)) {                                        \
5192
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5203
        GEN_EXCP_NO_AP(ctx);                                                  \
5193 5204
        return;                                                               \
5194 5205
    }                                                                         \
5195 5206
    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
......
5239 5250
static inline void gen_##name##i (DisasContext *ctx)                          \
5240 5251
{                                                                             \
5241 5252
    if (unlikely(!ctx->spe_enabled)) {                                        \
5242
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5253
        GEN_EXCP_NO_AP(ctx);                                                  \
5243 5254
        return;                                                               \
5244 5255
    }                                                                         \
5245 5256
    gen_op_load_gpr64_T0(rB(ctx->opcode));                                    \
......
5252 5263
static inline void gen_##name##i (DisasContext *ctx)                          \
5253 5264
{                                                                             \
5254 5265
    if (unlikely(!ctx->spe_enabled)) {                                        \
5255
        RET_EXCP(ctx, EXCP_NO_SPE, 0);                                        \
5266
        GEN_EXCP_NO_AP(ctx);                                                  \
5256 5267
        return;                                                               \
5257 5268
    }                                                                         \
5258 5269
    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
......
5324 5335
static inline void gen_evsel (DisasContext *ctx)
5325 5336
{
5326 5337
    if (unlikely(!ctx->spe_enabled)) {
5327
        RET_EXCP(ctx, EXCP_NO_SPE, 0);
5338
        GEN_EXCP_NO_AP(ctx);
5328 5339
        return;
5329 5340
    }
5330 5341
    gen_op_load_crf_T0(ctx->opcode & 0x7);
......
5942 5953
    nb_gen_labels = 0;
5943 5954
    ctx.nip = pc_start;
5944 5955
    ctx.tb = tb;
5945
    ctx.exception = EXCP_NONE;
5956
    ctx.exception = POWERPC_EXCP_NONE;
5946 5957
    ctx.spr_cb = env->spr_cb;
5947 5958
#if defined(CONFIG_USER_ONLY)
5948 5959
    ctx.mem_idx = msr_le;
......
5969 5980
    msr_se = 1;
5970 5981
#endif
5971 5982
    /* Set env in case of segfault during code fetch */
5972
    while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
5983
    while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
5973 5984
        if (unlikely(env->nb_breakpoints > 0)) {
5974 5985
            for (j = 0; j < env->nb_breakpoints; j++) {
5975 5986
                if (env->breakpoints[j] == ctx.nip) {
......
6038 6049
            if (unlikely((ctx.opcode & handler->inval) != 0)) {
6039 6050
                if (loglevel != 0) {
6040 6051
                    fprintf(logfile, "invalid bits: %08x for opcode: "
6041
                            "%02x -%02x - %02x (%08x) 0x" ADDRX "\n",
6052
                            "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6042 6053
                            ctx.opcode & handler->inval, opc1(ctx.opcode),
6043 6054
                            opc2(ctx.opcode), opc3(ctx.opcode),
6044 6055
                            ctx.opcode, ctx.nip - 4);
6045 6056
                } else {
6046 6057
                    printf("invalid bits: %08x for opcode: "
6047
                           "%02x -%02x - %02x (%08x) 0x" ADDRX "\n",
6058
                           "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6048 6059
                           ctx.opcode & handler->inval, opc1(ctx.opcode),
6049 6060
                           opc2(ctx.opcode), opc3(ctx.opcode),
6050 6061
                           ctx.opcode, ctx.nip - 4);
6051 6062
                }
6052
                RET_INVAL(ctxp);
6063
                GEN_EXCP_INVAL(ctxp);
6053 6064
                break;
6054 6065
            }
6055 6066
        }
......
6059 6070
#endif
6060 6071
        /* Check trace mode exceptions */
6061 6072
#if 0 // XXX: buggy on embedded PowerPC
6062
        if (unlikely((msr_be && ctx.exception == EXCP_BRANCH) ||
6073
        if (unlikely((msr_be && ctx.exception == POWERPC_EXCP_BRANCH) ||
6063 6074
                     /* Check in single step trace mode
6064 6075
                      * we need to stop except if:
6065 6076
                      * - rfi, trap or syscall
......
6068 6079
                     (msr_se && (ctx.nip < 0x100 ||
6069 6080
                                 ctx.nip > 0xF00 ||
6070 6081
                                 (ctx.nip & 0xFC) != 0x04) &&
6071
                      ctx.exception != EXCP_SYSCALL &&
6072
                      ctx.exception != EXCP_SYSCALL_USER &&
6073
                      ctx.exception != EXCP_TRAP))) {
6074
            RET_EXCP(ctxp, EXCP_TRACE, 0);
6082
#if defined(CONFIG_USER_ONLY)
6083
                      ctx.exception != POWERPC_EXCP_SYSCALL_USER &&
6084
#else
6085
                      ctx.exception != POWERPC_EXCP_SYSCALL &&
6086
#endif
6087
                      ctx.exception != POWERPC_EXCP_TRAP))) {
6088
            GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6075 6089
        }
6076 6090
#endif
6077 6091
        /* if we reach a page boundary or are single stepping, stop
......
6085 6099
        break;
6086 6100
#endif
6087 6101
    }
6088
    if (ctx.exception == EXCP_NONE) {
6102
    if (ctx.exception == POWERPC_EXCP_NONE) {
6089 6103
        gen_goto_tb(&ctx, 0, ctx.nip);
6090
    } else if (ctx.exception != EXCP_BRANCH) {
6104
    } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6091 6105
        gen_op_reset_T0();
6092 6106
        /* Generate the return instruction */
6093 6107
        gen_op_exit_tb();

Also available in: Unified diff