Statistics
| Branch: | Revision:

root / target-ppc / translate_init.c @ e1833e1f

History | View | Annotate | Download (234.4 kB)

1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20

    
21
/* A lot of PowerPC definition have been included here.
22
 * Most of them are not usable for now but have been kept
23
 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
#include "dis-asm.h"
27

    
28
//#define PPC_DUMP_CPU
29
//#define PPC_DEBUG_SPR
30
//#define PPC_DEBUG_IRQ
31

    
32
struct ppc_def_t {
33
    const unsigned char *name;
34
    uint32_t pvr;
35
    uint32_t pvr_mask;
36
    uint64_t insns_flags;
37
    uint64_t msr_mask;
38
    uint8_t mmu_model;
39
    uint8_t excp_model;
40
    uint8_t bus_model;
41
    uint8_t pad;
42
    int bfd_mach;
43
    void (*init_proc)(CPUPPCState *env);
44
};
45

    
46
/* For user-mode emulation, we don't emulate any IRQ controller */
47
#if defined(CONFIG_USER_ONLY)
48
#define PPC_IRQ_INIT_FN(name)                                                 \
49
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
50
{                                                                             \
51
}
52
#else
53
#define PPC_IRQ_INIT_FN(name)                                                 \
54
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
55
#endif
56

    
57
PPC_IRQ_INIT_FN(401);
58
PPC_IRQ_INIT_FN(405);
59
PPC_IRQ_INIT_FN(6xx);
60
PPC_IRQ_INIT_FN(970);
61

    
62
/* Generic callbacks:
63
 * do nothing but store/retrieve spr value
64
 */
65
#ifdef PPC_DUMP_SPR_ACCESSES
66
static void spr_read_generic (void *opaque, int sprn)
67
{
68
    gen_op_load_dump_spr(sprn);
69
}
70

    
71
static void spr_write_generic (void *opaque, int sprn)
72
{
73
    gen_op_store_dump_spr(sprn);
74
}
75
#else
76
static void spr_read_generic (void *opaque, int sprn)
77
{
78
    gen_op_load_spr(sprn);
79
}
80

    
81
static void spr_write_generic (void *opaque, int sprn)
82
{
83
    gen_op_store_spr(sprn);
84
}
85
#endif
86

    
87
#if !defined(CONFIG_USER_ONLY)
88
static void spr_write_clear (void *opaque, int sprn)
89
{
90
    gen_op_mask_spr(sprn);
91
}
92
#endif
93

    
94
/* SPR common to all PowerPC */
95
/* XER */
96
static void spr_read_xer (void *opaque, int sprn)
97
{
98
    gen_op_load_xer();
99
}
100

    
101
static void spr_write_xer (void *opaque, int sprn)
102
{
103
    gen_op_store_xer();
104
}
105

    
106
/* LR */
107
static void spr_read_lr (void *opaque, int sprn)
108
{
109
    gen_op_load_lr();
110
}
111

    
112
static void spr_write_lr (void *opaque, int sprn)
113
{
114
    gen_op_store_lr();
115
}
116

    
117
/* CTR */
118
static void spr_read_ctr (void *opaque, int sprn)
119
{
120
    gen_op_load_ctr();
121
}
122

    
123
static void spr_write_ctr (void *opaque, int sprn)
124
{
125
    gen_op_store_ctr();
126
}
127

    
128
/* User read access to SPR */
129
/* USPRx */
130
/* UMMCRx */
131
/* UPMCx */
132
/* USIA */
133
/* UDECR */
134
static void spr_read_ureg (void *opaque, int sprn)
135
{
136
    gen_op_load_spr(sprn + 0x10);
137
}
138

    
139
/* SPR common to all non-embedded PowerPC */
140
/* DECR */
141
#if !defined(CONFIG_USER_ONLY)
142
static void spr_read_decr (void *opaque, int sprn)
143
{
144
    gen_op_load_decr();
145
}
146

    
147
static void spr_write_decr (void *opaque, int sprn)
148
{
149
    gen_op_store_decr();
150
}
151
#endif
152

    
153
/* SPR common to all non-embedded PowerPC, except 601 */
154
/* Time base */
155
static void spr_read_tbl (void *opaque, int sprn)
156
{
157
    gen_op_load_tbl();
158
}
159

    
160
static void spr_read_tbu (void *opaque, int sprn)
161
{
162
    gen_op_load_tbu();
163
}
164

    
165
#if !defined(CONFIG_USER_ONLY)
166
static void spr_write_tbl (void *opaque, int sprn)
167
{
168
    gen_op_store_tbl();
169
}
170

    
171
static void spr_write_tbu (void *opaque, int sprn)
172
{
173
    gen_op_store_tbu();
174
}
175
#endif
176

    
177
#if !defined(CONFIG_USER_ONLY)
178
/* IBAT0U...IBAT0U */
179
/* IBAT0L...IBAT7L */
180
static void spr_read_ibat (void *opaque, int sprn)
181
{
182
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
183
}
184

    
185
static void spr_read_ibat_h (void *opaque, int sprn)
186
{
187
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
188
}
189

    
190
static void spr_write_ibatu (void *opaque, int sprn)
191
{
192
    DisasContext *ctx = opaque;
193

    
194
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
195
    GEN_STOP(ctx);
196
}
197

    
198
static void spr_write_ibatu_h (void *opaque, int sprn)
199
{
200
    DisasContext *ctx = opaque;
201

    
202
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
203
    GEN_STOP(ctx);
204
}
205

    
206
static void spr_write_ibatl (void *opaque, int sprn)
207
{
208
    DisasContext *ctx = opaque;
209

    
210
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
211
    GEN_STOP(ctx);
212
}
213

    
214
static void spr_write_ibatl_h (void *opaque, int sprn)
215
{
216
    DisasContext *ctx = opaque;
217

    
218
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
219
    GEN_STOP(ctx);
220
}
221

    
222
/* DBAT0U...DBAT7U */
223
/* DBAT0L...DBAT7L */
224
static void spr_read_dbat (void *opaque, int sprn)
225
{
226
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
227
}
228

    
229
static void spr_read_dbat_h (void *opaque, int sprn)
230
{
231
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
232
}
233

    
234
static void spr_write_dbatu (void *opaque, int sprn)
235
{
236
    DisasContext *ctx = opaque;
237

    
238
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
239
    GEN_STOP(ctx);
240
}
241

    
242
static void spr_write_dbatu_h (void *opaque, int sprn)
243
{
244
    DisasContext *ctx = opaque;
245

    
246
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
247
    GEN_STOP(ctx);
248
}
249

    
250
static void spr_write_dbatl (void *opaque, int sprn)
251
{
252
    DisasContext *ctx = opaque;
253

    
254
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
255
    GEN_STOP(ctx);
256
}
257

    
258
static void spr_write_dbatl_h (void *opaque, int sprn)
259
{
260
    DisasContext *ctx = opaque;
261

    
262
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
263
    GEN_STOP(ctx);
264
}
265

    
266
/* SDR1 */
267
static void spr_read_sdr1 (void *opaque, int sprn)
268
{
269
    gen_op_load_sdr1();
270
}
271

    
272
static void spr_write_sdr1 (void *opaque, int sprn)
273
{
274
    DisasContext *ctx = opaque;
275

    
276
    gen_op_store_sdr1();
277
    GEN_STOP(ctx);
278
}
279

    
280
/* 64 bits PowerPC specific SPRs */
281
/* ASR */
282
/* Currently unused */
283
#if 0 && defined(TARGET_PPC64)
284
static void spr_read_asr (void *opaque, int sprn)
285
{
286
    gen_op_load_asr();
287
}
288

289
static void spr_write_asr (void *opaque, int sprn)
290
{
291
    DisasContext *ctx = opaque;
292

293
    gen_op_store_asr();
294
    GEN_STOP(ctx);
295
}
296
#endif
297
#endif
298

    
299
/* PowerPC 601 specific registers */
300
/* RTC */
301
static void spr_read_601_rtcl (void *opaque, int sprn)
302
{
303
    gen_op_load_601_rtcl();
304
}
305

    
306
static void spr_read_601_rtcu (void *opaque, int sprn)
307
{
308
    gen_op_load_601_rtcu();
309
}
310

    
311
#if !defined(CONFIG_USER_ONLY)
312
static void spr_write_601_rtcu (void *opaque, int sprn)
313
{
314
    gen_op_store_601_rtcu();
315
}
316

    
317
static void spr_write_601_rtcl (void *opaque, int sprn)
318
{
319
    gen_op_store_601_rtcl();
320
}
321
#endif
322

    
323
/* Unified bats */
324
#if !defined(CONFIG_USER_ONLY)
325
static void spr_read_601_ubat (void *opaque, int sprn)
326
{
327
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
328
}
329

    
330
static void spr_write_601_ubatu (void *opaque, int sprn)
331
{
332
    DisasContext *ctx = opaque;
333

    
334
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
335
    GEN_STOP(ctx);
336
}
337

    
338
static void spr_write_601_ubatl (void *opaque, int sprn)
339
{
340
    DisasContext *ctx = opaque;
341

    
342
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
343
    GEN_STOP(ctx);
344
}
345
#endif
346

    
347
/* PowerPC 40x specific registers */
348
#if !defined(CONFIG_USER_ONLY)
349
static void spr_read_40x_pit (void *opaque, int sprn)
350
{
351
    gen_op_load_40x_pit();
352
}
353

    
354
static void spr_write_40x_pit (void *opaque, int sprn)
355
{
356
    gen_op_store_40x_pit();
357
}
358

    
359
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
360
{
361
    DisasContext *ctx = opaque;
362

    
363
    gen_op_store_40x_dbcr0();
364
    /* We must stop translation as we may have rebooted */
365
    GEN_STOP(ctx);
366
}
367

    
368
static void spr_write_40x_sler (void *opaque, int sprn)
369
{
370
    DisasContext *ctx = opaque;
371

    
372
    gen_op_store_40x_sler();
373
    /* We must stop the translation as we may have changed
374
     * some regions endianness
375
     */
376
    GEN_STOP(ctx);
377
}
378

    
379
static void spr_write_booke_tcr (void *opaque, int sprn)
380
{
381
    gen_op_store_booke_tcr();
382
}
383

    
384
static void spr_write_booke_tsr (void *opaque, int sprn)
385
{
386
    gen_op_store_booke_tsr();
387
}
388
#endif
389

    
390
/* PowerPC 403 specific registers */
391
/* PBL1 / PBU1 / PBL2 / PBU2 */
392
#if !defined(CONFIG_USER_ONLY)
393
static void spr_read_403_pbr (void *opaque, int sprn)
394
{
395
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
396
}
397

    
398
static void spr_write_403_pbr (void *opaque, int sprn)
399
{
400
    DisasContext *ctx = opaque;
401

    
402
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
403
    GEN_STOP(ctx);
404
}
405

    
406
static void spr_write_pir (void *opaque, int sprn)
407
{
408
    gen_op_store_pir();
409
}
410
#endif
411

    
412
#if defined(CONFIG_USER_ONLY)
413
#define spr_register(env, num, name, uea_read, uea_write,                     \
414
                     oea_read, oea_write, initial_value)                      \
415
do {                                                                          \
416
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
417
} while (0)
418
static inline void _spr_register (CPUPPCState *env, int num,
419
                                  const unsigned char *name,
420
                                  void (*uea_read)(void *opaque, int sprn),
421
                                  void (*uea_write)(void *opaque, int sprn),
422
                                  target_ulong initial_value)
423
#else
424
static inline void spr_register (CPUPPCState *env, int num,
425
                                 const unsigned char *name,
426
                                 void (*uea_read)(void *opaque, int sprn),
427
                                 void (*uea_write)(void *opaque, int sprn),
428
                                 void (*oea_read)(void *opaque, int sprn),
429
                                 void (*oea_write)(void *opaque, int sprn),
430
                                 target_ulong initial_value)
431
#endif
432
{
433
    ppc_spr_t *spr;
434

    
435
    spr = &env->spr_cb[num];
436
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
437
#if !defined(CONFIG_USER_ONLY)
438
        spr->oea_read != NULL || spr->oea_write != NULL ||
439
#endif
440
        spr->uea_read != NULL || spr->uea_write != NULL) {
441
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
442
        exit(1);
443
    }
444
#if defined(PPC_DEBUG_SPR)
445
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
446
           initial_value);
447
#endif
448
    spr->name = name;
449
    spr->uea_read = uea_read;
450
    spr->uea_write = uea_write;
451
#if !defined(CONFIG_USER_ONLY)
452
    spr->oea_read = oea_read;
453
    spr->oea_write = oea_write;
454
#endif
455
    env->spr[num] = initial_value;
456
}
457

    
458
/* Generic PowerPC SPRs */
459
static void gen_spr_generic (CPUPPCState *env)
460
{
461
    /* Integer processing */
462
    spr_register(env, SPR_XER, "XER",
463
                 &spr_read_xer, &spr_write_xer,
464
                 &spr_read_xer, &spr_write_xer,
465
                 0x00000000);
466
    /* Branch contol */
467
    spr_register(env, SPR_LR, "LR",
468
                 &spr_read_lr, &spr_write_lr,
469
                 &spr_read_lr, &spr_write_lr,
470
                 0x00000000);
471
    spr_register(env, SPR_CTR, "CTR",
472
                 &spr_read_ctr, &spr_write_ctr,
473
                 &spr_read_ctr, &spr_write_ctr,
474
                 0x00000000);
475
    /* Interrupt processing */
476
    spr_register(env, SPR_SRR0, "SRR0",
477
                 SPR_NOACCESS, SPR_NOACCESS,
478
                 &spr_read_generic, &spr_write_generic,
479
                 0x00000000);
480
    spr_register(env, SPR_SRR1, "SRR1",
481
                 SPR_NOACCESS, SPR_NOACCESS,
482
                 &spr_read_generic, &spr_write_generic,
483
                 0x00000000);
484
    /* Processor control */
485
    spr_register(env, SPR_SPRG0, "SPRG0",
486
                 SPR_NOACCESS, SPR_NOACCESS,
487
                 &spr_read_generic, &spr_write_generic,
488
                 0x00000000);
489
    spr_register(env, SPR_SPRG1, "SPRG1",
490
                 SPR_NOACCESS, SPR_NOACCESS,
491
                 &spr_read_generic, &spr_write_generic,
492
                 0x00000000);
493
    spr_register(env, SPR_SPRG2, "SPRG2",
494
                 SPR_NOACCESS, SPR_NOACCESS,
495
                 &spr_read_generic, &spr_write_generic,
496
                 0x00000000);
497
    spr_register(env, SPR_SPRG3, "SPRG3",
498
                 SPR_NOACCESS, SPR_NOACCESS,
499
                 &spr_read_generic, &spr_write_generic,
500
                 0x00000000);
501
}
502

    
503
/* SPR common to all non-embedded PowerPC, including 601 */
504
static void gen_spr_ne_601 (CPUPPCState *env)
505
{
506
    /* Exception processing */
507
    spr_register(env, SPR_DSISR, "DSISR",
508
                 SPR_NOACCESS, SPR_NOACCESS,
509
                 &spr_read_generic, &spr_write_generic,
510
                 0x00000000);
511
    spr_register(env, SPR_DAR, "DAR",
512
                 SPR_NOACCESS, SPR_NOACCESS,
513
                 &spr_read_generic, &spr_write_generic,
514
                 0x00000000);
515
    /* Timer */
516
    spr_register(env, SPR_DECR, "DECR",
517
                 SPR_NOACCESS, SPR_NOACCESS,
518
                 &spr_read_decr, &spr_write_decr,
519
                 0x00000000);
520
    /* Memory management */
521
    spr_register(env, SPR_SDR1, "SDR1",
522
                 SPR_NOACCESS, SPR_NOACCESS,
523
                 &spr_read_sdr1, &spr_write_sdr1,
524
                 0x00000000);
525
}
526

    
527
/* BATs 0-3 */
528
static void gen_low_BATs (CPUPPCState *env)
529
{
530
    spr_register(env, SPR_IBAT0U, "IBAT0U",
531
                 SPR_NOACCESS, SPR_NOACCESS,
532
                 &spr_read_ibat, &spr_write_ibatu,
533
                 0x00000000);
534
    spr_register(env, SPR_IBAT0L, "IBAT0L",
535
                 SPR_NOACCESS, SPR_NOACCESS,
536
                 &spr_read_ibat, &spr_write_ibatl,
537
                 0x00000000);
538
    spr_register(env, SPR_IBAT1U, "IBAT1U",
539
                 SPR_NOACCESS, SPR_NOACCESS,
540
                 &spr_read_ibat, &spr_write_ibatu,
541
                 0x00000000);
542
    spr_register(env, SPR_IBAT1L, "IBAT1L",
543
                 SPR_NOACCESS, SPR_NOACCESS,
544
                 &spr_read_ibat, &spr_write_ibatl,
545
                 0x00000000);
546
    spr_register(env, SPR_IBAT2U, "IBAT2U",
547
                 SPR_NOACCESS, SPR_NOACCESS,
548
                 &spr_read_ibat, &spr_write_ibatu,
549
                 0x00000000);
550
    spr_register(env, SPR_IBAT2L, "IBAT2L",
551
                 SPR_NOACCESS, SPR_NOACCESS,
552
                 &spr_read_ibat, &spr_write_ibatl,
553
                 0x00000000);
554
    spr_register(env, SPR_IBAT3U, "IBAT3U",
555
                 SPR_NOACCESS, SPR_NOACCESS,
556
                 &spr_read_ibat, &spr_write_ibatu,
557
                 0x00000000);
558
    spr_register(env, SPR_IBAT3L, "IBAT3L",
559
                 SPR_NOACCESS, SPR_NOACCESS,
560
                 &spr_read_ibat, &spr_write_ibatl,
561
                 0x00000000);
562
    spr_register(env, SPR_DBAT0U, "DBAT0U",
563
                 SPR_NOACCESS, SPR_NOACCESS,
564
                 &spr_read_dbat, &spr_write_dbatu,
565
                 0x00000000);
566
    spr_register(env, SPR_DBAT0L, "DBAT0L",
567
                 SPR_NOACCESS, SPR_NOACCESS,
568
                 &spr_read_dbat, &spr_write_dbatl,
569
                 0x00000000);
570
    spr_register(env, SPR_DBAT1U, "DBAT1U",
571
                 SPR_NOACCESS, SPR_NOACCESS,
572
                 &spr_read_dbat, &spr_write_dbatu,
573
                 0x00000000);
574
    spr_register(env, SPR_DBAT1L, "DBAT1L",
575
                 SPR_NOACCESS, SPR_NOACCESS,
576
                 &spr_read_dbat, &spr_write_dbatl,
577
                 0x00000000);
578
    spr_register(env, SPR_DBAT2U, "DBAT2U",
579
                 SPR_NOACCESS, SPR_NOACCESS,
580
                 &spr_read_dbat, &spr_write_dbatu,
581
                 0x00000000);
582
    spr_register(env, SPR_DBAT2L, "DBAT2L",
583
                 SPR_NOACCESS, SPR_NOACCESS,
584
                 &spr_read_dbat, &spr_write_dbatl,
585
                 0x00000000);
586
    spr_register(env, SPR_DBAT3U, "DBAT3U",
587
                 SPR_NOACCESS, SPR_NOACCESS,
588
                 &spr_read_dbat, &spr_write_dbatu,
589
                 0x00000000);
590
    spr_register(env, SPR_DBAT3L, "DBAT3L",
591
                 SPR_NOACCESS, SPR_NOACCESS,
592
                 &spr_read_dbat, &spr_write_dbatl,
593
                 0x00000000);
594
    env->nb_BATs += 4;
595
}
596

    
597
/* BATs 4-7 */
598
static void gen_high_BATs (CPUPPCState *env)
599
{
600
    spr_register(env, SPR_IBAT4U, "IBAT4U",
601
                 SPR_NOACCESS, SPR_NOACCESS,
602
                 &spr_read_ibat_h, &spr_write_ibatu_h,
603
                 0x00000000);
604
    spr_register(env, SPR_IBAT4L, "IBAT4L",
605
                 SPR_NOACCESS, SPR_NOACCESS,
606
                 &spr_read_ibat_h, &spr_write_ibatl_h,
607
                 0x00000000);
608
    spr_register(env, SPR_IBAT5U, "IBAT5U",
609
                 SPR_NOACCESS, SPR_NOACCESS,
610
                 &spr_read_ibat_h, &spr_write_ibatu_h,
611
                 0x00000000);
612
    spr_register(env, SPR_IBAT5L, "IBAT5L",
613
                 SPR_NOACCESS, SPR_NOACCESS,
614
                 &spr_read_ibat_h, &spr_write_ibatl_h,
615
                 0x00000000);
616
    spr_register(env, SPR_IBAT6U, "IBAT6U",
617
                 SPR_NOACCESS, SPR_NOACCESS,
618
                 &spr_read_ibat_h, &spr_write_ibatu_h,
619
                 0x00000000);
620
    spr_register(env, SPR_IBAT6L, "IBAT6L",
621
                 SPR_NOACCESS, SPR_NOACCESS,
622
                 &spr_read_ibat_h, &spr_write_ibatl_h,
623
                 0x00000000);
624
    spr_register(env, SPR_IBAT7U, "IBAT7U",
625
                 SPR_NOACCESS, SPR_NOACCESS,
626
                 &spr_read_ibat_h, &spr_write_ibatu_h,
627
                 0x00000000);
628
    spr_register(env, SPR_IBAT7L, "IBAT7L",
629
                 SPR_NOACCESS, SPR_NOACCESS,
630
                 &spr_read_ibat_h, &spr_write_ibatl_h,
631
                 0x00000000);
632
    spr_register(env, SPR_DBAT4U, "DBAT4U",
633
                 SPR_NOACCESS, SPR_NOACCESS,
634
                 &spr_read_dbat_h, &spr_write_dbatu_h,
635
                 0x00000000);
636
    spr_register(env, SPR_DBAT4L, "DBAT4L",
637
                 SPR_NOACCESS, SPR_NOACCESS,
638
                 &spr_read_dbat_h, &spr_write_dbatl_h,
639
                 0x00000000);
640
    spr_register(env, SPR_DBAT5U, "DBAT5U",
641
                 SPR_NOACCESS, SPR_NOACCESS,
642
                 &spr_read_dbat_h, &spr_write_dbatu_h,
643
                 0x00000000);
644
    spr_register(env, SPR_DBAT5L, "DBAT5L",
645
                 SPR_NOACCESS, SPR_NOACCESS,
646
                 &spr_read_dbat_h, &spr_write_dbatl_h,
647
                 0x00000000);
648
    spr_register(env, SPR_DBAT6U, "DBAT6U",
649
                 SPR_NOACCESS, SPR_NOACCESS,
650
                 &spr_read_dbat_h, &spr_write_dbatu_h,
651
                 0x00000000);
652
    spr_register(env, SPR_DBAT6L, "DBAT6L",
653
                 SPR_NOACCESS, SPR_NOACCESS,
654
                 &spr_read_dbat_h, &spr_write_dbatl_h,
655
                 0x00000000);
656
    spr_register(env, SPR_DBAT7U, "DBAT7U",
657
                 SPR_NOACCESS, SPR_NOACCESS,
658
                 &spr_read_dbat_h, &spr_write_dbatu_h,
659
                 0x00000000);
660
    spr_register(env, SPR_DBAT7L, "DBAT7L",
661
                 SPR_NOACCESS, SPR_NOACCESS,
662
                 &spr_read_dbat_h, &spr_write_dbatl_h,
663
                 0x00000000);
664
    env->nb_BATs += 4;
665
}
666

    
667
/* Generic PowerPC time base */
668
static void gen_tbl (CPUPPCState *env)
669
{
670
    spr_register(env, SPR_VTBL,  "TBL",
671
                 &spr_read_tbl, SPR_NOACCESS,
672
                 &spr_read_tbl, SPR_NOACCESS,
673
                 0x00000000);
674
    spr_register(env, SPR_TBL,   "TBL",
675
                 SPR_NOACCESS, SPR_NOACCESS,
676
                 SPR_NOACCESS, &spr_write_tbl,
677
                 0x00000000);
678
    spr_register(env, SPR_VTBU,  "TBU",
679
                 &spr_read_tbu, SPR_NOACCESS,
680
                 &spr_read_tbu, SPR_NOACCESS,
681
                 0x00000000);
682
    spr_register(env, SPR_TBU,   "TBU",
683
                 SPR_NOACCESS, SPR_NOACCESS,
684
                 SPR_NOACCESS, &spr_write_tbu,
685
                 0x00000000);
686
}
687

    
688
/* Softare table search registers */
689
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
690
{
691
    env->nb_tlb = nb_tlbs;
692
    env->nb_ways = nb_ways;
693
    env->id_tlbs = 1;
694
    spr_register(env, SPR_DMISS, "DMISS",
695
                 SPR_NOACCESS, SPR_NOACCESS,
696
                 &spr_read_generic, SPR_NOACCESS,
697
                 0x00000000);
698
    spr_register(env, SPR_DCMP, "DCMP",
699
                 SPR_NOACCESS, SPR_NOACCESS,
700
                 &spr_read_generic, SPR_NOACCESS,
701
                 0x00000000);
702
    spr_register(env, SPR_HASH1, "HASH1",
703
                 SPR_NOACCESS, SPR_NOACCESS,
704
                 &spr_read_generic, SPR_NOACCESS,
705
                 0x00000000);
706
    spr_register(env, SPR_HASH2, "HASH2",
707
                 SPR_NOACCESS, SPR_NOACCESS,
708
                 &spr_read_generic, SPR_NOACCESS,
709
                 0x00000000);
710
    spr_register(env, SPR_IMISS, "IMISS",
711
                 SPR_NOACCESS, SPR_NOACCESS,
712
                 &spr_read_generic, SPR_NOACCESS,
713
                 0x00000000);
714
    spr_register(env, SPR_ICMP, "ICMP",
715
                 SPR_NOACCESS, SPR_NOACCESS,
716
                 &spr_read_generic, SPR_NOACCESS,
717
                 0x00000000);
718
    spr_register(env, SPR_RPA, "RPA",
719
                 SPR_NOACCESS, SPR_NOACCESS,
720
                 &spr_read_generic, &spr_write_generic,
721
                 0x00000000);
722
}
723

    
724
/* SPR common to MPC755 and G2 */
725
static void gen_spr_G2_755 (CPUPPCState *env)
726
{
727
    /* SGPRs */
728
    spr_register(env, SPR_SPRG4, "SPRG4",
729
                 SPR_NOACCESS, SPR_NOACCESS,
730
                 &spr_read_generic, &spr_write_generic,
731
                 0x00000000);
732
    spr_register(env, SPR_SPRG5, "SPRG5",
733
                 SPR_NOACCESS, SPR_NOACCESS,
734
                 &spr_read_generic, &spr_write_generic,
735
                 0x00000000);
736
    spr_register(env, SPR_SPRG6, "SPRG6",
737
                 SPR_NOACCESS, SPR_NOACCESS,
738
                 &spr_read_generic, &spr_write_generic,
739
                 0x00000000);
740
    spr_register(env, SPR_SPRG7, "SPRG7",
741
                 SPR_NOACCESS, SPR_NOACCESS,
742
                 &spr_read_generic, &spr_write_generic,
743
                 0x00000000);
744
    /* External access control */
745
    /* XXX : not implemented */
746
    spr_register(env, SPR_EAR, "EAR",
747
                 SPR_NOACCESS, SPR_NOACCESS,
748
                 &spr_read_generic, &spr_write_generic,
749
                 0x00000000);
750
}
751

    
752
/* SPR common to all 7xx PowerPC implementations */
753
static void gen_spr_7xx (CPUPPCState *env)
754
{
755
    /* Breakpoints */
756
    /* XXX : not implemented */
757
    spr_register(env, SPR_DABR, "DABR",
758
                 SPR_NOACCESS, SPR_NOACCESS,
759
                 &spr_read_generic, &spr_write_generic,
760
                 0x00000000);
761
    /* XXX : not implemented */
762
    spr_register(env, SPR_IABR, "IABR",
763
                 SPR_NOACCESS, SPR_NOACCESS,
764
                 &spr_read_generic, &spr_write_generic,
765
                 0x00000000);
766
    /* Cache management */
767
    /* XXX : not implemented */
768
    spr_register(env, SPR_ICTC, "ICTC",
769
                 SPR_NOACCESS, SPR_NOACCESS,
770
                 &spr_read_generic, &spr_write_generic,
771
                 0x00000000);
772
    /* XXX : not implemented */
773
    spr_register(env, SPR_L2CR, "L2CR",
774
                 SPR_NOACCESS, SPR_NOACCESS,
775
                 &spr_read_generic, &spr_write_generic,
776
                 0x00000000);
777
    /* Performance monitors */
778
    /* XXX : not implemented */
779
    spr_register(env, SPR_MMCR0, "MMCR0",
780
                 SPR_NOACCESS, SPR_NOACCESS,
781
                 &spr_read_generic, &spr_write_generic,
782
                 0x00000000);
783
    /* XXX : not implemented */
784
    spr_register(env, SPR_MMCR1, "MMCR1",
785
                 SPR_NOACCESS, SPR_NOACCESS,
786
                 &spr_read_generic, &spr_write_generic,
787
                 0x00000000);
788
    /* XXX : not implemented */
789
    spr_register(env, SPR_PMC1, "PMC1",
790
                 SPR_NOACCESS, SPR_NOACCESS,
791
                 &spr_read_generic, &spr_write_generic,
792
                 0x00000000);
793
    /* XXX : not implemented */
794
    spr_register(env, SPR_PMC2, "PMC2",
795
                 SPR_NOACCESS, SPR_NOACCESS,
796
                 &spr_read_generic, &spr_write_generic,
797
                 0x00000000);
798
    /* XXX : not implemented */
799
    spr_register(env, SPR_PMC3, "PMC3",
800
                 SPR_NOACCESS, SPR_NOACCESS,
801
                 &spr_read_generic, &spr_write_generic,
802
                 0x00000000);
803
    /* XXX : not implemented */
804
    spr_register(env, SPR_PMC4, "PMC4",
805
                 SPR_NOACCESS, SPR_NOACCESS,
806
                 &spr_read_generic, &spr_write_generic,
807
                 0x00000000);
808
    /* XXX : not implemented */
809
    spr_register(env, SPR_SIAR, "SIAR",
810
                 SPR_NOACCESS, SPR_NOACCESS,
811
                 &spr_read_generic, SPR_NOACCESS,
812
                 0x00000000);
813
    spr_register(env, SPR_UMMCR0, "UMMCR0",
814
                 &spr_read_ureg, SPR_NOACCESS,
815
                 &spr_read_ureg, SPR_NOACCESS,
816
                 0x00000000);
817
    spr_register(env, SPR_UMMCR1, "UMMCR1",
818
                 &spr_read_ureg, SPR_NOACCESS,
819
                 &spr_read_ureg, SPR_NOACCESS,
820
                 0x00000000);
821
    spr_register(env, SPR_UPMC1, "UPMC1",
822
                 &spr_read_ureg, SPR_NOACCESS,
823
                 &spr_read_ureg, SPR_NOACCESS,
824
                 0x00000000);
825
    spr_register(env, SPR_UPMC2, "UPMC2",
826
                 &spr_read_ureg, SPR_NOACCESS,
827
                 &spr_read_ureg, SPR_NOACCESS,
828
                 0x00000000);
829
    spr_register(env, SPR_UPMC3, "UPMC3",
830
                 &spr_read_ureg, SPR_NOACCESS,
831
                 &spr_read_ureg, SPR_NOACCESS,
832
                 0x00000000);
833
    spr_register(env, SPR_UPMC4, "UPMC4",
834
                 &spr_read_ureg, SPR_NOACCESS,
835
                 &spr_read_ureg, SPR_NOACCESS,
836
                 0x00000000);
837
    spr_register(env, SPR_USIAR, "USIAR",
838
                 &spr_read_ureg, SPR_NOACCESS,
839
                 &spr_read_ureg, SPR_NOACCESS,
840
                 0x00000000);
841
    /* External access control */
842
    /* XXX : not implemented */
843
    spr_register(env, SPR_EAR, "EAR",
844
                 SPR_NOACCESS, SPR_NOACCESS,
845
                 &spr_read_generic, &spr_write_generic,
846
                 0x00000000);
847
}
848

    
849
static void gen_spr_thrm (CPUPPCState *env)
850
{
851
    /* Thermal management */
852
    /* XXX : not implemented */
853
    spr_register(env, SPR_THRM1, "THRM1",
854
                 SPR_NOACCESS, SPR_NOACCESS,
855
                 &spr_read_generic, &spr_write_generic,
856
                 0x00000000);
857
    /* XXX : not implemented */
858
    spr_register(env, SPR_THRM2, "THRM2",
859
                 SPR_NOACCESS, SPR_NOACCESS,
860
                 &spr_read_generic, &spr_write_generic,
861
                 0x00000000);
862
    /* XXX : not implemented */
863
    spr_register(env, SPR_THRM3, "THRM3",
864
                 SPR_NOACCESS, SPR_NOACCESS,
865
                 &spr_read_generic, &spr_write_generic,
866
                 0x00000000);
867
}
868

    
869
/* SPR specific to PowerPC 604 implementation */
870
static void gen_spr_604 (CPUPPCState *env)
871
{
872
    /* Processor identification */
873
    spr_register(env, SPR_PIR, "PIR",
874
                 SPR_NOACCESS, SPR_NOACCESS,
875
                 &spr_read_generic, &spr_write_pir,
876
                 0x00000000);
877
    /* Breakpoints */
878
    /* XXX : not implemented */
879
    spr_register(env, SPR_IABR, "IABR",
880
                 SPR_NOACCESS, SPR_NOACCESS,
881
                 &spr_read_generic, &spr_write_generic,
882
                 0x00000000);
883
    /* XXX : not implemented */
884
    spr_register(env, SPR_DABR, "DABR",
885
                 SPR_NOACCESS, SPR_NOACCESS,
886
                 &spr_read_generic, &spr_write_generic,
887
                 0x00000000);
888
    /* Performance counters */
889
    /* XXX : not implemented */
890
    spr_register(env, SPR_MMCR0, "MMCR0",
891
                 SPR_NOACCESS, SPR_NOACCESS,
892
                 &spr_read_generic, &spr_write_generic,
893
                 0x00000000);
894
    /* XXX : not implemented */
895
    spr_register(env, SPR_MMCR1, "MMCR1",
896
                 SPR_NOACCESS, SPR_NOACCESS,
897
                 &spr_read_generic, &spr_write_generic,
898
                 0x00000000);
899
    /* XXX : not implemented */
900
    spr_register(env, SPR_PMC1, "PMC1",
901
                 SPR_NOACCESS, SPR_NOACCESS,
902
                 &spr_read_generic, &spr_write_generic,
903
                 0x00000000);
904
    /* XXX : not implemented */
905
    spr_register(env, SPR_PMC2, "PMC2",
906
                 SPR_NOACCESS, SPR_NOACCESS,
907
                 &spr_read_generic, &spr_write_generic,
908
                 0x00000000);
909
    /* XXX : not implemented */
910
    spr_register(env, SPR_PMC3, "PMC3",
911
                 SPR_NOACCESS, SPR_NOACCESS,
912
                 &spr_read_generic, &spr_write_generic,
913
                 0x00000000);
914
    /* XXX : not implemented */
915
    spr_register(env, SPR_PMC4, "PMC4",
916
                 SPR_NOACCESS, SPR_NOACCESS,
917
                 &spr_read_generic, &spr_write_generic,
918
                 0x00000000);
919
    /* XXX : not implemented */
920
    spr_register(env, SPR_SIAR, "SIAR",
921
                 SPR_NOACCESS, SPR_NOACCESS,
922
                 &spr_read_generic, SPR_NOACCESS,
923
                 0x00000000);
924
    /* XXX : not implemented */
925
    spr_register(env, SPR_SDA, "SDA",
926
                 SPR_NOACCESS, SPR_NOACCESS,
927
                 &spr_read_generic, SPR_NOACCESS,
928
                 0x00000000);
929
    /* External access control */
930
    /* XXX : not implemented */
931
    spr_register(env, SPR_EAR, "EAR",
932
                 SPR_NOACCESS, SPR_NOACCESS,
933
                 &spr_read_generic, &spr_write_generic,
934
                 0x00000000);
935
}
936

    
937
/* SPR specific to PowerPC 603 implementation */
938
static void gen_spr_603 (CPUPPCState *env)
939
{
940
    /* External access control */
941
    /* XXX : not implemented */
942
    spr_register(env, SPR_EAR, "EAR",
943
                 SPR_NOACCESS, SPR_NOACCESS,
944
                 &spr_read_generic, &spr_write_generic,
945
                 0x00000000);
946
}
947

    
948
/* SPR specific to PowerPC G2 implementation */
949
static void gen_spr_G2 (CPUPPCState *env)
950
{
951
    /* Memory base address */
952
    /* MBAR */
953
    spr_register(env, SPR_MBAR, "MBAR",
954
                 SPR_NOACCESS, SPR_NOACCESS,
955
                 &spr_read_generic, &spr_write_generic,
956
                 0x00000000);
957
    /* System version register */
958
    /* SVR */
959
    spr_register(env, SPR_SVR, "SVR",
960
                 SPR_NOACCESS, SPR_NOACCESS,
961
                 &spr_read_generic, SPR_NOACCESS,
962
                 0x00000000);
963
    /* Exception processing */
964
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
965
                 SPR_NOACCESS, SPR_NOACCESS,
966
                 &spr_read_generic, &spr_write_generic,
967
                 0x00000000);
968
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
969
                 SPR_NOACCESS, SPR_NOACCESS,
970
                 &spr_read_generic, &spr_write_generic,
971
                 0x00000000);
972
    /* Breakpoints */
973
    /* XXX : not implemented */
974
    spr_register(env, SPR_DABR, "DABR",
975
                 SPR_NOACCESS, SPR_NOACCESS,
976
                 &spr_read_generic, &spr_write_generic,
977
                 0x00000000);
978
    /* XXX : not implemented */
979
    spr_register(env, SPR_DABR2, "DABR2",
980
                 SPR_NOACCESS, SPR_NOACCESS,
981
                 &spr_read_generic, &spr_write_generic,
982
                 0x00000000);
983
    /* XXX : not implemented */
984
    spr_register(env, SPR_IABR, "IABR",
985
                 SPR_NOACCESS, SPR_NOACCESS,
986
                 &spr_read_generic, &spr_write_generic,
987
                 0x00000000);
988
    /* XXX : not implemented */
989
    spr_register(env, SPR_IABR2, "IABR2",
990
                 SPR_NOACCESS, SPR_NOACCESS,
991
                 &spr_read_generic, &spr_write_generic,
992
                 0x00000000);
993
    /* XXX : not implemented */
994
    spr_register(env, SPR_IBCR, "IBCR",
995
                 SPR_NOACCESS, SPR_NOACCESS,
996
                 &spr_read_generic, &spr_write_generic,
997
                 0x00000000);
998
    /* XXX : not implemented */
999
    spr_register(env, SPR_DBCR, "DBCR",
1000
                 SPR_NOACCESS, SPR_NOACCESS,
1001
                 &spr_read_generic, &spr_write_generic,
1002
                 0x00000000);
1003
}
1004

    
1005
/* SPR specific to PowerPC 602 implementation */
1006
static void gen_spr_602 (CPUPPCState *env)
1007
{
1008
    /* ESA registers */
1009
    /* XXX : not implemented */
1010
    spr_register(env, SPR_SER, "SER",
1011
                 SPR_NOACCESS, SPR_NOACCESS,
1012
                 &spr_read_generic, &spr_write_generic,
1013
                 0x00000000);
1014
    /* XXX : not implemented */
1015
    spr_register(env, SPR_SEBR, "SEBR",
1016
                 SPR_NOACCESS, SPR_NOACCESS,
1017
                 &spr_read_generic, &spr_write_generic,
1018
                 0x00000000);
1019
    /* XXX : not implemented */
1020
    spr_register(env, SPR_ESASRR, "ESASRR",
1021
                 SPR_NOACCESS, SPR_NOACCESS,
1022
                 &spr_read_generic, &spr_write_generic,
1023
                 0x00000000);
1024
    /* Floating point status */
1025
    /* XXX : not implemented */
1026
    spr_register(env, SPR_SP, "SP",
1027
                 SPR_NOACCESS, SPR_NOACCESS,
1028
                 &spr_read_generic, &spr_write_generic,
1029
                 0x00000000);
1030
    /* XXX : not implemented */
1031
    spr_register(env, SPR_LT, "LT",
1032
                 SPR_NOACCESS, SPR_NOACCESS,
1033
                 &spr_read_generic, &spr_write_generic,
1034
                 0x00000000);
1035
    /* Watchdog timer */
1036
    /* XXX : not implemented */
1037
    spr_register(env, SPR_TCR, "TCR",
1038
                 SPR_NOACCESS, SPR_NOACCESS,
1039
                 &spr_read_generic, &spr_write_generic,
1040
                 0x00000000);
1041
    /* Interrupt base */
1042
    spr_register(env, SPR_IBR, "IBR",
1043
                 SPR_NOACCESS, SPR_NOACCESS,
1044
                 &spr_read_generic, &spr_write_generic,
1045
                 0x00000000);
1046
    /* XXX : not implemented */
1047
    spr_register(env, SPR_IABR, "IABR",
1048
                 SPR_NOACCESS, SPR_NOACCESS,
1049
                 &spr_read_generic, &spr_write_generic,
1050
                 0x00000000);
1051
}
1052

    
1053
/* SPR specific to PowerPC 601 implementation */
1054
static void gen_spr_601 (CPUPPCState *env)
1055
{
1056
    /* Multiplication/division register */
1057
    /* MQ */
1058
    spr_register(env, SPR_MQ, "MQ",
1059
                 &spr_read_generic, &spr_write_generic,
1060
                 &spr_read_generic, &spr_write_generic,
1061
                 0x00000000);
1062
    /* RTC registers */
1063
    spr_register(env, SPR_601_RTCU, "RTCU",
1064
                 SPR_NOACCESS, SPR_NOACCESS,
1065
                 SPR_NOACCESS, &spr_write_601_rtcu,
1066
                 0x00000000);
1067
    spr_register(env, SPR_601_VRTCU, "RTCU",
1068
                 &spr_read_601_rtcu, SPR_NOACCESS,
1069
                 &spr_read_601_rtcu, SPR_NOACCESS,
1070
                 0x00000000);
1071
    spr_register(env, SPR_601_RTCL, "RTCL",
1072
                 SPR_NOACCESS, SPR_NOACCESS,
1073
                 SPR_NOACCESS, &spr_write_601_rtcl,
1074
                 0x00000000);
1075
    spr_register(env, SPR_601_VRTCL, "RTCL",
1076
                 &spr_read_601_rtcl, SPR_NOACCESS,
1077
                 &spr_read_601_rtcl, SPR_NOACCESS,
1078
                 0x00000000);
1079
    /* Timer */
1080
#if 0 /* ? */
1081
    spr_register(env, SPR_601_UDECR, "UDECR",
1082
                 &spr_read_decr, SPR_NOACCESS,
1083
                 &spr_read_decr, SPR_NOACCESS,
1084
                 0x00000000);
1085
#endif
1086
    /* External access control */
1087
    /* XXX : not implemented */
1088
    spr_register(env, SPR_EAR, "EAR",
1089
                 SPR_NOACCESS, SPR_NOACCESS,
1090
                 &spr_read_generic, &spr_write_generic,
1091
                 0x00000000);
1092
    /* Memory management */
1093
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1094
                 SPR_NOACCESS, SPR_NOACCESS,
1095
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1096
                 0x00000000);
1097
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1098
                 SPR_NOACCESS, SPR_NOACCESS,
1099
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1100
                 0x00000000);
1101
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1102
                 SPR_NOACCESS, SPR_NOACCESS,
1103
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1104
                 0x00000000);
1105
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1106
                 SPR_NOACCESS, SPR_NOACCESS,
1107
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1108
                 0x00000000);
1109
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1110
                 SPR_NOACCESS, SPR_NOACCESS,
1111
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1112
                 0x00000000);
1113
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1114
                 SPR_NOACCESS, SPR_NOACCESS,
1115
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1116
                 0x00000000);
1117
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1118
                 SPR_NOACCESS, SPR_NOACCESS,
1119
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1120
                 0x00000000);
1121
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1122
                 SPR_NOACCESS, SPR_NOACCESS,
1123
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1124
                 0x00000000);
1125
    env->nb_BATs = 4;
1126
}
1127

    
1128
static void gen_spr_74xx (CPUPPCState *env)
1129
{
1130
    /* Processor identification */
1131
    spr_register(env, SPR_PIR, "PIR",
1132
                 SPR_NOACCESS, SPR_NOACCESS,
1133
                 &spr_read_generic, &spr_write_pir,
1134
                 0x00000000);
1135
    /* XXX : not implemented */
1136
    spr_register(env, SPR_MMCR2, "MMCR2",
1137
                 SPR_NOACCESS, SPR_NOACCESS,
1138
                 &spr_read_generic, &spr_write_generic,
1139
                 0x00000000);
1140
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1141
                 &spr_read_ureg, SPR_NOACCESS,
1142
                 &spr_read_ureg, SPR_NOACCESS,
1143
                 0x00000000);
1144
    /* XXX: not implemented */
1145
    spr_register(env, SPR_BAMR, "BAMR",
1146
                 SPR_NOACCESS, SPR_NOACCESS,
1147
                 &spr_read_generic, &spr_write_generic,
1148
                 0x00000000);
1149
    spr_register(env, SPR_UBAMR, "UBAMR",
1150
                 &spr_read_ureg, SPR_NOACCESS,
1151
                 &spr_read_ureg, SPR_NOACCESS,
1152
                 0x00000000);
1153
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1154
                 SPR_NOACCESS, SPR_NOACCESS,
1155
                 &spr_read_generic, &spr_write_generic,
1156
                 0x00000000);
1157
    /* Hardware implementation registers */
1158
    /* XXX : not implemented */
1159
    spr_register(env, SPR_HID0, "HID0",
1160
                 SPR_NOACCESS, SPR_NOACCESS,
1161
                 &spr_read_generic, &spr_write_generic,
1162
                 0x00000000);
1163
    /* XXX : not implemented */
1164
    spr_register(env, SPR_HID1, "HID1",
1165
                 SPR_NOACCESS, SPR_NOACCESS,
1166
                 &spr_read_generic, &spr_write_generic,
1167
                 0x00000000);
1168
    /* Altivec */
1169
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1170
                 &spr_read_generic, &spr_write_generic,
1171
                 &spr_read_generic, &spr_write_generic,
1172
                 0x00000000);
1173
}
1174

    
1175
#if defined (TODO)
1176
static void gen_l3_ctrl (CPUPPCState *env)
1177
{
1178
    /* L3CR */
1179
    /* XXX : not implemented */
1180
    spr_register(env, SPR_L3CR, "L3CR",
1181
                 SPR_NOACCESS, SPR_NOACCESS,
1182
                 &spr_read_generic, &spr_write_generic,
1183
                 0x00000000);
1184
    /* L3ITCR0 */
1185
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1186
                 SPR_NOACCESS, SPR_NOACCESS,
1187
                 &spr_read_generic, &spr_write_generic,
1188
                 0x00000000);
1189
    /* L3ITCR1 */
1190
    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1191
                 SPR_NOACCESS, SPR_NOACCESS,
1192
                 &spr_read_generic, &spr_write_generic,
1193
                 0x00000000);
1194
    /* L3ITCR2 */
1195
    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1196
                 SPR_NOACCESS, SPR_NOACCESS,
1197
                 &spr_read_generic, &spr_write_generic,
1198
                 0x00000000);
1199
    /* L3ITCR3 */
1200
    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1201
                 SPR_NOACCESS, SPR_NOACCESS,
1202
                 &spr_read_generic, &spr_write_generic,
1203
                 0x00000000);
1204
    /* L3OHCR */
1205
    spr_register(env, SPR_L3OHCR, "L3OHCR",
1206
                 SPR_NOACCESS, SPR_NOACCESS,
1207
                 &spr_read_generic, &spr_write_generic,
1208
                 0x00000000);
1209
    /* L3PM */
1210
    spr_register(env, SPR_L3PM, "L3PM",
1211
                 SPR_NOACCESS, SPR_NOACCESS,
1212
                 &spr_read_generic, &spr_write_generic,
1213
                 0x00000000);
1214
}
1215
#endif /* TODO */
1216

    
1217
#if defined (TODO)
1218
static void gen_74xx_soft_tlb (CPUPPCState *env)
1219
{
1220
    /* XXX: TODO */
1221
    spr_register(env, SPR_PTEHI, "PTEHI",
1222
                 SPR_NOACCESS, SPR_NOACCESS,
1223
                 &spr_read_generic, &spr_write_generic,
1224
                 0x00000000);
1225
    spr_register(env, SPR_PTELO, "PTELO",
1226
                 SPR_NOACCESS, SPR_NOACCESS,
1227
                 &spr_read_generic, &spr_write_generic,
1228
                 0x00000000);
1229
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1230
                 SPR_NOACCESS, SPR_NOACCESS,
1231
                 &spr_read_generic, &spr_write_generic,
1232
                 0x00000000);
1233
}
1234
#endif /* TODO */
1235

    
1236
/* PowerPC BookE SPR */
1237
static void gen_spr_BookE (CPUPPCState *env)
1238
{
1239
    /* Processor identification */
1240
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1241
                 SPR_NOACCESS, SPR_NOACCESS,
1242
                 &spr_read_generic, &spr_write_pir,
1243
                 0x00000000);
1244
    /* Interrupt processing */
1245
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1246
                 SPR_NOACCESS, SPR_NOACCESS,
1247
                 &spr_read_generic, &spr_write_generic,
1248
                 0x00000000);
1249
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1250
                 SPR_NOACCESS, SPR_NOACCESS,
1251
                 &spr_read_generic, &spr_write_generic,
1252
                 0x00000000);
1253
#if 0
1254
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1255
                 SPR_NOACCESS, SPR_NOACCESS,
1256
                 &spr_read_generic, &spr_write_generic,
1257
                 0x00000000);
1258
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1259
                 SPR_NOACCESS, SPR_NOACCESS,
1260
                 &spr_read_generic, &spr_write_generic,
1261
                 0x00000000);
1262
#endif
1263
    /* Debug */
1264
    /* XXX : not implemented */
1265
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1266
                 SPR_NOACCESS, SPR_NOACCESS,
1267
                 &spr_read_generic, &spr_write_generic,
1268
                 0x00000000);
1269
    /* XXX : not implemented */
1270
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1271
                 SPR_NOACCESS, SPR_NOACCESS,
1272
                 &spr_read_generic, &spr_write_generic,
1273
                 0x00000000);
1274
    /* XXX : not implemented */
1275
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1276
                 SPR_NOACCESS, SPR_NOACCESS,
1277
                 &spr_read_generic, &spr_write_generic,
1278
                 0x00000000);
1279
    /* XXX : not implemented */
1280
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1281
                 SPR_NOACCESS, SPR_NOACCESS,
1282
                 &spr_read_generic, &spr_write_generic,
1283
                 0x00000000);
1284
    /* XXX : not implemented */
1285
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1286
                 SPR_NOACCESS, SPR_NOACCESS,
1287
                 &spr_read_generic, &spr_write_generic,
1288
                 0x00000000);
1289
    /* XXX : not implemented */
1290
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1291
                 SPR_NOACCESS, SPR_NOACCESS,
1292
                 &spr_read_generic, &spr_write_generic,
1293
                 0x00000000);
1294
    /* XXX : not implemented */
1295
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1296
                 SPR_NOACCESS, SPR_NOACCESS,
1297
                 &spr_read_generic, &spr_write_generic,
1298
                 0x00000000);
1299
    /* XXX : not implemented */
1300
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1301
                 SPR_NOACCESS, SPR_NOACCESS,
1302
                 &spr_read_generic, &spr_write_generic,
1303
                 0x00000000);
1304
    /* XXX : not implemented */
1305
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1306
                 SPR_NOACCESS, SPR_NOACCESS,
1307
                 &spr_read_generic, &spr_write_generic,
1308
                 0x00000000);
1309
    /* XXX : not implemented */
1310
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1311
                 SPR_NOACCESS, SPR_NOACCESS,
1312
                 &spr_read_generic, &spr_write_generic,
1313
                 0x00000000);
1314
    /* XXX : not implemented */
1315
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1316
                 SPR_NOACCESS, SPR_NOACCESS,
1317
                 &spr_read_generic, &spr_write_generic,
1318
                 0x00000000);
1319
    /* XXX : not implemented */
1320
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1321
                 SPR_NOACCESS, SPR_NOACCESS,
1322
                 &spr_read_generic, &spr_write_clear,
1323
                 0x00000000);
1324
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1325
                 SPR_NOACCESS, SPR_NOACCESS,
1326
                 &spr_read_generic, &spr_write_generic,
1327
                 0x00000000);
1328
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1329
                 SPR_NOACCESS, SPR_NOACCESS,
1330
                 &spr_read_generic, &spr_write_generic,
1331
                 0x00000000);
1332
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1333
                 SPR_NOACCESS, SPR_NOACCESS,
1334
                 &spr_read_generic, &spr_write_generic,
1335
                 0x00000000);
1336
    /* Exception vectors */
1337
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1338
                 SPR_NOACCESS, SPR_NOACCESS,
1339
                 &spr_read_generic, &spr_write_generic,
1340
                 0x00000000);
1341
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1342
                 SPR_NOACCESS, SPR_NOACCESS,
1343
                 &spr_read_generic, &spr_write_generic,
1344
                 0x00000000);
1345
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1346
                 SPR_NOACCESS, SPR_NOACCESS,
1347
                 &spr_read_generic, &spr_write_generic,
1348
                 0x00000000);
1349
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1350
                 SPR_NOACCESS, SPR_NOACCESS,
1351
                 &spr_read_generic, &spr_write_generic,
1352
                 0x00000000);
1353
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1354
                 SPR_NOACCESS, SPR_NOACCESS,
1355
                 &spr_read_generic, &spr_write_generic,
1356
                 0x00000000);
1357
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1358
                 SPR_NOACCESS, SPR_NOACCESS,
1359
                 &spr_read_generic, &spr_write_generic,
1360
                 0x00000000);
1361
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1362
                 SPR_NOACCESS, SPR_NOACCESS,
1363
                 &spr_read_generic, &spr_write_generic,
1364
                 0x00000000);
1365
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1366
                 SPR_NOACCESS, SPR_NOACCESS,
1367
                 &spr_read_generic, &spr_write_generic,
1368
                 0x00000000);
1369
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1370
                 SPR_NOACCESS, SPR_NOACCESS,
1371
                 &spr_read_generic, &spr_write_generic,
1372
                 0x00000000);
1373
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1374
                 SPR_NOACCESS, SPR_NOACCESS,
1375
                 &spr_read_generic, &spr_write_generic,
1376
                 0x00000000);
1377
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1378
                 SPR_NOACCESS, SPR_NOACCESS,
1379
                 &spr_read_generic, &spr_write_generic,
1380
                 0x00000000);
1381
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1382
                 SPR_NOACCESS, SPR_NOACCESS,
1383
                 &spr_read_generic, &spr_write_generic,
1384
                 0x00000000);
1385
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1386
                 SPR_NOACCESS, SPR_NOACCESS,
1387
                 &spr_read_generic, &spr_write_generic,
1388
                 0x00000000);
1389
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1390
                 SPR_NOACCESS, SPR_NOACCESS,
1391
                 &spr_read_generic, &spr_write_generic,
1392
                 0x00000000);
1393
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1394
                 SPR_NOACCESS, SPR_NOACCESS,
1395
                 &spr_read_generic, &spr_write_generic,
1396
                 0x00000000);
1397
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1398
                 SPR_NOACCESS, SPR_NOACCESS,
1399
                 &spr_read_generic, &spr_write_generic,
1400
                 0x00000000);
1401
#if 0
1402
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1403
                 SPR_NOACCESS, SPR_NOACCESS,
1404
                 &spr_read_generic, &spr_write_generic,
1405
                 0x00000000);
1406
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1407
                 SPR_NOACCESS, SPR_NOACCESS,
1408
                 &spr_read_generic, &spr_write_generic,
1409
                 0x00000000);
1410
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1411
                 SPR_NOACCESS, SPR_NOACCESS,
1412
                 &spr_read_generic, &spr_write_generic,
1413
                 0x00000000);
1414
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1415
                 SPR_NOACCESS, SPR_NOACCESS,
1416
                 &spr_read_generic, &spr_write_generic,
1417
                 0x00000000);
1418
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1419
                 SPR_NOACCESS, SPR_NOACCESS,
1420
                 &spr_read_generic, &spr_write_generic,
1421
                 0x00000000);
1422
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1423
                 SPR_NOACCESS, SPR_NOACCESS,
1424
                 &spr_read_generic, &spr_write_generic,
1425
                 0x00000000);
1426
#endif
1427
    spr_register(env, SPR_BOOKE_PID, "PID",
1428
                 SPR_NOACCESS, SPR_NOACCESS,
1429
                 &spr_read_generic, &spr_write_generic,
1430
                 0x00000000);
1431
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1432
                 SPR_NOACCESS, SPR_NOACCESS,
1433
                 &spr_read_generic, &spr_write_booke_tcr,
1434
                 0x00000000);
1435
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1436
                 SPR_NOACCESS, SPR_NOACCESS,
1437
                 &spr_read_generic, &spr_write_booke_tsr,
1438
                 0x00000000);
1439
    /* Timer */
1440
    spr_register(env, SPR_DECR, "DECR",
1441
                 SPR_NOACCESS, SPR_NOACCESS,
1442
                 &spr_read_decr, &spr_write_decr,
1443
                 0x00000000);
1444
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1445
                 SPR_NOACCESS, SPR_NOACCESS,
1446
                 SPR_NOACCESS, &spr_write_generic,
1447
                 0x00000000);
1448
    /* SPRGs */
1449
    spr_register(env, SPR_USPRG0, "USPRG0",
1450
                 &spr_read_generic, &spr_write_generic,
1451
                 &spr_read_generic, &spr_write_generic,
1452
                 0x00000000);
1453
    spr_register(env, SPR_SPRG4, "SPRG4",
1454
                 SPR_NOACCESS, SPR_NOACCESS,
1455
                 &spr_read_generic, &spr_write_generic,
1456
                 0x00000000);
1457
    spr_register(env, SPR_USPRG4, "USPRG4",
1458
                 &spr_read_ureg, SPR_NOACCESS,
1459
                 &spr_read_ureg, SPR_NOACCESS,
1460
                 0x00000000);
1461
    spr_register(env, SPR_SPRG5, "SPRG5",
1462
                 SPR_NOACCESS, SPR_NOACCESS,
1463
                 &spr_read_generic, &spr_write_generic,
1464
                 0x00000000);
1465
    spr_register(env, SPR_USPRG5, "USPRG5",
1466
                 &spr_read_ureg, SPR_NOACCESS,
1467
                 &spr_read_ureg, SPR_NOACCESS,
1468
                 0x00000000);
1469
    spr_register(env, SPR_SPRG6, "SPRG6",
1470
                 SPR_NOACCESS, SPR_NOACCESS,
1471
                 &spr_read_generic, &spr_write_generic,
1472
                 0x00000000);
1473
    spr_register(env, SPR_USPRG6, "USPRG6",
1474
                 &spr_read_ureg, SPR_NOACCESS,
1475
                 &spr_read_ureg, SPR_NOACCESS,
1476
                 0x00000000);
1477
    spr_register(env, SPR_SPRG7, "SPRG7",
1478
                 SPR_NOACCESS, SPR_NOACCESS,
1479
                 &spr_read_generic, &spr_write_generic,
1480
                 0x00000000);
1481
    spr_register(env, SPR_USPRG7, "USPRG7",
1482
                 &spr_read_ureg, SPR_NOACCESS,
1483
                 &spr_read_ureg, SPR_NOACCESS,
1484
                 0x00000000);
1485
}
1486

    
1487
/* FSL storage control registers */
1488
#if defined(TODO)
1489
static void gen_spr_BookE_FSL (CPUPPCState *env)
1490
{
1491
    /* TLB assist registers */
1492
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1493
                 SPR_NOACCESS, SPR_NOACCESS,
1494
                 &spr_read_generic, &spr_write_generic,
1495
                 0x00000000);
1496
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1497
                 SPR_NOACCESS, SPR_NOACCESS,
1498
                 &spr_read_generic, &spr_write_generic,
1499
                 0x00000000);
1500
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1501
                 SPR_NOACCESS, SPR_NOACCESS,
1502
                 &spr_read_generic, &spr_write_generic,
1503
                 0x00000000);
1504
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1505
                 SPR_NOACCESS, SPR_NOACCESS,
1506
                 &spr_read_generic, &spr_write_generic,
1507
                 0x00000000);
1508
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1509
                 SPR_NOACCESS, SPR_NOACCESS,
1510
                 &spr_read_generic, &spr_write_generic,
1511
                 0x00000000);
1512
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1513
                 SPR_NOACCESS, SPR_NOACCESS,
1514
                 &spr_read_generic, &spr_write_generic,
1515
                 0x00000000);
1516
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1517
                 SPR_NOACCESS, SPR_NOACCESS,
1518
                 &spr_read_generic, &spr_write_generic,
1519
                 0x00000000);
1520
    if (env->nb_pids > 1) {
1521
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1522
                     SPR_NOACCESS, SPR_NOACCESS,
1523
                     &spr_read_generic, &spr_write_generic,
1524
                     0x00000000);
1525
    }
1526
    if (env->nb_pids > 2) {
1527
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1528
                     SPR_NOACCESS, SPR_NOACCESS,
1529
                     &spr_read_generic, &spr_write_generic,
1530
                     0x00000000);
1531
    }
1532
    spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1533
                 SPR_NOACCESS, SPR_NOACCESS,
1534
                 &spr_read_generic, SPR_NOACCESS,
1535
                 0x00000000); /* TOFIX */
1536
    spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1537
                 SPR_NOACCESS, SPR_NOACCESS,
1538
                 &spr_read_generic, &spr_write_generic,
1539
                 0x00000000); /* TOFIX */
1540
    switch (env->nb_ways) {
1541
    case 4:
1542
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1543
                     SPR_NOACCESS, SPR_NOACCESS,
1544
                     &spr_read_generic, SPR_NOACCESS,
1545
                     0x00000000); /* TOFIX */
1546
        /* Fallthru */
1547
    case 3:
1548
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1549
                     SPR_NOACCESS, SPR_NOACCESS,
1550
                     &spr_read_generic, SPR_NOACCESS,
1551
                     0x00000000); /* TOFIX */
1552
        /* Fallthru */
1553
    case 2:
1554
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1555
                     SPR_NOACCESS, SPR_NOACCESS,
1556
                     &spr_read_generic, SPR_NOACCESS,
1557
                     0x00000000); /* TOFIX */
1558
        /* Fallthru */
1559
    case 1:
1560
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1561
                     SPR_NOACCESS, SPR_NOACCESS,
1562
                     &spr_read_generic, SPR_NOACCESS,
1563
                     0x00000000); /* TOFIX */
1564
        /* Fallthru */
1565
    case 0:
1566
    default:
1567
        break;
1568
    }
1569
}
1570
#endif
1571

    
1572
/* SPR specific to PowerPC 440 implementation */
1573
static void gen_spr_440 (CPUPPCState *env)
1574
{
1575
    /* Cache control */
1576
    /* XXX : not implemented */
1577
    spr_register(env, SPR_440_DNV0, "DNV0",
1578
                 SPR_NOACCESS, SPR_NOACCESS,
1579
                 &spr_read_generic, &spr_write_generic,
1580
                 0x00000000);
1581
    /* XXX : not implemented */
1582
    spr_register(env, SPR_440_DNV1, "DNV1",
1583
                 SPR_NOACCESS, SPR_NOACCESS,
1584
                 &spr_read_generic, &spr_write_generic,
1585
                 0x00000000);
1586
    /* XXX : not implemented */
1587
    spr_register(env, SPR_440_DNV2, "DNV2",
1588
                 SPR_NOACCESS, SPR_NOACCESS,
1589
                 &spr_read_generic, &spr_write_generic,
1590
                 0x00000000);
1591
    /* XXX : not implemented */
1592
    spr_register(env, SPR_440_DNV3, "DNV3",
1593
                 SPR_NOACCESS, SPR_NOACCESS,
1594
                 &spr_read_generic, &spr_write_generic,
1595
                 0x00000000);
1596
    /* XXX : not implemented */
1597
    spr_register(env, SPR_440_DTV0, "DTV0",
1598
                 SPR_NOACCESS, SPR_NOACCESS,
1599
                 &spr_read_generic, &spr_write_generic,
1600
                 0x00000000);
1601
    /* XXX : not implemented */
1602
    spr_register(env, SPR_440_DTV1, "DTV1",
1603
                 SPR_NOACCESS, SPR_NOACCESS,
1604
                 &spr_read_generic, &spr_write_generic,
1605
                 0x00000000);
1606
    /* XXX : not implemented */
1607
    spr_register(env, SPR_440_DTV2, "DTV2",
1608
                 SPR_NOACCESS, SPR_NOACCESS,
1609
                 &spr_read_generic, &spr_write_generic,
1610
                 0x00000000);
1611
    /* XXX : not implemented */
1612
    spr_register(env, SPR_440_DTV3, "DTV3",
1613
                 SPR_NOACCESS, SPR_NOACCESS,
1614
                 &spr_read_generic, &spr_write_generic,
1615
                 0x00000000);
1616
    /* XXX : not implemented */
1617
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1618
                 SPR_NOACCESS, SPR_NOACCESS,
1619
                 &spr_read_generic, &spr_write_generic,
1620
                 0x00000000);
1621
    /* XXX : not implemented */
1622
    spr_register(env, SPR_440_INV0, "INV0",
1623
                 SPR_NOACCESS, SPR_NOACCESS,
1624
                 &spr_read_generic, &spr_write_generic,
1625
                 0x00000000);
1626
    /* XXX : not implemented */
1627
    spr_register(env, SPR_440_INV1, "INV1",
1628
                 SPR_NOACCESS, SPR_NOACCESS,
1629
                 &spr_read_generic, &spr_write_generic,
1630
                 0x00000000);
1631
    /* XXX : not implemented */
1632
    spr_register(env, SPR_440_INV2, "INV2",
1633
                 SPR_NOACCESS, SPR_NOACCESS,
1634
                 &spr_read_generic, &spr_write_generic,
1635
                 0x00000000);
1636
    /* XXX : not implemented */
1637
    spr_register(env, SPR_440_INV3, "INV3",
1638
                 SPR_NOACCESS, SPR_NOACCESS,
1639
                 &spr_read_generic, &spr_write_generic,
1640
                 0x00000000);
1641
    /* XXX : not implemented */
1642
    spr_register(env, SPR_440_ITV0, "ITV0",
1643
                 SPR_NOACCESS, SPR_NOACCESS,
1644
                 &spr_read_generic, &spr_write_generic,
1645
                 0x00000000);
1646
    /* XXX : not implemented */
1647
    spr_register(env, SPR_440_ITV1, "ITV1",
1648
                 SPR_NOACCESS, SPR_NOACCESS,
1649
                 &spr_read_generic, &spr_write_generic,
1650
                 0x00000000);
1651
    /* XXX : not implemented */
1652
    spr_register(env, SPR_440_ITV2, "ITV2",
1653
                 SPR_NOACCESS, SPR_NOACCESS,
1654
                 &spr_read_generic, &spr_write_generic,
1655
                 0x00000000);
1656
    /* XXX : not implemented */
1657
    spr_register(env, SPR_440_ITV3, "ITV3",
1658
                 SPR_NOACCESS, SPR_NOACCESS,
1659
                 &spr_read_generic, &spr_write_generic,
1660
                 0x00000000);
1661
    /* XXX : not implemented */
1662
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1663
                 SPR_NOACCESS, SPR_NOACCESS,
1664
                 &spr_read_generic, &spr_write_generic,
1665
                 0x00000000);
1666
    /* Cache debug */
1667
    /* XXX : not implemented */
1668
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1669
                 SPR_NOACCESS, SPR_NOACCESS,
1670
                 &spr_read_generic, SPR_NOACCESS,
1671
                 0x00000000);
1672
    /* XXX : not implemented */
1673
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1674
                 SPR_NOACCESS, SPR_NOACCESS,
1675
                 &spr_read_generic, SPR_NOACCESS,
1676
                 0x00000000);
1677
    /* XXX : not implemented */
1678
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1679
                 SPR_NOACCESS, SPR_NOACCESS,
1680
                 &spr_read_generic, SPR_NOACCESS,
1681
                 0x00000000);
1682
    /* XXX : not implemented */
1683
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1684
                 SPR_NOACCESS, SPR_NOACCESS,
1685
                 &spr_read_generic, SPR_NOACCESS,
1686
                 0x00000000);
1687
    /* XXX : not implemented */
1688
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1689
                 SPR_NOACCESS, SPR_NOACCESS,
1690
                 &spr_read_generic, SPR_NOACCESS,
1691
                 0x00000000);
1692
    /* XXX : not implemented */
1693
    spr_register(env, SPR_440_DBDR, "DBDR",
1694
                 SPR_NOACCESS, SPR_NOACCESS,
1695
                 &spr_read_generic, &spr_write_generic,
1696
                 0x00000000);
1697
    /* Processor control */
1698
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1699
                 SPR_NOACCESS, SPR_NOACCESS,
1700
                 &spr_read_generic, &spr_write_generic,
1701
                 0x00000000);
1702
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1703
                 SPR_NOACCESS, SPR_NOACCESS,
1704
                 &spr_read_generic, SPR_NOACCESS,
1705
                 0x00000000);
1706
    /* Storage control */
1707
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1708
                 SPR_NOACCESS, SPR_NOACCESS,
1709
                 &spr_read_generic, &spr_write_generic,
1710
                 0x00000000);
1711
}
1712

    
1713
/* SPR shared between PowerPC 40x implementations */
1714
static void gen_spr_40x (CPUPPCState *env)
1715
{
1716
    /* Cache */
1717
    /* XXX : not implemented */
1718
    spr_register(env, SPR_40x_DCCR, "DCCR",
1719
                 SPR_NOACCESS, SPR_NOACCESS,
1720
                 &spr_read_generic, &spr_write_generic,
1721
                 0x00000000);
1722
    /* XXX : not implemented */
1723
    spr_register(env, SPR_40x_ICCR, "ICCR",
1724
                 SPR_NOACCESS, SPR_NOACCESS,
1725
                 &spr_read_generic, &spr_write_generic,
1726
                 0x00000000);
1727
    /* XXX : not implemented */
1728
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1729
                 SPR_NOACCESS, SPR_NOACCESS,
1730
                 &spr_read_generic, SPR_NOACCESS,
1731
                 0x00000000);
1732
    /* Exception */
1733
    spr_register(env, SPR_40x_DEAR, "DEAR",
1734
                 SPR_NOACCESS, SPR_NOACCESS,
1735
                 &spr_read_generic, &spr_write_generic,
1736
                 0x00000000);
1737
    spr_register(env, SPR_40x_ESR, "ESR",
1738
                 SPR_NOACCESS, SPR_NOACCESS,
1739
                 &spr_read_generic, &spr_write_generic,
1740
                 0x00000000);
1741
    spr_register(env, SPR_40x_EVPR, "EVPR",
1742
                 SPR_NOACCESS, SPR_NOACCESS,
1743
                 &spr_read_generic, &spr_write_generic,
1744
                 0x00000000);
1745
    spr_register(env, SPR_40x_SRR2, "SRR2",
1746
                 &spr_read_generic, &spr_write_generic,
1747
                 &spr_read_generic, &spr_write_generic,
1748
                 0x00000000);
1749
    spr_register(env, SPR_40x_SRR3, "SRR3",
1750
                 &spr_read_generic, &spr_write_generic,
1751
                 &spr_read_generic, &spr_write_generic,
1752
                 0x00000000);
1753
    /* Timers */
1754
    spr_register(env, SPR_40x_PIT, "PIT",
1755
                 SPR_NOACCESS, SPR_NOACCESS,
1756
                 &spr_read_40x_pit, &spr_write_40x_pit,
1757
                 0x00000000);
1758
    spr_register(env, SPR_40x_TCR, "TCR",
1759
                 SPR_NOACCESS, SPR_NOACCESS,
1760
                 &spr_read_generic, &spr_write_booke_tcr,
1761
                 0x00000000);
1762
    spr_register(env, SPR_40x_TSR, "TSR",
1763
                 SPR_NOACCESS, SPR_NOACCESS,
1764
                 &spr_read_generic, &spr_write_booke_tsr,
1765
                 0x00000000);
1766
}
1767

    
1768
/* SPR specific to PowerPC 405 implementation */
1769
static void gen_spr_405 (CPUPPCState *env)
1770
{
1771
    /* MMU */
1772
    spr_register(env, SPR_40x_PID, "PID",
1773
                 SPR_NOACCESS, SPR_NOACCESS,
1774
                 &spr_read_generic, &spr_write_generic,
1775
                 0x00000000);
1776
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1777
                 SPR_NOACCESS, SPR_NOACCESS,
1778
                 &spr_read_generic, &spr_write_generic,
1779
                 0x00700000);
1780
    /* Debug interface */
1781
    /* XXX : not implemented */
1782
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1783
                 SPR_NOACCESS, SPR_NOACCESS,
1784
                 &spr_read_generic, &spr_write_40x_dbcr0,
1785
                 0x00000000);
1786
    /* XXX : not implemented */
1787
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1788
                 SPR_NOACCESS, SPR_NOACCESS,
1789
                 &spr_read_generic, &spr_write_generic,
1790
                 0x00000000);
1791
    /* XXX : not implemented */
1792
    spr_register(env, SPR_40x_DBSR, "DBSR",
1793
                 SPR_NOACCESS, SPR_NOACCESS,
1794
                 &spr_read_generic, &spr_write_clear,
1795
                 /* Last reset was system reset */
1796
                 0x00000300);
1797
    /* XXX : not implemented */
1798
    spr_register(env, SPR_40x_DAC1, "DAC1",
1799
                 SPR_NOACCESS, SPR_NOACCESS,
1800
                 &spr_read_generic, &spr_write_generic,
1801
                 0x00000000);
1802
    spr_register(env, SPR_40x_DAC2, "DAC2",
1803
                 SPR_NOACCESS, SPR_NOACCESS,
1804
                 &spr_read_generic, &spr_write_generic,
1805
                 0x00000000);
1806
    /* XXX : not implemented */
1807
    spr_register(env, SPR_405_DVC1, "DVC1",
1808
                 SPR_NOACCESS, SPR_NOACCESS,
1809
                 &spr_read_generic, &spr_write_generic,
1810
                 0x00000000);
1811
    /* XXX : not implemented */
1812
    spr_register(env, SPR_405_DVC2, "DVC2",
1813
                 SPR_NOACCESS, SPR_NOACCESS,
1814
                 &spr_read_generic, &spr_write_generic,
1815
                 0x00000000);
1816
    /* XXX : not implemented */
1817
    spr_register(env, SPR_40x_IAC1, "IAC1",
1818
                 SPR_NOACCESS, SPR_NOACCESS,
1819
                 &spr_read_generic, &spr_write_generic,
1820
                 0x00000000);
1821
    spr_register(env, SPR_40x_IAC2, "IAC2",
1822
                 SPR_NOACCESS, SPR_NOACCESS,
1823
                 &spr_read_generic, &spr_write_generic,
1824
                 0x00000000);
1825
    /* XXX : not implemented */
1826
    spr_register(env, SPR_405_IAC3, "IAC3",
1827
                 SPR_NOACCESS, SPR_NOACCESS,
1828
                 &spr_read_generic, &spr_write_generic,
1829
                 0x00000000);
1830
    /* XXX : not implemented */
1831
    spr_register(env, SPR_405_IAC4, "IAC4",
1832
                 SPR_NOACCESS, SPR_NOACCESS,
1833
                 &spr_read_generic, &spr_write_generic,
1834
                 0x00000000);
1835
    /* Storage control */
1836
    spr_register(env, SPR_405_SLER, "SLER",
1837
                 SPR_NOACCESS, SPR_NOACCESS,
1838
                 &spr_read_generic, &spr_write_40x_sler,
1839
                 0x00000000);
1840
    spr_register(env, SPR_40x_ZPR, "ZPR",
1841
                 SPR_NOACCESS, SPR_NOACCESS,
1842
                 &spr_read_generic, &spr_write_generic,
1843
                 0x00000000);
1844
    /* XXX : not implemented */
1845
    spr_register(env, SPR_405_SU0R, "SU0R",
1846
                 SPR_NOACCESS, SPR_NOACCESS,
1847
                 &spr_read_generic, &spr_write_generic,
1848
                 0x00000000);
1849
    /* SPRG */
1850
    spr_register(env, SPR_USPRG0, "USPRG0",
1851
                 &spr_read_ureg, SPR_NOACCESS,
1852
                 &spr_read_ureg, SPR_NOACCESS,
1853
                 0x00000000);
1854
    spr_register(env, SPR_SPRG4, "SPRG4",
1855
                 SPR_NOACCESS, SPR_NOACCESS,
1856
                 &spr_read_generic, &spr_write_generic,
1857
                 0x00000000);
1858
    spr_register(env, SPR_USPRG4, "USPRG4",
1859
                 &spr_read_ureg, SPR_NOACCESS,
1860
                 &spr_read_ureg, SPR_NOACCESS,
1861
                 0x00000000);
1862
    spr_register(env, SPR_SPRG5, "SPRG5",
1863
                 SPR_NOACCESS, SPR_NOACCESS,
1864
                 spr_read_generic, &spr_write_generic,
1865
                 0x00000000);
1866
    spr_register(env, SPR_USPRG5, "USPRG5",
1867
                 &spr_read_ureg, SPR_NOACCESS,
1868
                 &spr_read_ureg, SPR_NOACCESS,
1869
                 0x00000000);
1870
    spr_register(env, SPR_SPRG6, "SPRG6",
1871
                 SPR_NOACCESS, SPR_NOACCESS,
1872
                 spr_read_generic, &spr_write_generic,
1873
                 0x00000000);
1874
    spr_register(env, SPR_USPRG6, "USPRG6",
1875
                 &spr_read_ureg, SPR_NOACCESS,
1876
                 &spr_read_ureg, SPR_NOACCESS,
1877
                 0x00000000);
1878
    spr_register(env, SPR_SPRG7, "SPRG7",
1879
                 SPR_NOACCESS, SPR_NOACCESS,
1880
                 spr_read_generic, &spr_write_generic,
1881
                 0x00000000);
1882
    spr_register(env, SPR_USPRG7, "USPRG7",
1883
                 &spr_read_ureg, SPR_NOACCESS,
1884
                 &spr_read_ureg, SPR_NOACCESS,
1885
                 0x00000000);
1886
}
1887

    
1888
/* SPR shared between PowerPC 401 & 403 implementations */
1889
static void gen_spr_401_403 (CPUPPCState *env)
1890
{
1891
    /* Time base */
1892
    spr_register(env, SPR_403_VTBL,  "TBL",
1893
                 &spr_read_tbl, SPR_NOACCESS,
1894
                 &spr_read_tbl, SPR_NOACCESS,
1895
                 0x00000000);
1896
    spr_register(env, SPR_403_TBL,   "TBL",
1897
                 SPR_NOACCESS, SPR_NOACCESS,
1898
                 SPR_NOACCESS, &spr_write_tbl,
1899
                 0x00000000);
1900
    spr_register(env, SPR_403_VTBU,  "TBU",
1901
                 &spr_read_tbu, SPR_NOACCESS,
1902
                 &spr_read_tbu, SPR_NOACCESS,
1903
                 0x00000000);
1904
    spr_register(env, SPR_403_TBU,   "TBU",
1905
                 SPR_NOACCESS, SPR_NOACCESS,
1906
                 SPR_NOACCESS, &spr_write_tbu,
1907
                 0x00000000);
1908
    /* Debug */
1909
    /* XXX: not implemented */
1910
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1911
                 SPR_NOACCESS, SPR_NOACCESS,
1912
                 &spr_read_generic, &spr_write_generic,
1913
                 0x00000000);
1914
}
1915

    
1916
/* SPR specific to PowerPC 401 implementation */
1917
static void gen_spr_401 (CPUPPCState *env)
1918
{
1919
    /* Debug interface */
1920
    /* XXX : not implemented */
1921
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1922
                 SPR_NOACCESS, SPR_NOACCESS,
1923
                 &spr_read_generic, &spr_write_40x_dbcr0,
1924
                 0x00000000);
1925
    /* XXX : not implemented */
1926
    spr_register(env, SPR_40x_DBSR, "DBSR",
1927
                 SPR_NOACCESS, SPR_NOACCESS,
1928
                 &spr_read_generic, &spr_write_clear,
1929
                 /* Last reset was system reset */
1930
                 0x00000300);
1931
    /* XXX : not implemented */
1932
    spr_register(env, SPR_40x_DAC1, "DAC",
1933
                 SPR_NOACCESS, SPR_NOACCESS,
1934
                 &spr_read_generic, &spr_write_generic,
1935
                 0x00000000);
1936
    /* XXX : not implemented */
1937
    spr_register(env, SPR_40x_IAC1, "IAC",
1938
                 SPR_NOACCESS, SPR_NOACCESS,
1939
                 &spr_read_generic, &spr_write_generic,
1940
                 0x00000000);
1941
    /* Storage control */
1942
    spr_register(env, SPR_405_SLER, "SLER",
1943
                 SPR_NOACCESS, SPR_NOACCESS,
1944
                 &spr_read_generic, &spr_write_40x_sler,
1945
                 0x00000000);
1946
}
1947

    
1948
static void gen_spr_401x2 (CPUPPCState *env)
1949
{
1950
    gen_spr_401(env);
1951
    spr_register(env, SPR_40x_PID, "PID",
1952
                 SPR_NOACCESS, SPR_NOACCESS,
1953
                 &spr_read_generic, &spr_write_generic,
1954
                 0x00000000);
1955
    spr_register(env, SPR_40x_ZPR, "ZPR",
1956
                 SPR_NOACCESS, SPR_NOACCESS,
1957
                 &spr_read_generic, &spr_write_generic,
1958
                 0x00000000);
1959
}
1960

    
1961
/* SPR specific to PowerPC 403 implementation */
1962
static void gen_spr_403 (CPUPPCState *env)
1963
{
1964
    /* Debug interface */
1965
    /* XXX : not implemented */
1966
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1967
                 SPR_NOACCESS, SPR_NOACCESS,
1968
                 &spr_read_generic, &spr_write_40x_dbcr0,
1969
                 0x00000000);
1970
    /* XXX : not implemented */
1971
    spr_register(env, SPR_40x_DBSR, "DBSR",
1972
                 SPR_NOACCESS, SPR_NOACCESS,
1973
                 &spr_read_generic, &spr_write_clear,
1974
                 /* Last reset was system reset */
1975
                 0x00000300);
1976
    /* XXX : not implemented */
1977
    spr_register(env, SPR_40x_DAC1, "DAC1",
1978
                 SPR_NOACCESS, SPR_NOACCESS,
1979
                 &spr_read_generic, &spr_write_generic,
1980
                 0x00000000);
1981
    spr_register(env, SPR_40x_DAC2, "DAC2",
1982
                 SPR_NOACCESS, SPR_NOACCESS,
1983
                 &spr_read_generic, &spr_write_generic,
1984
                 0x00000000);
1985
    /* XXX : not implemented */
1986
    spr_register(env, SPR_40x_IAC1, "IAC1",
1987
                 SPR_NOACCESS, SPR_NOACCESS,
1988
                 &spr_read_generic, &spr_write_generic,
1989
                 0x00000000);
1990
    spr_register(env, SPR_40x_IAC2, "IAC2",
1991
                 SPR_NOACCESS, SPR_NOACCESS,
1992
                 &spr_read_generic, &spr_write_generic,
1993
                 0x00000000);
1994
}
1995

    
1996
static void gen_spr_403_real (CPUPPCState *env)
1997
{
1998
    spr_register(env, SPR_403_PBL1,  "PBL1",
1999
                 SPR_NOACCESS, SPR_NOACCESS,
2000
                 &spr_read_403_pbr, &spr_write_403_pbr,
2001
                 0x00000000);
2002
    spr_register(env, SPR_403_PBU1,  "PBU1",
2003
                 SPR_NOACCESS, SPR_NOACCESS,
2004
                 &spr_read_403_pbr, &spr_write_403_pbr,
2005
                 0x00000000);
2006
    spr_register(env, SPR_403_PBL2,  "PBL2",
2007
                 SPR_NOACCESS, SPR_NOACCESS,
2008
                 &spr_read_403_pbr, &spr_write_403_pbr,
2009
                 0x00000000);
2010
    spr_register(env, SPR_403_PBU2,  "PBU2",
2011
                 SPR_NOACCESS, SPR_NOACCESS,
2012
                 &spr_read_403_pbr, &spr_write_403_pbr,
2013
                 0x00000000);
2014
}
2015

    
2016
static void gen_spr_403_mmu (CPUPPCState *env)
2017
{
2018
    /* MMU */
2019
    spr_register(env, SPR_40x_PID, "PID",
2020
                 SPR_NOACCESS, SPR_NOACCESS,
2021
                 &spr_read_generic, &spr_write_generic,
2022
                 0x00000000);
2023
    spr_register(env, SPR_40x_ZPR, "ZPR",
2024
                 SPR_NOACCESS, SPR_NOACCESS,
2025
                 &spr_read_generic, &spr_write_generic,
2026
                 0x00000000);
2027
}
2028

    
2029
/* SPR specific to PowerPC compression coprocessor extension */
2030
static void gen_spr_compress (CPUPPCState *env)
2031
{
2032
    spr_register(env, SPR_401_SKR, "SKR",
2033
                 SPR_NOACCESS, SPR_NOACCESS,
2034
                 &spr_read_generic, &spr_write_generic,
2035
                 0x00000000);
2036
}
2037

    
2038
#if defined (TARGET_PPC64)
2039
#if defined (TODO)
2040
/* SPR specific to PowerPC 620 */
2041
static void gen_spr_620 (CPUPPCState *env)
2042
{
2043
    spr_register(env, SPR_620_PMR0, "PMR0",
2044
                 SPR_NOACCESS, SPR_NOACCESS,
2045
                 &spr_read_generic, &spr_write_generic,
2046
                 0x00000000);
2047
    spr_register(env, SPR_620_PMR1, "PMR1",
2048
                 SPR_NOACCESS, SPR_NOACCESS,
2049
                 &spr_read_generic, &spr_write_generic,
2050
                 0x00000000);
2051
    spr_register(env, SPR_620_PMR2, "PMR2",
2052
                 SPR_NOACCESS, SPR_NOACCESS,
2053
                 &spr_read_generic, &spr_write_generic,
2054
                 0x00000000);
2055
    spr_register(env, SPR_620_PMR3, "PMR3",
2056
                 SPR_NOACCESS, SPR_NOACCESS,
2057
                 &spr_read_generic, &spr_write_generic,
2058
                 0x00000000);
2059
    spr_register(env, SPR_620_PMR4, "PMR4",
2060
                 SPR_NOACCESS, SPR_NOACCESS,
2061
                 &spr_read_generic, &spr_write_generic,
2062
                 0x00000000);
2063
    spr_register(env, SPR_620_PMR5, "PMR5",
2064
                 SPR_NOACCESS, SPR_NOACCESS,
2065
                 &spr_read_generic, &spr_write_generic,
2066
                 0x00000000);
2067
    spr_register(env, SPR_620_PMR6, "PMR6",
2068
                 SPR_NOACCESS, SPR_NOACCESS,
2069
                 &spr_read_generic, &spr_write_generic,
2070
                 0x00000000);
2071
    spr_register(env, SPR_620_PMR7, "PMR7",
2072
                 SPR_NOACCESS, SPR_NOACCESS,
2073
                 &spr_read_generic, &spr_write_generic,
2074
                 0x00000000);
2075
    spr_register(env, SPR_620_PMR8, "PMR8",
2076
                 SPR_NOACCESS, SPR_NOACCESS,
2077
                 &spr_read_generic, &spr_write_generic,
2078
                 0x00000000);
2079
    spr_register(env, SPR_620_PMR9, "PMR9",
2080
                 SPR_NOACCESS, SPR_NOACCESS,
2081
                 &spr_read_generic, &spr_write_generic,
2082
                 0x00000000);
2083
    spr_register(env, SPR_620_PMRA, "PMR10",
2084
                 SPR_NOACCESS, SPR_NOACCESS,
2085
                 &spr_read_generic, &spr_write_generic,
2086
                 0x00000000);
2087
    spr_register(env, SPR_620_PMRB, "PMR11",
2088
                 SPR_NOACCESS, SPR_NOACCESS,
2089
                 &spr_read_generic, &spr_write_generic,
2090
                 0x00000000);
2091
    spr_register(env, SPR_620_PMRC, "PMR12",
2092
                 SPR_NOACCESS, SPR_NOACCESS,
2093
                 &spr_read_generic, &spr_write_generic,
2094
                 0x00000000);
2095
    spr_register(env, SPR_620_PMRD, "PMR13",
2096
                 SPR_NOACCESS, SPR_NOACCESS,
2097
                 &spr_read_generic, &spr_write_generic,
2098
                 0x00000000);
2099
    spr_register(env, SPR_620_PMRE, "PMR14",
2100
                 SPR_NOACCESS, SPR_NOACCESS,
2101
                 &spr_read_generic, &spr_write_generic,
2102
                 0x00000000);
2103
    spr_register(env, SPR_620_PMRF, "PMR15",
2104
                 SPR_NOACCESS, SPR_NOACCESS,
2105
                 &spr_read_generic, &spr_write_generic,
2106
                 0x00000000);
2107
    spr_register(env, SPR_620_HID8, "HID8",
2108
                 SPR_NOACCESS, SPR_NOACCESS,
2109
                 &spr_read_generic, &spr_write_generic,
2110
                 0x00000000);
2111
    spr_register(env, SPR_620_HID9, "HID9",
2112
                 SPR_NOACCESS, SPR_NOACCESS,
2113
                 &spr_read_generic, &spr_write_generic,
2114
                 0x00000000);
2115
}
2116
#endif
2117
#endif /* defined (TARGET_PPC64) */
2118

    
2119
// XXX: TODO
2120
/*
2121
 * AMR     => SPR 29 (Power 2.04)
2122
 * CTRL    => SPR 136 (Power 2.04)
2123
 * CTRL    => SPR 152 (Power 2.04)
2124
 * SCOMC   => SPR 276 (64 bits ?)
2125
 * SCOMD   => SPR 277 (64 bits ?)
2126
 * ASR     => SPR 280 (64 bits)
2127
 * TBU40   => SPR 286 (Power 2.04 hypv)
2128
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2129
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2130
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2131
 * HDAR    => SPR 307 (Power 2.04 hypv)
2132
 * PURR    => SPR 309 (Power 2.04 hypv)
2133
 * HDEC    => SPR 310 (Power 2.04 hypv)
2134
 * HIOR    => SPR 311 (hypv)
2135
 * RMOR    => SPR 312 (970)
2136
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2137
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2138
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2139
 * LPCR    => SPR 316 (970)
2140
 * LPIDR   => SPR 317 (970)
2141
 * SPEFSCR => SPR 512 (Power 2.04 emb)
2142
 * ATBL    => SPR 526 (Power 2.04 emb)
2143
 * ATBU    => SPR 527 (Power 2.04 emb)
2144
 * EPR     => SPR 702 (Power 2.04 emb)
2145
 * perf    => 768-783 (Power 2.04)
2146
 * perf    => 784-799 (Power 2.04)
2147
 * PPR     => SPR 896 (Power 2.04)
2148
 * EPLC    => SPR 947 (Power 2.04 emb)
2149
 * EPSC    => SPR 948 (Power 2.04 emb)
2150
 * DABRX   => 1015    (Power 2.04 hypv)
2151
 * FPECR   => SPR 1022 (?)
2152
 * ... and more (thermal management, performance counters, ...)
2153
 */
2154

    
2155
/*****************************************************************************/
2156
/* Exception vectors models                                                  */
2157
static void init_excp_4xx_real (CPUPPCState *env)
2158
{
2159
#if !defined(CONFIG_USER_ONLY)
2160
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2161
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2162
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2163
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2164
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2165
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2166
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2167
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2168
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2169
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2170
#endif
2171
}
2172

    
2173
static void init_excp_4xx_softmmu (CPUPPCState *env)
2174
{
2175
#if !defined(CONFIG_USER_ONLY)
2176
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2177
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2178
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2179
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2180
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2181
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2182
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2183
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2184
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2185
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2186
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2187
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2188
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2189
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2190
#endif
2191
}
2192

    
2193
static void init_excp_BookE (CPUPPCState *env)
2194
{
2195
#if !defined(CONFIG_USER_ONLY)
2196
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2197
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2198
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2199
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2200
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2201
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2202
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2203
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2204
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2205
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2206
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2207
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2208
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2209
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2210
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2211
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2212
    env->excp_prefix = 0x00000000;
2213
    env->ivor_mask = 0x0000FFE0;
2214
    env->ivpr_mask = 0xFFFF0000;
2215
#endif
2216
}
2217

    
2218
static void init_excp_601 (CPUPPCState *env)
2219
{
2220
#if !defined(CONFIG_USER_ONLY)
2221
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2222
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2223
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2224
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2225
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2226
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2227
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2228
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2229
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2230
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2231
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2232
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2233
    env->excp_prefix = 0xFFF00000;
2234
#endif
2235
}
2236

    
2237
static void init_excp_602 (CPUPPCState *env)
2238
{
2239
#if !defined(CONFIG_USER_ONLY)
2240
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2241
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2242
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2243
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2244
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2245
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2246
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2247
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2248
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2249
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2250
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2251
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2252
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2253
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2254
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2255
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2256
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2257
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2258
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2259
    env->excp_prefix = 0xFFF00000;
2260
#endif
2261
}
2262

    
2263
static void init_excp_603 (CPUPPCState *env)
2264
{
2265
#if !defined(CONFIG_USER_ONLY)
2266
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2267
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2268
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2269
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2270
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2271
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2272
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2273
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2274
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2275
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2276
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2277
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2278
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2279
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2280
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2281
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2282
#endif
2283
}
2284

    
2285
static void init_excp_G2 (CPUPPCState *env)
2286
{
2287
#if !defined(CONFIG_USER_ONLY)
2288
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2289
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2290
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2291
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2292
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2293
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2294
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2295
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2296
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2297
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2298
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2299
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2300
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2301
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2302
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2303
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2304
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2305
#endif
2306
}
2307

    
2308
static void init_excp_604 (CPUPPCState *env)
2309
{
2310
#if !defined(CONFIG_USER_ONLY)
2311
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2312
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2313
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2314
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2315
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2317
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2318
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2319
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2320
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2321
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2322
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2323
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2324
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2325
#endif
2326
}
2327

    
2328
#if defined (TODO)
2329
static void init_excp_620 (CPUPPCState *env)
2330
{
2331
#if !defined(CONFIG_USER_ONLY)
2332
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2333
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2334
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2335
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2336
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2337
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2338
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2339
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2340
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2341
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2342
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2343
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2344
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2345
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2346
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2347
#endif
2348
}
2349
#endif /* defined (TODO) */
2350

    
2351
static void init_excp_7x0 (CPUPPCState *env)
2352
{
2353
#if !defined(CONFIG_USER_ONLY)
2354
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2355
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2356
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2357
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2358
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2359
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2360
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2361
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2362
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2363
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2364
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2365
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2366
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2367
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2368
#endif
2369
}
2370

    
2371
static void init_excp_750FX (CPUPPCState *env)
2372
{
2373
#if !defined(CONFIG_USER_ONLY)
2374
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2375
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2376
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2377
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2378
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2379
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2380
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2381
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2382
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2383
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2384
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2385
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2386
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2387
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2388
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2389
#endif
2390
}
2391

    
2392
static void init_excp_7400 (CPUPPCState *env)
2393
{
2394
#if !defined(CONFIG_USER_ONLY)
2395
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2396
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2397
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2398
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2399
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2400
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2401
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2402
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2403
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2404
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2405
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2406
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2407
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2408
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2409
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2410
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2411
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2412
#endif
2413
}
2414

    
2415
#if defined (TODO)
2416
static void init_excp_7450 (CPUPPCState *env)
2417
{
2418
#if !defined(CONFIG_USER_ONLY)
2419
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2420
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2421
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2422
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2423
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2424
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2425
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2426
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2427
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2428
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2429
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2430
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2431
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2432
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2433
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2434
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2435
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2436
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2437
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2438
#endif
2439
}
2440
#endif /* defined (TODO) */
2441

    
2442
#if defined (TARGET_PPC64)
2443
static void init_excp_970 (CPUPPCState *env)
2444
{
2445
#if !defined(CONFIG_USER_ONLY)
2446
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2447
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2448
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2449
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2450
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2451
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2452
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2453
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2454
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2455
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2456
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2457
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2458
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2459
#endif
2460
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2461
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2462
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2463
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2464
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2465
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2466
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2467
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2468
#endif
2469
}
2470
#endif
2471

    
2472
/*****************************************************************************/
2473
/* PowerPC implementations definitions                                       */
2474

    
2475
/* PowerPC 40x instruction set                                               */
2476
#define POWERPC_INSNS_EMB    (PPC_INSNS_BASE | PPC_EMB_COMMON)
2477

    
2478
/* PowerPC 401                                                               */
2479
#define POWERPC_INSNS_401    (POWERPC_INSNS_EMB |                             \
2480
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2481
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2482
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
2483
#define POWERPC_MMU_401      (POWERPC_MMU_REAL_4xx)
2484
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
2485
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
2486
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
2487

    
2488
static void init_proc_401 (CPUPPCState *env)
2489
{
2490
    gen_spr_40x(env);
2491
    gen_spr_401_403(env);
2492
    gen_spr_401(env);
2493
    /* Bus access control */
2494
    spr_register(env, SPR_40x_SGR, "SGR",
2495
                 SPR_NOACCESS, SPR_NOACCESS,
2496
                 &spr_read_generic, &spr_write_generic,
2497
                 0xFFFFFFFF);
2498
    /* XXX : not implemented */
2499
    spr_register(env, SPR_40x_DCWR, "DCWR",
2500
                 SPR_NOACCESS, SPR_NOACCESS,
2501
                 &spr_read_generic, &spr_write_generic,
2502
                 0x00000000);
2503
    init_excp_4xx_real(env);
2504
    /* XXX: TODO: allocate internal IRQ controller */
2505
}
2506

    
2507
/* PowerPC 401x2                                                             */
2508
#define POWERPC_INSNS_401x2  (POWERPC_INSNS_EMB |                             \
2509
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2510
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2511
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2512
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2513
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
2514
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
2515
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
2516
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
2517
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
2518

    
2519
static void init_proc_401x2 (CPUPPCState *env)
2520
{
2521
    gen_spr_40x(env);
2522
    gen_spr_401_403(env);
2523
    gen_spr_401x2(env);
2524
    gen_spr_compress(env);
2525
    /* Bus access control */
2526
    spr_register(env, SPR_40x_SGR, "SGR",
2527
                 SPR_NOACCESS, SPR_NOACCESS,
2528
                 &spr_read_generic, &spr_write_generic,
2529
                 0xFFFFFFFF);
2530
    /* XXX : not implemented */
2531
    spr_register(env, SPR_40x_DCWR, "DCWR",
2532
                 SPR_NOACCESS, SPR_NOACCESS,
2533
                 &spr_read_generic, &spr_write_generic,
2534
                 0x00000000);
2535
    /* Memory management */
2536
    env->nb_tlb = 64;
2537
    env->nb_ways = 1;
2538
    env->id_tlbs = 0;
2539
    init_excp_4xx_softmmu(env);
2540
    /* XXX: TODO: allocate internal IRQ controller */
2541
}
2542

    
2543
/* PowerPC 401x3                                                             */
2544
#if defined(TODO)
2545
#define POWERPC_INSNS_401x3  (POWERPC_INSNS_EMB |                             \
2546
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2547
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2548
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2549
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2550
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
2551
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
2552
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
2553
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
2554
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
2555

    
2556
static void init_proc_401x3 (CPUPPCState *env)
2557
{
2558
    init_excp_4xx_softmmu(env);
2559
}
2560
#endif /* TODO */
2561

    
2562
/* IOP480                                                                    */
2563
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB |                             \
2564
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2565
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2566
                              PPC_CACHE_DCBA |                                \
2567
                              PPC_4xx_COMMON | PPC_40x_EXCP |  PPC_40x_ICBT)
2568
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
2569
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
2570
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
2571
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2572
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
2573

    
2574
static void init_proc_IOP480 (CPUPPCState *env)
2575
{
2576
    gen_spr_40x(env);
2577
    gen_spr_401_403(env);
2578
    gen_spr_401x2(env);
2579
    gen_spr_compress(env);
2580
    /* Bus access control */
2581
    spr_register(env, SPR_40x_SGR, "SGR",
2582
                 SPR_NOACCESS, SPR_NOACCESS,
2583
                 &spr_read_generic, &spr_write_generic,
2584
                 0xFFFFFFFF);
2585
    /* XXX : not implemented */
2586
    spr_register(env, SPR_40x_DCWR, "DCWR",
2587
                 SPR_NOACCESS, SPR_NOACCESS,
2588
                 &spr_read_generic, &spr_write_generic,
2589
                 0x00000000);
2590
    /* Memory management */
2591
    env->nb_tlb = 64;
2592
    env->nb_ways = 1;
2593
    env->id_tlbs = 0;
2594
    init_excp_4xx_softmmu(env);
2595
    /* XXX: TODO: allocate internal IRQ controller */
2596
}
2597

    
2598
/* PowerPC 403                                                               */
2599
#define POWERPC_INSNS_403    (POWERPC_INSNS_EMB |                             \
2600
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2601
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2602
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2603
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
2604
#define POWERPC_MMU_403      (POWERPC_MMU_REAL_4xx)
2605
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
2606
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
2607
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
2608

    
2609
static void init_proc_403 (CPUPPCState *env)
2610
{
2611
    gen_spr_40x(env);
2612
    gen_spr_401_403(env);
2613
    gen_spr_403(env);
2614
    gen_spr_403_real(env);
2615
    init_excp_4xx_real(env);
2616
    /* XXX: TODO: allocate internal IRQ controller */
2617
}
2618

    
2619
/* PowerPC 403 GCX                                                           */
2620
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB |                             \
2621
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2622
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2623
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2624
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
2625
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
2626
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
2627
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2628
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
2629

    
2630
static void init_proc_403GCX (CPUPPCState *env)
2631
{
2632
    gen_spr_40x(env);
2633
    gen_spr_401_403(env);
2634
    gen_spr_403(env);
2635
    gen_spr_403_real(env);
2636
    gen_spr_403_mmu(env);
2637
    /* Bus access control */
2638
    spr_register(env, SPR_40x_SGR, "SGR",
2639
                 SPR_NOACCESS, SPR_NOACCESS,
2640
                 &spr_read_generic, &spr_write_generic,
2641
                 0xFFFFFFFF);
2642
    /* XXX : not implemented */
2643
    spr_register(env, SPR_40x_DCWR, "DCWR",
2644
                 SPR_NOACCESS, SPR_NOACCESS,
2645
                 &spr_read_generic, &spr_write_generic,
2646
                 0x00000000);
2647
    /* Memory management */
2648
    env->nb_tlb = 64;
2649
    env->nb_ways = 1;
2650
    env->id_tlbs = 0;
2651
    init_excp_4xx_softmmu(env);
2652
    /* XXX: TODO: allocate internal IRQ controller */
2653
}
2654

    
2655
/* PowerPC 405                                                               */
2656
#define POWERPC_INSNS_405    (POWERPC_INSNS_EMB | PPC_MFTB |                  \
2657
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2658
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2659
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT |  \
2660
                              PPC_405_MAC)
2661
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
2662
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
2663
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
2664
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
2665
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
2666

    
2667
static void init_proc_405 (CPUPPCState *env)
2668
{
2669
    /* Time base */
2670
    gen_tbl(env);
2671
    gen_spr_40x(env);
2672
    gen_spr_405(env);
2673
    /* Bus access control */
2674
    spr_register(env, SPR_40x_SGR, "SGR",
2675
                 SPR_NOACCESS, SPR_NOACCESS,
2676
                 &spr_read_generic, &spr_write_generic,
2677
                 0xFFFFFFFF);
2678
    /* XXX : not implemented */
2679
    spr_register(env, SPR_40x_DCWR, "DCWR",
2680
                 SPR_NOACCESS, SPR_NOACCESS,
2681
                 &spr_read_generic, &spr_write_generic,
2682
                 0x00000000);
2683
    /* Memory management */
2684
    env->nb_tlb = 64;
2685
    env->nb_ways = 1;
2686
    env->id_tlbs = 0;
2687
    init_excp_4xx_softmmu(env);
2688
    /* Allocate hardware IRQ controller */
2689
    ppc405_irq_init(env);
2690
}
2691

    
2692
/* PowerPC 440 EP                                                            */
2693
#define POWERPC_INSNS_440EP  (POWERPC_INSNS_EMB |                             \
2694
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2695
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2696
                              PPC_440_SPEC | PPC_RFMCI)
2697
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
2698
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
2699
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
2700
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
2701
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
2702

    
2703
static void init_proc_440EP (CPUPPCState *env)
2704
{
2705
    /* Time base */
2706
    gen_tbl(env);
2707
    gen_spr_BookE(env);
2708
    gen_spr_440(env);
2709
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2710
                 SPR_NOACCESS, SPR_NOACCESS,
2711
                 &spr_read_generic, &spr_write_generic,
2712
                 0x00000000);
2713
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2714
                 SPR_NOACCESS, SPR_NOACCESS,
2715
                 &spr_read_generic, &spr_write_generic,
2716
                 0x00000000);
2717
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2718
                 SPR_NOACCESS, SPR_NOACCESS,
2719
                 &spr_read_generic, &spr_write_generic,
2720
                 0x00000000);
2721
    spr_register(env, SPR_440_CCR1, "CCR1",
2722
                 SPR_NOACCESS, SPR_NOACCESS,
2723
                 &spr_read_generic, &spr_write_generic,
2724
                 0x00000000);
2725
    /* Memory management */
2726
    env->nb_tlb = 64;
2727
    env->nb_ways = 1;
2728
    env->id_tlbs = 0;
2729
    init_excp_BookE(env);
2730
    /* XXX: TODO: allocate internal IRQ controller */
2731
}
2732

    
2733
/* PowerPC 440 GP                                                            */
2734
#define POWERPC_INSNS_440GP  (POWERPC_INSNS_EMB |                             \
2735
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2736
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2737
                              PPC_405_MAC | PPC_440_SPEC)
2738
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
2739
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
2740
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
2741
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
2742
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
2743

    
2744
static void init_proc_440GP (CPUPPCState *env)
2745
{
2746
    /* Time base */
2747
    gen_tbl(env);
2748
    gen_spr_BookE(env);
2749
    gen_spr_440(env);
2750
    /* Memory management */
2751
    env->nb_tlb = 64;
2752
    env->nb_ways = 1;
2753
    env->id_tlbs = 0;
2754
    init_excp_BookE(env);
2755
    /* XXX: TODO: allocate internal IRQ controller */
2756
}
2757

    
2758
/* PowerPC 440x4                                                             */
2759
#if defined(TODO)
2760
#define POWERPC_INSNS_440x4  (POWERPC_INSNS_EMB |                             \
2761
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2762
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2763
                              PPC_440_SPEC)
2764
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
2765
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
2766
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
2767
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
2768
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
2769

    
2770
static void init_proc_440x4 (CPUPPCState *env)
2771
{
2772
    /* Time base */
2773
    gen_tbl(env);
2774
    gen_spr_BookE(env);
2775
    gen_spr_440(env);
2776
    /* Memory management */
2777
    env->nb_tlb = 64;
2778
    env->nb_ways = 1;
2779
    env->id_tlbs = 0;
2780
    init_excp_BookE(env);
2781
    /* XXX: TODO: allocate internal IRQ controller */
2782
}
2783
#endif /* TODO */
2784

    
2785
/* PowerPC 440x5                                                             */
2786
#define POWERPC_INSNS_440x5  (POWERPC_INSNS_EMB |                             \
2787
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2788
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2789
                              PPC_440_SPEC | PPC_RFMCI)
2790
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
2791
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
2792
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
2793
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
2794
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
2795

    
2796
static void init_proc_440x5 (CPUPPCState *env)
2797
{
2798
    /* Time base */
2799
    gen_tbl(env);
2800
    gen_spr_BookE(env);
2801
    gen_spr_440(env);
2802
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2803
                 SPR_NOACCESS, SPR_NOACCESS,
2804
                 &spr_read_generic, &spr_write_generic,
2805
                 0x00000000);
2806
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2807
                 SPR_NOACCESS, SPR_NOACCESS,
2808
                 &spr_read_generic, &spr_write_generic,
2809
                 0x00000000);
2810
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2811
                 SPR_NOACCESS, SPR_NOACCESS,
2812
                 &spr_read_generic, &spr_write_generic,
2813
                 0x00000000);
2814
    spr_register(env, SPR_440_CCR1, "CCR1",
2815
                 SPR_NOACCESS, SPR_NOACCESS,
2816
                 &spr_read_generic, &spr_write_generic,
2817
                 0x00000000);
2818
    /* Memory management */
2819
    env->nb_tlb = 64;
2820
    env->nb_ways = 1;
2821
    env->id_tlbs = 0;
2822
    init_excp_BookE(env);
2823
    /* XXX: TODO: allocate internal IRQ controller */
2824
}
2825

    
2826
/* PowerPC 460 (guessed)                                                     */
2827
#if defined(TODO)
2828
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
2829
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2830
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2831
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2832
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
2833
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
2834
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
2835
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
2836
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
2837

    
2838
static void init_proc_460 (CPUPPCState *env)
2839
{
2840
    /* Time base */
2841
    gen_tbl(env);
2842
    gen_spr_BookE(env);
2843
    gen_spr_440(env);
2844
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2845
                 SPR_NOACCESS, SPR_NOACCESS,
2846
                 &spr_read_generic, &spr_write_generic,
2847
                 0x00000000);
2848
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2849
                 SPR_NOACCESS, SPR_NOACCESS,
2850
                 &spr_read_generic, &spr_write_generic,
2851
                 0x00000000);
2852
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2853
                 SPR_NOACCESS, SPR_NOACCESS,
2854
                 &spr_read_generic, &spr_write_generic,
2855
                 0x00000000);
2856
    spr_register(env, SPR_440_CCR1, "CCR1",
2857
                 SPR_NOACCESS, SPR_NOACCESS,
2858
                 &spr_read_generic, &spr_write_generic,
2859
                 0x00000000);
2860
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2861
                 &spr_read_generic, &spr_write_generic,
2862
                 &spr_read_generic, &spr_write_generic,
2863
                 0x00000000);
2864
    /* Memory management */
2865
    env->nb_tlb = 64;
2866
    env->nb_ways = 1;
2867
    env->id_tlbs = 0;
2868
    init_excp_BookE(env);
2869
    /* XXX: TODO: allocate internal IRQ controller */
2870
}
2871
#endif /* TODO */
2872

    
2873
/* PowerPC 460F (guessed)                                                    */
2874
#if defined(TODO)
2875
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
2876
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2877
                              PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES |  \
2878
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |            \
2879
                              PPC_FLOAT_STFIWX |                              \
2880
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2881
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2882
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
2883
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
2884
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
2885
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
2886
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
2887

    
2888
static void init_proc_460F (CPUPPCState *env)
2889
{
2890
    /* Time base */
2891
    gen_tbl(env);
2892
    gen_spr_BookE(env);
2893
    gen_spr_440(env);
2894
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2895
                 SPR_NOACCESS, SPR_NOACCESS,
2896
                 &spr_read_generic, &spr_write_generic,
2897
                 0x00000000);
2898
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2899
                 SPR_NOACCESS, SPR_NOACCESS,
2900
                 &spr_read_generic, &spr_write_generic,
2901
                 0x00000000);
2902
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2903
                 SPR_NOACCESS, SPR_NOACCESS,
2904
                 &spr_read_generic, &spr_write_generic,
2905
                 0x00000000);
2906
    spr_register(env, SPR_440_CCR1, "CCR1",
2907
                 SPR_NOACCESS, SPR_NOACCESS,
2908
                 &spr_read_generic, &spr_write_generic,
2909
                 0x00000000);
2910
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2911
                 &spr_read_generic, &spr_write_generic,
2912
                 &spr_read_generic, &spr_write_generic,
2913
                 0x00000000);
2914
    /* Memory management */
2915
    env->nb_tlb = 64;
2916
    env->nb_ways = 1;
2917
    env->id_tlbs = 0;
2918
    init_excp_BookE(env);
2919
    /* XXX: TODO: allocate internal IRQ controller */
2920
}
2921
#endif /* TODO */
2922

    
2923
/* Generic BookE PowerPC                                                     */
2924
#if defined(TODO)
2925
#define POWERPC_INSNS_BookE  (POWERPC_INSNS_EMB |                             \
2926
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
2927
                              PPC_CACHE_DCBA |                                \
2928
                              PPC_FLOAT | PPC_FLOAT_FSQRT |                   \
2929
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
2930
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIW |              \
2931
                              PPC_BOOKE)
2932
#define POWERPC_MSRM_BookE   (0x000000000006D630ULL)
2933
#define POWERPC_MMU_BookE    (POWERPC_MMU_BOOKE)
2934
#define POWERPC_EXCP_BookE   (POWERPC_EXCP_BOOKE)
2935
#define POWERPC_INPUT_BookE  (PPC_FLAGS_INPUT_BookE)
2936
#define POWERPC_BFDM_BookE   (bfd_mach_ppc_403)
2937

    
2938
static void init_proc_BookE (CPUPPCState *env)
2939
{
2940
    init_excp_BookE(env);
2941
}
2942
#endif /* TODO */
2943

    
2944
/* e200 core                                                                 */
2945
#if defined(TODO)
2946
#endif /* TODO */
2947

    
2948
/* e300 core                                                                 */
2949
#if defined(TODO)
2950
#endif /* TODO */
2951

    
2952
/* e500 core                                                                 */
2953
#if defined(TODO)
2954
#define POWERPC_INSNS_e500   (POWERPC_INSNS_EMB |                             \
2955
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
2956
                              PPC_CACHE_DCBA |                                \
2957
                              PPC_BOOKE | PPC_E500_VECTOR)
2958
#define POWERPC_MMU_e500     (POWERPC_MMU_SOFT_4xx)
2959
#define POWERPC_EXCP_e500    (POWERPC_EXCP_40x)
2960
#define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
2961
#define POWERPC_BFDM_e500    (bfd_mach_ppc_403)
2962

    
2963
static void init_proc_e500 (CPUPPCState *env)
2964
{
2965
    /* Time base */
2966
    gen_tbl(env);
2967
    gen_spr_BookE(env);
2968
    /* Memory management */
2969
    gen_spr_BookE_FSL(env);
2970
    env->nb_tlb = 64;
2971
    env->nb_ways = 1;
2972
    env->id_tlbs = 0;
2973
    init_excp_BookE(env);
2974
    /* XXX: TODO: allocate internal IRQ controller */
2975
}
2976
#endif /* TODO */
2977

    
2978
/* e600 core                                                                 */
2979
#if defined(TODO)
2980
#endif /* TODO */
2981

    
2982
/* Non-embedded PowerPC                                                      */
2983
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC                    */
2984
#define POWERPC_INSNS_6xx    (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |     \
2985
                              PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
2986
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602      */
2987
#define POWERPC_INSNS_WORKS  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |           \
2988
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
2989
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
2990
                              PPC_MEM_TLBSYNC | PPC_MFTB)
2991

    
2992
/* POWER : same as 601, without mfmsr, mfsr                                  */
2993
#if defined(TODO)
2994
#define POWERPC_INSNS_POWER  (XXX_TODO)
2995
/* POWER RSC (from RAD6000) */
2996
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
2997
#endif /* TODO */
2998

    
2999
/* PowerPC 601                                                               */
3000
#define POWERPC_INSNS_601    (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
3001
#define POWERPC_MSRM_601     (0x000000000000FE70ULL)
3002
//#define POWERPC_MMU_601      (POWERPC_MMU_601)
3003
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
3004
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
3005
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
3006

    
3007
static void init_proc_601 (CPUPPCState *env)
3008
{
3009
    gen_spr_ne_601(env);
3010
    gen_spr_601(env);
3011
    /* Hardware implementation registers */
3012
    /* XXX : not implemented */
3013
    spr_register(env, SPR_HID0, "HID0",
3014
                 SPR_NOACCESS, SPR_NOACCESS,
3015
                 &spr_read_generic, &spr_write_generic,
3016
                 0x00000000);
3017
    /* XXX : not implemented */
3018
    spr_register(env, SPR_HID1, "HID1",
3019
                 SPR_NOACCESS, SPR_NOACCESS,
3020
                 &spr_read_generic, &spr_write_generic,
3021
                 0x00000000);
3022
    /* XXX : not implemented */
3023
    spr_register(env, SPR_601_HID2, "HID2",
3024
                 SPR_NOACCESS, SPR_NOACCESS,
3025
                 &spr_read_generic, &spr_write_generic,
3026
                 0x00000000);
3027
    /* XXX : not implemented */
3028
    spr_register(env, SPR_601_HID5, "HID5",
3029
                 SPR_NOACCESS, SPR_NOACCESS,
3030
                 &spr_read_generic, &spr_write_generic,
3031
                 0x00000000);
3032
    /* XXX : not implemented */
3033
    spr_register(env, SPR_601_HID15, "HID15",
3034
                 SPR_NOACCESS, SPR_NOACCESS,
3035
                 &spr_read_generic, &spr_write_generic,
3036
                 0x00000000);
3037
    /* Memory management */
3038
    env->nb_tlb = 64;
3039
    env->nb_ways = 2;
3040
    env->id_tlbs = 0;
3041
    env->id_tlbs = 0;
3042
    init_excp_601(env);
3043
    /* XXX: TODO: allocate internal IRQ controller */
3044
}
3045

    
3046
/* PowerPC 602                                                               */
3047
#define POWERPC_INSNS_602    (POWERPC_INSNS_6xx | PPC_MFTB |                  \
3048
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3049
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3050
                              PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
3051
#define POWERPC_MSRM_602     (0x000000000033FF73ULL)
3052
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
3053
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
3054
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
3055
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
3056

    
3057
static void init_proc_602 (CPUPPCState *env)
3058
{
3059
    gen_spr_ne_601(env);
3060
    gen_spr_602(env);
3061
    /* Time base */
3062
    gen_tbl(env);
3063
    /* hardware implementation registers */
3064
    /* XXX : not implemented */
3065
    spr_register(env, SPR_HID0, "HID0",
3066
                 SPR_NOACCESS, SPR_NOACCESS,
3067
                 &spr_read_generic, &spr_write_generic,
3068
                 0x00000000);
3069
    /* XXX : not implemented */
3070
    spr_register(env, SPR_HID1, "HID1",
3071
                 SPR_NOACCESS, SPR_NOACCESS,
3072
                 &spr_read_generic, &spr_write_generic,
3073
                 0x00000000);
3074
    /* Memory management */
3075
    gen_low_BATs(env);
3076
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3077
    init_excp_602(env);
3078
    /* Allocate hardware IRQ controller */
3079
    ppc6xx_irq_init(env);
3080
}
3081

    
3082
/* PowerPC 603                                                               */
3083
#define POWERPC_INSNS_603    (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3084
#define POWERPC_MSRM_603     (0x000000000001FF73ULL)
3085
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
3086
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
3087
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
3088
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
3089

    
3090
static void init_proc_603 (CPUPPCState *env)
3091
{
3092
    gen_spr_ne_601(env);
3093
    gen_spr_603(env);
3094
    /* Time base */
3095
    gen_tbl(env);
3096
    /* hardware implementation registers */
3097
    /* XXX : not implemented */
3098
    spr_register(env, SPR_HID0, "HID0",
3099
                 SPR_NOACCESS, SPR_NOACCESS,
3100
                 &spr_read_generic, &spr_write_generic,
3101
                 0x00000000);
3102
    /* XXX : not implemented */
3103
    spr_register(env, SPR_HID1, "HID1",
3104
                 SPR_NOACCESS, SPR_NOACCESS,
3105
                 &spr_read_generic, &spr_write_generic,
3106
                 0x00000000);
3107
    /* Memory management */
3108
    gen_low_BATs(env);
3109
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3110
    init_excp_603(env);
3111
    /* Allocate hardware IRQ controller */
3112
    ppc6xx_irq_init(env);
3113
}
3114

    
3115
/* PowerPC 603e                                                              */
3116
#define POWERPC_INSNS_603E   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3117
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
3118
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
3119
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
3120
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
3121
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
3122

    
3123
static void init_proc_603E (CPUPPCState *env)
3124
{
3125
    gen_spr_ne_601(env);
3126
    gen_spr_603(env);
3127
    /* Time base */
3128
    gen_tbl(env);
3129
    /* hardware implementation registers */
3130
    /* XXX : not implemented */
3131
    spr_register(env, SPR_HID0, "HID0",
3132
                 SPR_NOACCESS, SPR_NOACCESS,
3133
                 &spr_read_generic, &spr_write_generic,
3134
                 0x00000000);
3135
    /* XXX : not implemented */
3136
    spr_register(env, SPR_HID1, "HID1",
3137
                 SPR_NOACCESS, SPR_NOACCESS,
3138
                 &spr_read_generic, &spr_write_generic,
3139
                 0x00000000);
3140
    /* XXX : not implemented */
3141
    spr_register(env, SPR_IABR, "IABR",
3142
                 SPR_NOACCESS, SPR_NOACCESS,
3143
                 &spr_read_generic, &spr_write_generic,
3144
                 0x00000000);
3145
    /* Memory management */
3146
    gen_low_BATs(env);
3147
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3148
    init_excp_603(env);
3149
    /* Allocate hardware IRQ controller */
3150
    ppc6xx_irq_init(env);
3151
}
3152

    
3153
/* PowerPC G2                                                                */
3154
#define POWERPC_INSNS_G2     (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3155
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3156
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3157
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3158
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3159
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3160

    
3161
static void init_proc_G2 (CPUPPCState *env)
3162
{
3163
    gen_spr_ne_601(env);
3164
    gen_spr_G2_755(env);
3165
    gen_spr_G2(env);
3166
    /* Time base */
3167
    gen_tbl(env);
3168
    /* Hardware implementation register */
3169
    /* XXX : not implemented */
3170
    spr_register(env, SPR_HID0, "HID0",
3171
                 SPR_NOACCESS, SPR_NOACCESS,
3172
                 &spr_read_generic, &spr_write_generic,
3173
                 0x00000000);
3174
    /* XXX : not implemented */
3175
    spr_register(env, SPR_HID1, "HID1",
3176
                 SPR_NOACCESS, SPR_NOACCESS,
3177
                 &spr_read_generic, &spr_write_generic,
3178
                 0x00000000);
3179
    /* XXX : not implemented */
3180
    spr_register(env, SPR_HID2, "HID2",
3181
                 SPR_NOACCESS, SPR_NOACCESS,
3182
                 &spr_read_generic, &spr_write_generic,
3183
                 0x00000000);
3184
    /* Memory management */
3185
    gen_low_BATs(env);
3186
    gen_high_BATs(env);
3187
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3188
    init_excp_G2(env);
3189
    /* Allocate hardware IRQ controller */
3190
    ppc6xx_irq_init(env);
3191
}
3192

    
3193
/* PowerPC G2LE                                                              */
3194
#define POWERPC_INSNS_G2LE   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3195
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3196
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3197
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3198
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3199
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3200

    
3201
static void init_proc_G2LE (CPUPPCState *env)
3202
{
3203
    gen_spr_ne_601(env);
3204
    gen_spr_G2_755(env);
3205
    gen_spr_G2(env);
3206
    /* Time base */
3207
    gen_tbl(env);
3208
    /* Hardware implementation register */
3209
    /* XXX : not implemented */
3210
    spr_register(env, SPR_HID0, "HID0",
3211
                 SPR_NOACCESS, SPR_NOACCESS,
3212
                 &spr_read_generic, &spr_write_generic,
3213
                 0x00000000);
3214
    /* XXX : not implemented */
3215
    spr_register(env, SPR_HID1, "HID1",
3216
                 SPR_NOACCESS, SPR_NOACCESS,
3217
                 &spr_read_generic, &spr_write_generic,
3218
                 0x00000000);
3219
    /* XXX : not implemented */
3220
    spr_register(env, SPR_HID2, "HID2",
3221
                 SPR_NOACCESS, SPR_NOACCESS,
3222
                 &spr_read_generic, &spr_write_generic,
3223
                 0x00000000);
3224
    /* Memory management */
3225
    gen_low_BATs(env);
3226
    gen_high_BATs(env);
3227
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3228
    init_excp_G2(env);
3229
    /* Allocate hardware IRQ controller */
3230
    ppc6xx_irq_init(env);
3231
}
3232

    
3233
/* PowerPC 604                                                               */
3234
#define POWERPC_INSNS_604    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3235
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
3236
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
3237
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
3238
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
3239
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
3240

    
3241
static void init_proc_604 (CPUPPCState *env)
3242
{
3243
    gen_spr_ne_601(env);
3244
    gen_spr_604(env);
3245
    /* Time base */
3246
    gen_tbl(env);
3247
    /* Hardware implementation registers */
3248
    /* XXX : not implemented */
3249
    spr_register(env, SPR_HID0, "HID0",
3250
                 SPR_NOACCESS, SPR_NOACCESS,
3251
                 &spr_read_generic, &spr_write_generic,
3252
                 0x00000000);
3253
    /* XXX : not implemented */
3254
    spr_register(env, SPR_HID1, "HID1",
3255
                 SPR_NOACCESS, SPR_NOACCESS,
3256
                 &spr_read_generic, &spr_write_generic,
3257
                 0x00000000);
3258
    /* Memory management */
3259
    gen_low_BATs(env);
3260
    init_excp_604(env);
3261
    /* Allocate hardware IRQ controller */
3262
    ppc6xx_irq_init(env);
3263
}
3264

    
3265
/* PowerPC 740/750 (aka G3)                                                  */
3266
#define POWERPC_INSNS_7x0    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3267
#define POWERPC_MSRM_7x0     (0x000000000007FF77ULL)
3268
#define POWERPC_MMU_7x0      (POWERPC_MMU_32B)
3269
//#define POWERPC_EXCP_7x0     (POWERPC_EXCP_7x0)
3270
#define POWERPC_INPUT_7x0    (PPC_FLAGS_INPUT_6xx)
3271
#define POWERPC_BFDM_7x0     (bfd_mach_ppc_750)
3272

    
3273
static void init_proc_7x0 (CPUPPCState *env)
3274
{
3275
    gen_spr_ne_601(env);
3276
    gen_spr_7xx(env);
3277
    /* Time base */
3278
    gen_tbl(env);
3279
    /* Thermal management */
3280
    gen_spr_thrm(env);
3281
    /* Hardware implementation registers */
3282
    /* XXX : not implemented */
3283
    spr_register(env, SPR_HID0, "HID0",
3284
                 SPR_NOACCESS, SPR_NOACCESS,
3285
                 &spr_read_generic, &spr_write_generic,
3286
                 0x00000000);
3287
    /* XXX : not implemented */
3288
    spr_register(env, SPR_HID1, "HID1",
3289
                 SPR_NOACCESS, SPR_NOACCESS,
3290
                 &spr_read_generic, &spr_write_generic,
3291
                 0x00000000);
3292
    /* Memory management */
3293
    gen_low_BATs(env);
3294
    init_excp_7x0(env);
3295
    /* Allocate hardware IRQ controller */
3296
    ppc6xx_irq_init(env);
3297
}
3298

    
3299
/* PowerPC 750FX/GX                                                          */
3300
#define POWERPC_INSNS_750fx  (POWERPC_INSNS_WORKS | PPC_EXTERN)
3301
#define POWERPC_MSRM_750fx   (0x000000000007FF77ULL)
3302
#define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
3303
#define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
3304
#define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
3305
#define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
3306

    
3307
static void init_proc_750fx (CPUPPCState *env)
3308
{
3309
    gen_spr_ne_601(env);
3310
    gen_spr_7xx(env);
3311
    /* Time base */
3312
    gen_tbl(env);
3313
    /* Thermal management */
3314
    gen_spr_thrm(env);
3315
    /* Hardware implementation registers */
3316
    /* XXX : not implemented */
3317
    spr_register(env, SPR_HID0, "HID0",
3318
                 SPR_NOACCESS, SPR_NOACCESS,
3319
                 &spr_read_generic, &spr_write_generic,
3320
                 0x00000000);
3321
    /* XXX : not implemented */
3322
    spr_register(env, SPR_HID1, "HID1",
3323
                 SPR_NOACCESS, SPR_NOACCESS,
3324
                 &spr_read_generic, &spr_write_generic,
3325
                 0x00000000);
3326
    /* XXX : not implemented */
3327
    spr_register(env, SPR_750_HID2, "HID2",
3328
                 SPR_NOACCESS, SPR_NOACCESS,
3329
                 &spr_read_generic, &spr_write_generic,
3330
                 0x00000000);
3331
    /* Memory management */
3332
    gen_low_BATs(env);
3333
    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3334
    gen_high_BATs(env);
3335
    init_excp_750FX(env);
3336
    /* Allocate hardware IRQ controller */
3337
    ppc6xx_irq_init(env);
3338
}
3339

    
3340
/* PowerPC 745/755                                                           */
3341
#define POWERPC_INSNS_7x5    (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3342
#define POWERPC_MSRM_7x5     (0x000000000007FF77ULL)
3343
#define POWERPC_MMU_7x5      (POWERPC_MMU_SOFT_6xx)
3344
//#define POWERPC_EXCP_7x5     (POWERPC_EXCP_7x5)
3345
#define POWERPC_INPUT_7x5    (PPC_FLAGS_INPUT_6xx)
3346
#define POWERPC_BFDM_7x5     (bfd_mach_ppc_750)
3347

    
3348
static void init_proc_7x5 (CPUPPCState *env)
3349
{
3350
    gen_spr_ne_601(env);
3351
    gen_spr_G2_755(env);
3352
    /* Time base */
3353
    gen_tbl(env);
3354
    /* L2 cache control */
3355
    /* XXX : not implemented */
3356
    spr_register(env, SPR_ICTC, "ICTC",
3357
                 SPR_NOACCESS, SPR_NOACCESS,
3358
                 &spr_read_generic, &spr_write_generic,
3359
                 0x00000000);
3360
    /* XXX : not implemented */
3361
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3362
                 SPR_NOACCESS, SPR_NOACCESS,
3363
                 &spr_read_generic, &spr_write_generic,
3364
                 0x00000000);
3365
    /* Hardware implementation registers */
3366
    /* XXX : not implemented */
3367
    spr_register(env, SPR_HID0, "HID0",
3368
                 SPR_NOACCESS, SPR_NOACCESS,
3369
                 &spr_read_generic, &spr_write_generic,
3370
                 0x00000000);
3371
    /* XXX : not implemented */
3372
    spr_register(env, SPR_HID1, "HID1",
3373
                 SPR_NOACCESS, SPR_NOACCESS,
3374
                 &spr_read_generic, &spr_write_generic,
3375
                 0x00000000);
3376
    /* XXX : not implemented */
3377
    spr_register(env, SPR_HID2, "HID2",
3378
                 SPR_NOACCESS, SPR_NOACCESS,
3379
                 &spr_read_generic, &spr_write_generic,
3380
                 0x00000000);
3381
    /* Memory management */
3382
    gen_low_BATs(env);
3383
    gen_high_BATs(env);
3384
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3385
    /* Allocate hardware IRQ controller */
3386
    ppc6xx_irq_init(env);
3387
}
3388

    
3389
/* PowerPC 7400 (aka G4)                                                     */
3390
#define POWERPC_INSNS_7400   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3391
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3392
                              PPC_ALTIVEC)
3393
#define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
3394
#define POWERPC_MMU_7400     (POWERPC_MMU_32B)
3395
#define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
3396
#define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
3397
#define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
3398

    
3399
static void init_proc_7400 (CPUPPCState *env)
3400
{
3401
    gen_spr_ne_601(env);
3402
    gen_spr_7xx(env);
3403
    /* Time base */
3404
    gen_tbl(env);
3405
    /* 74xx specific SPR */
3406
    gen_spr_74xx(env);
3407
    /* Thermal management */
3408
    gen_spr_thrm(env);
3409
    /* Memory management */
3410
    gen_low_BATs(env);
3411
    init_excp_7400(env);
3412
    /* Allocate hardware IRQ controller */
3413
    ppc6xx_irq_init(env);
3414
}
3415

    
3416
/* PowerPC 7410 (aka G4)                                                     */
3417
#define POWERPC_INSNS_7410   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3418
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3419
                              PPC_ALTIVEC)
3420
#define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
3421
#define POWERPC_MMU_7410     (POWERPC_MMU_32B)
3422
#define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
3423
#define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
3424
#define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
3425

    
3426
static void init_proc_7410 (CPUPPCState *env)
3427
{
3428
    gen_spr_ne_601(env);
3429
    gen_spr_7xx(env);
3430
    /* Time base */
3431
    gen_tbl(env);
3432
    /* 74xx specific SPR */
3433
    gen_spr_74xx(env);
3434
    /* Thermal management */
3435
    gen_spr_thrm(env);
3436
    /* L2PMCR */
3437
    /* XXX : not implemented */
3438
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3439
                 SPR_NOACCESS, SPR_NOACCESS,
3440
                 &spr_read_generic, &spr_write_generic,
3441
                 0x00000000);
3442
    /* LDSTDB */
3443
    /* XXX : not implemented */
3444
    spr_register(env, SPR_LDSTDB, "LDSTDB",
3445
                 SPR_NOACCESS, SPR_NOACCESS,
3446
                 &spr_read_generic, &spr_write_generic,
3447
                 0x00000000);
3448
    /* Memory management */
3449
    gen_low_BATs(env);
3450
    init_excp_7400(env);
3451
    /* Allocate hardware IRQ controller */
3452
    ppc6xx_irq_init(env);
3453
}
3454

    
3455
/* PowerPC 7440 (aka G4)                                                     */
3456
#if defined (TODO)
3457
#define POWERPC_INSNS_7440   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3458
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3459
                              PPC_ALTIVEC)
3460
#define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
3461
#define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
3462
#define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
3463
#define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
3464
#define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
3465

    
3466
static void init_proc_7440 (CPUPPCState *env)
3467
{
3468
    gen_spr_ne_601(env);
3469
    gen_spr_7xx(env);
3470
    /* Time base */
3471
    gen_tbl(env);
3472
    /* 74xx specific SPR */
3473
    gen_spr_74xx(env);
3474
    /* LDSTCR */
3475
    /* XXX : not implemented */
3476
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3477
                 SPR_NOACCESS, SPR_NOACCESS,
3478
                 &spr_read_generic, &spr_write_generic,
3479
                 0x00000000);
3480
    /* ICTRL */
3481
    /* XXX : not implemented */
3482
    spr_register(env, SPR_ICTRL, "ICTRL",
3483
                 SPR_NOACCESS, SPR_NOACCESS,
3484
                 &spr_read_generic, &spr_write_generic,
3485
                 0x00000000);
3486
    /* MSSSR0 */
3487
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3488
                 SPR_NOACCESS, SPR_NOACCESS,
3489
                 &spr_read_generic, &spr_write_generic,
3490
                 0x00000000);
3491
    /* PMC */
3492
    /* XXX : not implemented */
3493
    spr_register(env, SPR_PMC5, "PMC5",
3494
                 SPR_NOACCESS, SPR_NOACCESS,
3495
                 &spr_read_generic, &spr_write_generic,
3496
                 0x00000000);
3497
    spr_register(env, SPR_UPMC5, "UPMC5",
3498
                 &spr_read_ureg, SPR_NOACCESS,
3499
                 &spr_read_ureg, SPR_NOACCESS,
3500
                 0x00000000);
3501
    spr_register(env, SPR_PMC6, "PMC6",
3502
                 SPR_NOACCESS, SPR_NOACCESS,
3503
                 &spr_read_generic, &spr_write_generic,
3504
                 0x00000000);
3505
    spr_register(env, SPR_UPMC6, "UPMC6",
3506
                 &spr_read_ureg, SPR_NOACCESS,
3507
                 &spr_read_ureg, SPR_NOACCESS,
3508
                 0x00000000);
3509
    /* Memory management */
3510
    gen_low_BATs(env);
3511
    gen_74xx_soft_tlb(env);
3512
    /* Allocate hardware IRQ controller */
3513
    ppc6xx_irq_init(env);
3514
}
3515
#endif /* TODO */
3516

    
3517
/* PowerPC 7450 (aka G4)                                                     */
3518
#if defined (TODO)
3519
#define POWERPC_INSNS_7450   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3520
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3521
                              PPC_ALTIVEC)
3522
#define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
3523
#define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
3524
#define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
3525
#define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
3526
#define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
3527

    
3528
static void init_proc_7450 (CPUPPCState *env)
3529
{
3530
    gen_spr_ne_601(env);
3531
    gen_spr_7xx(env);
3532
    /* Time base */
3533
    gen_tbl(env);
3534
    /* 74xx specific SPR */
3535
    gen_spr_74xx(env);
3536
    /* Level 3 cache control */
3537
    gen_l3_ctrl(env);
3538
    /* LDSTCR */
3539
    /* XXX : not implemented */
3540
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3541
                 SPR_NOACCESS, SPR_NOACCESS,
3542
                 &spr_read_generic, &spr_write_generic,
3543
                 0x00000000);
3544
    /* ICTRL */
3545
    /* XXX : not implemented */
3546
    spr_register(env, SPR_ICTRL, "ICTRL",
3547
                 SPR_NOACCESS, SPR_NOACCESS,
3548
                 &spr_read_generic, &spr_write_generic,
3549
                 0x00000000);
3550
    /* MSSSR0 */
3551
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3552
                 SPR_NOACCESS, SPR_NOACCESS,
3553
                 &spr_read_generic, &spr_write_generic,
3554
                 0x00000000);
3555
    /* PMC */
3556
    /* XXX : not implemented */
3557
    spr_register(env, SPR_PMC5, "PMC5",
3558
                 SPR_NOACCESS, SPR_NOACCESS,
3559
                 &spr_read_generic, &spr_write_generic,
3560
                 0x00000000);
3561
    spr_register(env, SPR_UPMC5, "UPMC5",
3562
                 &spr_read_ureg, SPR_NOACCESS,
3563
                 &spr_read_ureg, SPR_NOACCESS,
3564
                 0x00000000);
3565
    spr_register(env, SPR_PMC6, "PMC6",
3566
                 SPR_NOACCESS, SPR_NOACCESS,
3567
                 &spr_read_generic, &spr_write_generic,
3568
                 0x00000000);
3569
    spr_register(env, SPR_UPMC6, "UPMC6",
3570
                 &spr_read_ureg, SPR_NOACCESS,
3571
                 &spr_read_ureg, SPR_NOACCESS,
3572
                 0x00000000);
3573
    /* Memory management */
3574
    gen_low_BATs(env);
3575
    gen_74xx_soft_tlb(env);
3576
    init_excp_7450(env);
3577
    /* Allocate hardware IRQ controller */
3578
    ppc6xx_irq_init(env);
3579
}
3580
#endif /* TODO */
3581

    
3582
/* PowerPC 7445 (aka G4)                                                     */
3583
#if defined (TODO)
3584
#define POWERPC_INSNS_7445   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3585
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3586
                              PPC_ALTIVEC)
3587
#define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
3588
#define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
3589
#define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
3590
#define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
3591
#define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
3592

    
3593
static void init_proc_7445 (CPUPPCState *env)
3594
{
3595
    gen_spr_ne_601(env);
3596
    gen_spr_7xx(env);
3597
    /* Time base */
3598
    gen_tbl(env);
3599
    /* 74xx specific SPR */
3600
    gen_spr_74xx(env);
3601
    /* LDSTCR */
3602
    /* XXX : not implemented */
3603
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3604
                 SPR_NOACCESS, SPR_NOACCESS,
3605
                 &spr_read_generic, &spr_write_generic,
3606
                 0x00000000);
3607
    /* ICTRL */
3608
    /* XXX : not implemented */
3609
    spr_register(env, SPR_ICTRL, "ICTRL",
3610
                 SPR_NOACCESS, SPR_NOACCESS,
3611
                 &spr_read_generic, &spr_write_generic,
3612
                 0x00000000);
3613
    /* MSSSR0 */
3614
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3615
                 SPR_NOACCESS, SPR_NOACCESS,
3616
                 &spr_read_generic, &spr_write_generic,
3617
                 0x00000000);
3618
    /* PMC */
3619
    /* XXX : not implemented */
3620
    spr_register(env, SPR_PMC5, "PMC5",
3621
                 SPR_NOACCESS, SPR_NOACCESS,
3622
                 &spr_read_generic, &spr_write_generic,
3623
                 0x00000000);
3624
    spr_register(env, SPR_UPMC5, "UPMC5",
3625
                 &spr_read_ureg, SPR_NOACCESS,
3626
                 &spr_read_ureg, SPR_NOACCESS,
3627
                 0x00000000);
3628
    spr_register(env, SPR_PMC6, "PMC6",
3629
                 SPR_NOACCESS, SPR_NOACCESS,
3630
                 &spr_read_generic, &spr_write_generic,
3631
                 0x00000000);
3632
    spr_register(env, SPR_UPMC6, "UPMC6",
3633
                 &spr_read_ureg, SPR_NOACCESS,
3634
                 &spr_read_ureg, SPR_NOACCESS,
3635
                 0x00000000);
3636
    /* SPRGs */
3637
    spr_register(env, SPR_SPRG4, "SPRG4",
3638
                 SPR_NOACCESS, SPR_NOACCESS,
3639
                 &spr_read_generic, &spr_write_generic,
3640
                 0x00000000);
3641
    spr_register(env, SPR_USPRG4, "USPRG4",
3642
                 &spr_read_ureg, SPR_NOACCESS,
3643
                 &spr_read_ureg, SPR_NOACCESS,
3644
                 0x00000000);
3645
    spr_register(env, SPR_SPRG5, "SPRG5",
3646
                 SPR_NOACCESS, SPR_NOACCESS,
3647
                 &spr_read_generic, &spr_write_generic,
3648
                 0x00000000);
3649
    spr_register(env, SPR_USPRG5, "USPRG5",
3650
                 &spr_read_ureg, SPR_NOACCESS,
3651
                 &spr_read_ureg, SPR_NOACCESS,
3652
                 0x00000000);
3653
    spr_register(env, SPR_SPRG6, "SPRG6",
3654
                 SPR_NOACCESS, SPR_NOACCESS,
3655
                 &spr_read_generic, &spr_write_generic,
3656
                 0x00000000);
3657
    spr_register(env, SPR_USPRG6, "USPRG6",
3658
                 &spr_read_ureg, SPR_NOACCESS,
3659
                 &spr_read_ureg, SPR_NOACCESS,
3660
                 0x00000000);
3661
    spr_register(env, SPR_SPRG7, "SPRG7",
3662
                 SPR_NOACCESS, SPR_NOACCESS,
3663
                 &spr_read_generic, &spr_write_generic,
3664
                 0x00000000);
3665
    spr_register(env, SPR_USPRG7, "USPRG7",
3666
                 &spr_read_ureg, SPR_NOACCESS,
3667
                 &spr_read_ureg, SPR_NOACCESS,
3668
                 0x00000000);
3669
    /* Memory management */
3670
    gen_low_BATs(env);
3671
    gen_high_BATs(env);
3672
    gen_74xx_soft_tlb(env);
3673
    init_excp_7450(env);
3674
    /* Allocate hardware IRQ controller */
3675
    ppc6xx_irq_init(env);
3676
}
3677
#endif /* TODO */
3678

    
3679
/* PowerPC 7455 (aka G4)                                                     */
3680
#if defined (TODO)
3681
#define POWERPC_INSNS_7455   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3682
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3683
                              PPC_ALTIVEC)
3684
#define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
3685
#define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
3686
#define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
3687
#define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
3688
#define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
3689

    
3690
static void init_proc_7455 (CPUPPCState *env)
3691
{
3692
    gen_spr_ne_601(env);
3693
    gen_spr_7xx(env);
3694
    /* Time base */
3695
    gen_tbl(env);
3696
    /* 74xx specific SPR */
3697
    gen_spr_74xx(env);
3698
    /* Level 3 cache control */
3699
    gen_l3_ctrl(env);
3700
    /* LDSTCR */
3701
    /* XXX : not implemented */
3702
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3703
                 SPR_NOACCESS, SPR_NOACCESS,
3704
                 &spr_read_generic, &spr_write_generic,
3705
                 0x00000000);
3706
    /* ICTRL */
3707
    /* XXX : not implemented */
3708
    spr_register(env, SPR_ICTRL, "ICTRL",
3709
                 SPR_NOACCESS, SPR_NOACCESS,
3710
                 &spr_read_generic, &spr_write_generic,
3711
                 0x00000000);
3712
    /* MSSSR0 */
3713
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3714
                 SPR_NOACCESS, SPR_NOACCESS,
3715
                 &spr_read_generic, &spr_write_generic,
3716
                 0x00000000);
3717
    /* PMC */
3718
    /* XXX : not implemented */
3719
    spr_register(env, SPR_PMC5, "PMC5",
3720
                 SPR_NOACCESS, SPR_NOACCESS,
3721
                 &spr_read_generic, &spr_write_generic,
3722
                 0x00000000);
3723
    spr_register(env, SPR_UPMC5, "UPMC5",
3724
                 &spr_read_ureg, SPR_NOACCESS,
3725
                 &spr_read_ureg, SPR_NOACCESS,
3726
                 0x00000000);
3727
    spr_register(env, SPR_PMC6, "PMC6",
3728
                 SPR_NOACCESS, SPR_NOACCESS,
3729
                 &spr_read_generic, &spr_write_generic,
3730
                 0x00000000);
3731
    spr_register(env, SPR_UPMC6, "UPMC6",
3732
                 &spr_read_ureg, SPR_NOACCESS,
3733
                 &spr_read_ureg, SPR_NOACCESS,
3734
                 0x00000000);
3735
    /* SPRGs */
3736
    spr_register(env, SPR_SPRG4, "SPRG4",
3737
                 SPR_NOACCESS, SPR_NOACCESS,
3738
                 &spr_read_generic, &spr_write_generic,
3739
                 0x00000000);
3740
    spr_register(env, SPR_USPRG4, "USPRG4",
3741
                 &spr_read_ureg, SPR_NOACCESS,
3742
                 &spr_read_ureg, SPR_NOACCESS,
3743
                 0x00000000);
3744
    spr_register(env, SPR_SPRG5, "SPRG5",
3745
                 SPR_NOACCESS, SPR_NOACCESS,
3746
                 &spr_read_generic, &spr_write_generic,
3747
                 0x00000000);
3748
    spr_register(env, SPR_USPRG5, "USPRG5",
3749
                 &spr_read_ureg, SPR_NOACCESS,
3750
                 &spr_read_ureg, SPR_NOACCESS,
3751
                 0x00000000);
3752
    spr_register(env, SPR_SPRG6, "SPRG6",
3753
                 SPR_NOACCESS, SPR_NOACCESS,
3754
                 &spr_read_generic, &spr_write_generic,
3755
                 0x00000000);
3756
    spr_register(env, SPR_USPRG6, "USPRG6",
3757
                 &spr_read_ureg, SPR_NOACCESS,
3758
                 &spr_read_ureg, SPR_NOACCESS,
3759
                 0x00000000);
3760
    spr_register(env, SPR_SPRG7, "SPRG7",
3761
                 SPR_NOACCESS, SPR_NOACCESS,
3762
                 &spr_read_generic, &spr_write_generic,
3763
                 0x00000000);
3764
    spr_register(env, SPR_USPRG7, "USPRG7",
3765
                 &spr_read_ureg, SPR_NOACCESS,
3766
                 &spr_read_ureg, SPR_NOACCESS,
3767
                 0x00000000);
3768
    /* Memory management */
3769
    gen_low_BATs(env);
3770
    gen_high_BATs(env);
3771
    gen_74xx_soft_tlb(env);
3772
    init_excp_7450(env);
3773
    /* Allocate hardware IRQ controller */
3774
    ppc6xx_irq_init(env);
3775
}
3776
#endif /* TODO */
3777

    
3778
#if defined (TARGET_PPC64)
3779
/* PowerPC 970                                                               */
3780
#define POWERPC_INSNS_970    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3781
                              PPC_64B | PPC_ALTIVEC |                         \
3782
                              PPC_64_BRIDGE | PPC_SLBI)
3783
#define POWERPC_MSRM_970     (0x900000000204FF36ULL)
3784
#define POWERPC_MMU_970      (POWERPC_MMU_64BRIDGE)
3785
//#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
3786
#define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
3787
#define POWERPC_BFDM_970     (bfd_mach_ppc64)
3788

    
3789
static void init_proc_970 (CPUPPCState *env)
3790
{
3791
    gen_spr_ne_601(env);
3792
    gen_spr_7xx(env);
3793
    /* Time base */
3794
    gen_tbl(env);
3795
    /* Hardware implementation registers */
3796
    /* XXX : not implemented */
3797
    spr_register(env, SPR_HID0, "HID0",
3798
                 SPR_NOACCESS, SPR_NOACCESS,
3799
                 &spr_read_generic, &spr_write_generic,
3800
                 0x00000000);
3801
    /* XXX : not implemented */
3802
    spr_register(env, SPR_HID1, "HID1",
3803
                 SPR_NOACCESS, SPR_NOACCESS,
3804
                 &spr_read_generic, &spr_write_generic,
3805
                 0x00000000);
3806
    /* XXX : not implemented */
3807
    spr_register(env, SPR_750_HID2, "HID2",
3808
                 SPR_NOACCESS, SPR_NOACCESS,
3809
                 &spr_read_generic, &spr_write_generic,
3810
                 0x00000000);
3811
    /* Memory management */
3812
    /* XXX: not correct */
3813
    gen_low_BATs(env);
3814
#if 0 // TODO
3815
    env->slb_nr = 32;
3816
#endif
3817
    init_excp_970(env);
3818
    /* Allocate hardware IRQ controller */
3819
    ppc970_irq_init(env);
3820
}
3821

    
3822
/* PowerPC 970FX (aka G5)                                                    */
3823
#define POWERPC_INSNS_970FX  (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3824
                              PPC_64B | PPC_ALTIVEC |                         \
3825
                              PPC_64_BRIDGE | PPC_SLBI)
3826
#define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
3827
#define POWERPC_MMU_970FX    (POWERPC_MMU_64BRIDGE)
3828
#define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
3829
#define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
3830
#define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
3831

    
3832
static void init_proc_970FX (CPUPPCState *env)
3833
{
3834
    gen_spr_ne_601(env);
3835
    gen_spr_7xx(env);
3836
    /* Time base */
3837
    gen_tbl(env);
3838
    /* Hardware implementation registers */
3839
    /* XXX : not implemented */
3840
    spr_register(env, SPR_HID0, "HID0",
3841
                 SPR_NOACCESS, SPR_NOACCESS,
3842
                 &spr_read_generic, &spr_write_generic,
3843
                 0x00000000);
3844
    /* XXX : not implemented */
3845
    spr_register(env, SPR_HID1, "HID1",
3846
                 SPR_NOACCESS, SPR_NOACCESS,
3847
                 &spr_read_generic, &spr_write_generic,
3848
                 0x00000000);
3849
    /* XXX : not implemented */
3850
    spr_register(env, SPR_750_HID2, "HID2",
3851
                 SPR_NOACCESS, SPR_NOACCESS,
3852
                 &spr_read_generic, &spr_write_generic,
3853
                 0x00000000);
3854
    /* Memory management */
3855
    /* XXX: not correct */
3856
    gen_low_BATs(env);
3857
#if 0 // TODO
3858
    env->slb_nr = 32;
3859
#endif
3860
    init_excp_970(env);
3861
    /* Allocate hardware IRQ controller */
3862
    ppc970_irq_init(env);
3863
}
3864

    
3865
/* PowerPC 970 GX                                                            */
3866
#define POWERPC_INSNS_970GX  (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3867
                              PPC_64B | PPC_ALTIVEC |                         \
3868
                              PPC_64_BRIDGE | PPC_SLBI)
3869
#define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
3870
#define POWERPC_MMU_970GX    (POWERPC_MMU_64BRIDGE)
3871
#define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
3872
#define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
3873
#define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
3874

    
3875
static void init_proc_970GX (CPUPPCState *env)
3876
{
3877
    gen_spr_ne_601(env);
3878
    gen_spr_7xx(env);
3879
    /* Time base */
3880
    gen_tbl(env);
3881
    /* Hardware implementation registers */
3882
    /* XXX : not implemented */
3883
    spr_register(env, SPR_HID0, "HID0",
3884
                 SPR_NOACCESS, SPR_NOACCESS,
3885
                 &spr_read_generic, &spr_write_generic,
3886
                 0x00000000);
3887
    /* XXX : not implemented */
3888
    spr_register(env, SPR_HID1, "HID1",
3889
                 SPR_NOACCESS, SPR_NOACCESS,
3890
                 &spr_read_generic, &spr_write_generic,
3891
                 0x00000000);
3892
    /* XXX : not implemented */
3893
    spr_register(env, SPR_750_HID2, "HID2",
3894
                 SPR_NOACCESS, SPR_NOACCESS,
3895
                 &spr_read_generic, &spr_write_generic,
3896
                 0x00000000);
3897
    /* Memory management */
3898
    /* XXX: not correct */
3899
    gen_low_BATs(env);
3900
#if 0 // TODO
3901
    env->slb_nr = 32;
3902
#endif
3903
    init_excp_970(env);
3904
    /* Allocate hardware IRQ controller */
3905
    ppc970_irq_init(env);
3906
}
3907

    
3908
/* PowerPC 620                                                               */
3909
#if defined (TODO)
3910
#define POWERPC_INSNS_620    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3911
                              PPC_64B | PPC_SLBI)
3912
#define POWERPC_MSRM_620     (0x800000000005FF73ULL)
3913
#define POWERPC_MMU_620      (POWERPC_MMU_64B)
3914
#define POWERPC_EXCP_620     (POWERPC_EXCP_970)
3915
#define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_970)
3916
#define POWERPC_BFDM_620     (bfd_mach_ppc64)
3917

    
3918
static void init_proc_620 (CPUPPCState *env)
3919
{
3920
    gen_spr_ne_601(env);
3921
    gen_spr_620(env);
3922
    /* Time base */
3923
    gen_tbl(env);
3924
    /* Hardware implementation registers */
3925
    /* XXX : not implemented */
3926
    spr_register(env, SPR_HID0, "HID0",
3927
                 SPR_NOACCESS, SPR_NOACCESS,
3928
                 &spr_read_generic, &spr_write_generic,
3929
                 0x00000000);
3930
    /* Memory management */
3931
    gen_low_BATs(env);
3932
    gen_high_BATs(env);
3933
    init_excp_620(env);
3934
    /* XXX: TODO: initialize internal interrupt controller */
3935
}
3936
#endif /* TODO */
3937
#endif /* defined (TARGET_PPC64) */
3938

    
3939
/* Default 32 bits PowerPC target will be 604 */
3940
#define CPU_POWERPC_PPC32     CPU_POWERPC_604
3941
#define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
3942
#define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
3943
#define POWERPC_MMU_PPC32     POWERPC_MMU_604
3944
#define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
3945
#define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
3946
#define init_proc_PPC32       init_proc_604
3947
#define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
3948

    
3949
/* Default 64 bits PowerPC target will be 970 FX */
3950
#define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
3951
#define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
3952
#define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
3953
#define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
3954
#define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
3955
#define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
3956
#define init_proc_PPC64       init_proc_970FX
3957
#define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
3958

    
3959
/* Default PowerPC target will be PowerPC 32 */
3960
#if defined (TARGET_PPC64) && 0 // XXX: TODO
3961
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
3962
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
3963
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
3964
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
3965
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
3966
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
3967
#define init_proc_DEFAULT     init_proc_PPC64
3968
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
3969
#else
3970
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
3971
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
3972
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
3973
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
3974
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
3975
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
3976
#define init_proc_DEFAULT     init_proc_PPC32
3977
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
3978
#endif
3979

    
3980
/*****************************************************************************/
3981
/* PVR definitions for most known PowerPC                                    */
3982
enum {
3983
    /* PowerPC 401 family */
3984
    /* Generic PowerPC 401 */
3985
#define CPU_POWERPC_401       CPU_POWERPC_401G2
3986
    /* PowerPC 401 cores */
3987
    CPU_POWERPC_401A1       = 0x00210000,
3988
    CPU_POWERPC_401B2       = 0x00220000,
3989
#if 0
3990
    CPU_POWERPC_401B3       = xxx,
3991
#endif
3992
    CPU_POWERPC_401C2       = 0x00230000,
3993
    CPU_POWERPC_401D2       = 0x00240000,
3994
    CPU_POWERPC_401E2       = 0x00250000,
3995
    CPU_POWERPC_401F2       = 0x00260000,
3996
    CPU_POWERPC_401G2       = 0x00270000,
3997
    /* PowerPC 401 microcontrolers */
3998
#if 0
3999
    CPU_POWERPC_401GF       = xxx,
4000
#endif
4001
#define CPU_POWERPC_IOP480    CPU_POWERPC_401B2
4002
    /* IBM Processor for Network Resources */
4003
    CPU_POWERPC_COBRA       = 0x10100000, /* XXX: 405 ? */
4004
#if 0
4005
    CPU_POWERPC_XIPCHIP     = xxx,
4006
#endif
4007
    /* PowerPC 403 family */
4008
    /* Generic PowerPC 403 */
4009
#define CPU_POWERPC_403       CPU_POWERPC_403GC
4010
    /* PowerPC 403 microcontrollers */
4011
    CPU_POWERPC_403GA       = 0x00200011,
4012
    CPU_POWERPC_403GB       = 0x00200100,
4013
    CPU_POWERPC_403GC       = 0x00200200,
4014
    CPU_POWERPC_403GCX      = 0x00201400,
4015
#if 0
4016
    CPU_POWERPC_403GP       = xxx,
4017
#endif
4018
    /* PowerPC 405 family */
4019
    /* Generic PowerPC 405 */
4020
#define CPU_POWERPC_405       CPU_POWERPC_405D4
4021
    /* PowerPC 405 cores */
4022
#if 0
4023
    CPU_POWERPC_405A3       = xxx,
4024
#endif
4025
#if 0
4026
    CPU_POWERPC_405A4       = xxx,
4027
#endif
4028
#if 0
4029
    CPU_POWERPC_405B3       = xxx,
4030
#endif
4031
#if 0
4032
    CPU_POWERPC_405B4       = xxx,
4033
#endif
4034
#if 0
4035
    CPU_POWERPC_405C3       = xxx,
4036
#endif
4037
#if 0
4038
    CPU_POWERPC_405C4       = xxx,
4039
#endif
4040
    CPU_POWERPC_405D2       = 0x20010000,
4041
#if 0
4042
    CPU_POWERPC_405D3       = xxx,
4043
#endif
4044
    CPU_POWERPC_405D4       = 0x41810000,
4045
#if 0
4046
    CPU_POWERPC_405D5       = xxx,
4047
#endif
4048
#if 0
4049
    CPU_POWERPC_405E4       = xxx,
4050
#endif
4051
#if 0
4052
    CPU_POWERPC_405F4       = xxx,
4053
#endif
4054
#if 0
4055
    CPU_POWERPC_405F5       = xxx,
4056
#endif
4057
#if 0
4058
    CPU_POWERPC_405F6       = xxx,
4059
#endif
4060
    /* PowerPC 405 microcontrolers */
4061
    /* XXX: missing 0x200108a0 */
4062
#define CPU_POWERPC_405CR     CPU_POWERPC_405CRc
4063
    CPU_POWERPC_405CRa      = 0x40110041,
4064
    CPU_POWERPC_405CRb      = 0x401100C5,
4065
    CPU_POWERPC_405CRc      = 0x40110145,
4066
    CPU_POWERPC_405EP       = 0x51210950,
4067
#if 0
4068
    CPU_POWERPC_405EXr      = xxx,
4069
#endif
4070
    CPU_POWERPC_405EZ       = 0x41511460, /* 0x51210950 ? */
4071
#if 0
4072
    CPU_POWERPC_405FX       = xxx,
4073
#endif
4074
#define CPU_POWERPC_405GP     CPU_POWERPC_405GPd
4075
    CPU_POWERPC_405GPa      = 0x40110000,
4076
    CPU_POWERPC_405GPb      = 0x40110040,
4077
    CPU_POWERPC_405GPc      = 0x40110082,
4078
    CPU_POWERPC_405GPd      = 0x401100C4,
4079
#define CPU_POWERPC_405GPe    CPU_POWERPC_405CRc
4080
    CPU_POWERPC_405GPR      = 0x50910951,
4081
#if 0
4082
    CPU_POWERPC_405H        = xxx,
4083
#endif
4084
#if 0
4085
    CPU_POWERPC_405L        = xxx,
4086
#endif
4087
    CPU_POWERPC_405LP       = 0x41F10000,
4088
#if 0
4089
    CPU_POWERPC_405PM       = xxx,
4090
#endif
4091
#if 0
4092
    CPU_POWERPC_405PS       = xxx,
4093
#endif
4094
#if 0
4095
    CPU_POWERPC_405S        = xxx,
4096
#endif
4097
    /* IBM network processors */
4098
    CPU_POWERPC_NPE405H     = 0x414100C0,
4099
    CPU_POWERPC_NPE405H2    = 0x41410140,
4100
    CPU_POWERPC_NPE405L     = 0x416100C0,
4101
    CPU_POWERPC_NPE4GS3     = 0x40B10000,
4102
#if 0
4103
    CPU_POWERPC_NPCxx1      = xxx,
4104
#endif
4105
#if 0
4106
    CPU_POWERPC_NPR161      = xxx,
4107
#endif
4108
#if 0
4109
    CPU_POWERPC_LC77700     = xxx,
4110
#endif
4111
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4112
#if 0
4113
    CPU_POWERPC_STB01000    = xxx,
4114
#endif
4115
#if 0
4116
    CPU_POWERPC_STB01010    = xxx,
4117
#endif
4118
#if 0
4119
    CPU_POWERPC_STB0210     = xxx, /* 401B3 */
4120
#endif
4121
    CPU_POWERPC_STB03       = 0x40310000, /* 0x40130000 ? */
4122
#if 0
4123
    CPU_POWERPC_STB043      = xxx,
4124
#endif
4125
#if 0
4126
    CPU_POWERPC_STB045      = xxx,
4127
#endif
4128
    CPU_POWERPC_STB04       = 0x41810000,
4129
    CPU_POWERPC_STB25       = 0x51510950,
4130
#if 0
4131
    CPU_POWERPC_STB130      = xxx,
4132
#endif
4133
    /* Xilinx cores */
4134
    CPU_POWERPC_X2VP4       = 0x20010820,
4135
#define CPU_POWERPC_X2VP7     CPU_POWERPC_X2VP4
4136
    CPU_POWERPC_X2VP20      = 0x20010860,
4137
#define CPU_POWERPC_X2VP50    CPU_POWERPC_X2VP20
4138
#if 0
4139
    CPU_POWERPC_ZL10310     = xxx,
4140
#endif
4141
#if 0
4142
    CPU_POWERPC_ZL10311     = xxx,
4143
#endif
4144
#if 0
4145
    CPU_POWERPC_ZL10320     = xxx,
4146
#endif
4147
#if 0
4148
    CPU_POWERPC_ZL10321     = xxx,
4149
#endif
4150
    /* PowerPC 440 family */
4151
    /* Generic PowerPC 440 */
4152
#define CPU_POWERPC_440       CPU_POWERPC_440GXf
4153
    /* PowerPC 440 cores */
4154
#if 0
4155
    CPU_POWERPC_440A4       = xxx,
4156
#endif
4157
#if 0
4158
    CPU_POWERPC_440A5       = xxx,
4159
#endif
4160
#if 0
4161
    CPU_POWERPC_440B4       = xxx,
4162
#endif
4163
#if 0
4164
    CPU_POWERPC_440F5       = xxx,
4165
#endif
4166
#if 0
4167
    CPU_POWERPC_440G5       = xxx,
4168
#endif
4169
#if 0
4170
    CPU_POWERPC_440H4       = xxx,
4171
#endif
4172
#if 0
4173
    CPU_POWERPC_440H6       = xxx,
4174
#endif
4175
    /* PowerPC 440 microcontrolers */
4176
#define CPU_POWERPC_440EP     CPU_POWERPC_440EPb
4177
    CPU_POWERPC_440EPa      = 0x42221850,
4178
    CPU_POWERPC_440EPb      = 0x422218D3,
4179
#define CPU_POWERPC_440GP     CPU_POWERPC_440GPc
4180
    CPU_POWERPC_440GPb      = 0x40120440,
4181
    CPU_POWERPC_440GPc      = 0x40120481,
4182
#define CPU_POWERPC_440GR     CPU_POWERPC_440GRa
4183
#define CPU_POWERPC_440GRa    CPU_POWERPC_440EPb
4184
    CPU_POWERPC_440GRX      = 0x200008D0,
4185
#define CPU_POWERPC_440EPX    CPU_POWERPC_440GRX
4186
#define CPU_POWERPC_440GX     CPU_POWERPC_440GXf
4187
    CPU_POWERPC_440GXa      = 0x51B21850,
4188
    CPU_POWERPC_440GXb      = 0x51B21851,
4189
    CPU_POWERPC_440GXc      = 0x51B21892,
4190
    CPU_POWERPC_440GXf      = 0x51B21894,
4191
#if 0
4192
    CPU_POWERPC_440S        = xxx,
4193
#endif
4194
    CPU_POWERPC_440SP       = 0x53221850,
4195
    CPU_POWERPC_440SP2      = 0x53221891,
4196
    CPU_POWERPC_440SPE      = 0x53421890,
4197
    /* PowerPC 460 family */
4198
#if 0
4199
    /* Generic PowerPC 464 */
4200
#define CPU_POWERPC_464       CPU_POWERPC_464H90
4201
#endif
4202
    /* PowerPC 464 microcontrolers */
4203
#if 0
4204
    CPU_POWERPC_464H90      = xxx,
4205
#endif
4206
#if 0
4207
    CPU_POWERPC_464H90FP    = xxx,
4208
#endif
4209
    /* Freescale embedded PowerPC cores */
4210
    /* e200 family */
4211
#define CPU_POWERPC_e200      CPU_POWERPC_e200z6
4212
#if 0
4213
    CPU_POWERPC_e200z0      = xxx,
4214
#endif
4215
#if 0
4216
    CPU_POWERPC_e200z3      = xxx,
4217
#endif
4218
    CPU_POWERPC_e200z5      = 0x81000000,
4219
    CPU_POWERPC_e200z6      = 0x81120000,
4220
    /* e300 family */
4221
#define CPU_POWERPC_e300      CPU_POWERPC_e300c3
4222
    CPU_POWERPC_e300c1      = 0x00830000,
4223
    CPU_POWERPC_e300c2      = 0x00840000,
4224
    CPU_POWERPC_e300c3      = 0x00850000,
4225
    /* e500 family */
4226
#define CPU_POWERPC_e500      CPU_POWERPC_e500_v22
4227
    CPU_POWERPC_e500_v11    = 0x80200010,
4228
    CPU_POWERPC_e500_v12    = 0x80200020,
4229
    CPU_POWERPC_e500_v21    = 0x80210010,
4230
    CPU_POWERPC_e500_v22    = 0x80210020,
4231
#if 0
4232
    CPU_POWERPC_e500mc      = xxx,
4233
#endif
4234
    /* e600 family */
4235
    CPU_POWERPC_e600        = 0x80040010,
4236
    /* PowerPC MPC 5xx cores */
4237
    CPU_POWERPC_5xx         = 0x00020020,
4238
    /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4239
    CPU_POWERPC_8xx         = 0x00500000,
4240
    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4241
    CPU_POWERPC_82xx_HIP3   = 0x00810101,
4242
    CPU_POWERPC_82xx_HIP4   = 0x80811014,
4243
    CPU_POWERPC_827x        = 0x80822013,
4244
    /* PowerPC 6xx cores */
4245
    CPU_POWERPC_601         = 0x00010001,
4246
    CPU_POWERPC_601a        = 0x00010002,
4247
    CPU_POWERPC_602         = 0x00050100,
4248
    CPU_POWERPC_603         = 0x00030100,
4249
#define CPU_POWERPC_603E      CPU_POWERPC_603E_v41
4250
    CPU_POWERPC_603E_v11    = 0x00060101,
4251
    CPU_POWERPC_603E_v12    = 0x00060102,
4252
    CPU_POWERPC_603E_v13    = 0x00060103,
4253
    CPU_POWERPC_603E_v14    = 0x00060104,
4254
    CPU_POWERPC_603E_v22    = 0x00060202,
4255
    CPU_POWERPC_603E_v3     = 0x00060300,
4256
    CPU_POWERPC_603E_v4     = 0x00060400,
4257
    CPU_POWERPC_603E_v41    = 0x00060401,
4258
    CPU_POWERPC_603E7t      = 0x00071201,
4259
    CPU_POWERPC_603E7v      = 0x00070100,
4260
    CPU_POWERPC_603E7v1     = 0x00070101,
4261
    CPU_POWERPC_603E7v2     = 0x00070201,
4262
    CPU_POWERPC_603E7       = 0x00070200,
4263
    CPU_POWERPC_603P        = 0x00070000,
4264
#define CPU_POWERPC_603R      CPU_POWERPC_603E7t
4265
    CPU_POWERPC_G2          = 0x00810011,
4266
#if 0 // Linux pretends the MSB is zero...
4267
    CPU_POWERPC_G2H4        = 0x80811010,
4268
    CPU_POWERPC_G2gp        = 0x80821010,
4269
    CPU_POWERPC_G2ls        = 0x90810010,
4270
    CPU_POWERPC_G2LE        = 0x80820010,
4271
    CPU_POWERPC_G2LEgp      = 0x80822010,
4272
    CPU_POWERPC_G2LEls      = 0xA0822010,
4273
#else
4274
    CPU_POWERPC_G2H4        = 0x00811010,
4275
    CPU_POWERPC_G2gp        = 0x00821010,
4276
    CPU_POWERPC_G2ls        = 0x10810010,
4277
    CPU_POWERPC_G2LE        = 0x00820010,
4278
    CPU_POWERPC_G2LEgp      = 0x00822010,
4279
    CPU_POWERPC_G2LEls      = 0x20822010,
4280
#endif
4281
    CPU_POWERPC_604         = 0x00040103,
4282
#define CPU_POWERPC_604E      CPU_POWERPC_604E_v24
4283
    CPU_POWERPC_604E_v10    = 0x00090100, /* Also 2110 & 2120 */
4284
    CPU_POWERPC_604E_v22    = 0x00090202,
4285
    CPU_POWERPC_604E_v24    = 0x00090204,
4286
    CPU_POWERPC_604R        = 0x000a0101, /* Also 0x00093102 */
4287
#if 0
4288
    CPU_POWERPC_604EV       = xxx,
4289
#endif
4290
    /* PowerPC 740/750 cores (aka G3) */
4291
    /* XXX: missing 0x00084202 */
4292
#define CPU_POWERPC_7x0       CPU_POWERPC_7x0_v31
4293
    CPU_POWERPC_7x0_v20     = 0x00080200,
4294
    CPU_POWERPC_7x0_v21     = 0x00080201,
4295
    CPU_POWERPC_7x0_v22     = 0x00080202,
4296
    CPU_POWERPC_7x0_v30     = 0x00080300,
4297
    CPU_POWERPC_7x0_v31     = 0x00080301,
4298
    CPU_POWERPC_740E        = 0x00080100,
4299
    CPU_POWERPC_7x0P        = 0x10080000,
4300
    /* XXX: missing 0x00087010 (CL ?) */
4301
    CPU_POWERPC_750CL       = 0x00087200,
4302
#define CPU_POWERPC_750CX     CPU_POWERPC_750CX_v22
4303
    CPU_POWERPC_750CX_v21   = 0x00082201,
4304
    CPU_POWERPC_750CX_v22   = 0x00082202,
4305
#define CPU_POWERPC_750CXE    CPU_POWERPC_750CXE_v31b
4306
    CPU_POWERPC_750CXE_v21  = 0x00082211,
4307
    CPU_POWERPC_750CXE_v22  = 0x00082212,
4308
    CPU_POWERPC_750CXE_v23  = 0x00082213,
4309
    CPU_POWERPC_750CXE_v24  = 0x00082214,
4310
    CPU_POWERPC_750CXE_v24b = 0x00083214,
4311
    CPU_POWERPC_750CXE_v31  = 0x00083211,
4312
    CPU_POWERPC_750CXE_v31b = 0x00083311,
4313
    CPU_POWERPC_750CXR      = 0x00083410,
4314
    CPU_POWERPC_750E        = 0x00080200,
4315
    CPU_POWERPC_750FL       = 0x700A0203,
4316
#define CPU_POWERPC_750FX     CPU_POWERPC_750FX_v23
4317
    CPU_POWERPC_750FX_v10   = 0x70000100,
4318
    CPU_POWERPC_750FX_v20   = 0x70000200,
4319
    CPU_POWERPC_750FX_v21   = 0x70000201,
4320
    CPU_POWERPC_750FX_v22   = 0x70000202,
4321
    CPU_POWERPC_750FX_v23   = 0x70000203,
4322
    CPU_POWERPC_750GL       = 0x70020102,
4323
#define CPU_POWERPC_750GX     CPU_POWERPC_750GX_v12
4324
    CPU_POWERPC_750GX_v10   = 0x70020100,
4325
    CPU_POWERPC_750GX_v11   = 0x70020101,
4326
    CPU_POWERPC_750GX_v12   = 0x70020102,
4327
#define CPU_POWERPC_750L      CPU_POWERPC_750L_v32 /* Aka LoneStar */
4328
    CPU_POWERPC_750L_v22    = 0x00088202,
4329
    CPU_POWERPC_750L_v30    = 0x00088300,
4330
    CPU_POWERPC_750L_v32    = 0x00088302,
4331
    /* PowerPC 745/755 cores */
4332
#define CPU_POWERPC_7x5       CPU_POWERPC_7x5_v28
4333
    CPU_POWERPC_7x5_v10     = 0x00083100,
4334
    CPU_POWERPC_7x5_v11     = 0x00083101,
4335
    CPU_POWERPC_7x5_v20     = 0x00083200,
4336
    CPU_POWERPC_7x5_v21     = 0x00083201,
4337
    CPU_POWERPC_7x5_v22     = 0x00083202, /* aka D */
4338
    CPU_POWERPC_7x5_v23     = 0x00083203, /* aka E */
4339
    CPU_POWERPC_7x5_v24     = 0x00083204,
4340
    CPU_POWERPC_7x5_v25     = 0x00083205,
4341
    CPU_POWERPC_7x5_v26     = 0x00083206,
4342
    CPU_POWERPC_7x5_v27     = 0x00083207,
4343
    CPU_POWERPC_7x5_v28     = 0x00083208,
4344
#if 0
4345
    CPU_POWERPC_7x5P        = xxx,
4346
#endif
4347
    /* PowerPC 74xx cores (aka G4) */
4348
    /* XXX: missing 0x000C1101 */
4349
#define CPU_POWERPC_7400      CPU_POWERPC_7400_v29
4350
    CPU_POWERPC_7400_v10    = 0x000C0100,
4351
    CPU_POWERPC_7400_v11    = 0x000C0101,
4352
    CPU_POWERPC_7400_v20    = 0x000C0200,
4353
    CPU_POWERPC_7400_v22    = 0x000C0202,
4354
    CPU_POWERPC_7400_v26    = 0x000C0206,
4355
    CPU_POWERPC_7400_v27    = 0x000C0207,
4356
    CPU_POWERPC_7400_v28    = 0x000C0208,
4357
    CPU_POWERPC_7400_v29    = 0x000C0209,
4358
#define CPU_POWERPC_7410      CPU_POWERPC_7410_v14
4359
    CPU_POWERPC_7410_v10    = 0x800C1100,
4360
    CPU_POWERPC_7410_v11    = 0x800C1101,
4361
    CPU_POWERPC_7410_v12    = 0x800C1102, /* aka C */
4362
    CPU_POWERPC_7410_v13    = 0x800C1103, /* aka D */
4363
    CPU_POWERPC_7410_v14    = 0x800C1104, /* aka E */
4364
#define CPU_POWERPC_7448      CPU_POWERPC_7448_v21
4365
    CPU_POWERPC_7448_v10    = 0x80040100,
4366
    CPU_POWERPC_7448_v11    = 0x80040101,
4367
    CPU_POWERPC_7448_v20    = 0x80040200,
4368
    CPU_POWERPC_7448_v21    = 0x80040201,
4369
#define CPU_POWERPC_7450      CPU_POWERPC_7450_v21
4370
    CPU_POWERPC_7450_v10    = 0x80000100,
4371
    CPU_POWERPC_7450_v11    = 0x80000101,
4372
    CPU_POWERPC_7450_v12    = 0x80000102,
4373
    CPU_POWERPC_7450_v20    = 0x80000200, /* aka D: 2.04 */
4374
    CPU_POWERPC_7450_v21    = 0x80000201, /* aka E */
4375
    CPU_POWERPC_74x1        = 0x80000203,
4376
    CPU_POWERPC_74x1G       = 0x80000210, /* aka G: 2.3 */
4377
    /* XXX: missing 0x80010200 */
4378
#define CPU_POWERPC_74x5      CPU_POWERPC_74x5_v32
4379
    CPU_POWERPC_74x5_v10    = 0x80010100,
4380
    CPU_POWERPC_74x5_v21    = 0x80010201, /* aka C: 2.1 */
4381
    CPU_POWERPC_74x5_v32    = 0x80010302,
4382
    CPU_POWERPC_74x5_v33    = 0x80010303, /* aka F: 3.3 */
4383
    CPU_POWERPC_74x5_v34    = 0x80010304, /* aka G: 3.4 */
4384
#define CPU_POWERPC_74x7      CPU_POWERPC_74x7_v12
4385
    CPU_POWERPC_74x7_v10    = 0x80020100, /* aka A: 1.0 */
4386
    CPU_POWERPC_74x7_v11    = 0x80030101, /* aka B: 1.1 */
4387
    CPU_POWERPC_74x7_v12    = 0x80020102, /* aka C: 1.2 */
4388
    /* 64 bits PowerPC */
4389
    CPU_POWERPC_620         = 0x00140000,
4390
    CPU_POWERPC_630         = 0x00400000,
4391
    CPU_POWERPC_631         = 0x00410104,
4392
    CPU_POWERPC_POWER4      = 0x00350000,
4393
    CPU_POWERPC_POWER4P     = 0x00380000,
4394
    CPU_POWERPC_POWER5      = 0x003A0203,
4395
#define CPU_POWERPC_POWER5GR  CPU_POWERPC_POWER5
4396
    CPU_POWERPC_POWER5P     = 0x003B0000,
4397
#define CPU_POWERPC_POWER5GS  CPU_POWERPC_POWER5P
4398
    CPU_POWERPC_POWER6      = 0x003E0000,
4399
    CPU_POWERPC_POWER6_5    = 0x0F000001, /* POWER6 running POWER5 mode */
4400
    CPU_POWERPC_POWER6A     = 0x0F000002,
4401
    CPU_POWERPC_970         = 0x00390202,
4402
#define CPU_POWERPC_970FX     CPU_POWERPC_970FX_v31
4403
    CPU_POWERPC_970FX_v10   = 0x00391100,
4404
    CPU_POWERPC_970FX_v20   = 0x003C0200,
4405
    CPU_POWERPC_970FX_v21   = 0x003C0201,
4406
    CPU_POWERPC_970FX_v30   = 0x003C0300,
4407
    CPU_POWERPC_970FX_v31   = 0x003C0301,
4408
    CPU_POWERPC_970GX       = 0x00450000,
4409
#define CPU_POWERPC_970MP     CPU_POWERPC_970MP_v11
4410
    CPU_POWERPC_970MP_v10   = 0x00440100,
4411
    CPU_POWERPC_970MP_v11   = 0x00440101,
4412
#define CPU_POWERPC_CELL      CPU_POWERPC_CELL_v32
4413
    CPU_POWERPC_CELL_v10    = 0x00700100,
4414
    CPU_POWERPC_CELL_v20    = 0x00700400,
4415
    CPU_POWERPC_CELL_v30    = 0x00700500,
4416
    CPU_POWERPC_CELL_v31    = 0x00700501,
4417
#define CPU_POWERPC_CELL_v32  CPU_POWERPC_CELL_v31
4418
    CPU_POWERPC_RS64        = 0x00330000,
4419
    CPU_POWERPC_RS64II      = 0x00340000,
4420
    CPU_POWERPC_RS64III     = 0x00360000,
4421
    CPU_POWERPC_RS64IV      = 0x00370000,
4422
    /* Original POWER */
4423
    /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4424
     * POWER2 (RIOS2) & RSC2 (P2SC) here
4425
     */
4426
#if 0
4427
    CPU_POWER           = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4428
#endif
4429
#if 0
4430
    CPU_POWER2          = xxx, /* 0x40000 ? */
4431
#endif
4432
    /* PA Semi core */
4433
    CPU_POWERPC_PA6T        = 0x00900000,
4434
};
4435

    
4436
/* System version register (used on MPC 8xxx)                                */
4437
enum {
4438
    PPC_SVR_8540      = 0x80300000,
4439
    PPC_SVR_8541E     = 0x807A0010,
4440
    PPC_SVR_8543v10   = 0x80320010,
4441
    PPC_SVR_8543v11   = 0x80320011,
4442
    PPC_SVR_8543v20   = 0x80320020,
4443
    PPC_SVR_8543Ev10  = 0x803A0010,
4444
    PPC_SVR_8543Ev11  = 0x803A0011,
4445
    PPC_SVR_8543Ev20  = 0x803A0020,
4446
    PPC_SVR_8545      = 0x80310220,
4447
    PPC_SVR_8545E     = 0x80390220,
4448
    PPC_SVR_8547E     = 0x80390120,
4449
    PPC_SCR_8548v10   = 0x80310010,
4450
    PPC_SCR_8548v11   = 0x80310011,
4451
    PPC_SCR_8548v20   = 0x80310020,
4452
    PPC_SVR_8548Ev10  = 0x80390010,
4453
    PPC_SVR_8548Ev11  = 0x80390011,
4454
    PPC_SVR_8548Ev20  = 0x80390020,
4455
    PPC_SVR_8555E     = 0x80790010,
4456
    PPC_SVR_8560v10   = 0x80700010,
4457
    PPC_SVR_8560v20   = 0x80700020,
4458
};
4459

    
4460
/*****************************************************************************/
4461
/* PowerPC CPU definitions                                                   */
4462
#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type)                            \
4463
    {                                                                         \
4464
        .name        = _name,                                                 \
4465
        .pvr         = _pvr,                                                  \
4466
        .pvr_mask    = _pvr_mask,                                             \
4467
        .insns_flags = glue(POWERPC_INSNS_,_type),                            \
4468
        .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
4469
        .mmu_model   = glue(POWERPC_MMU_,_type),                              \
4470
        .excp_model  = glue(POWERPC_EXCP_,_type),                             \
4471
        .bus_model   = glue(POWERPC_INPUT_,_type),                            \
4472
        .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
4473
        .init_proc   = &glue(init_proc_,_type),                               \
4474
    }
4475

    
4476
static ppc_def_t ppc_defs[] = {
4477
    /* Embedded PowerPC                                                      */
4478
    /* PowerPC 401 family                                                    */
4479
    /* Generic PowerPC 401 */
4480
    POWERPC_DEF("401",         CPU_POWERPC_401,         0xFFFF0000, 401),
4481
    /* PowerPC 401 cores                                                     */
4482
    /* PowerPC 401A1 */
4483
    POWERPC_DEF("401A1",       CPU_POWERPC_401A1,       0xFFFFFFFF, 401),
4484
    /* PowerPC 401B2                                                         */
4485
    POWERPC_DEF("401B2",       CPU_POWERPC_401B2,       0xFFFFFFFF, 401x2),
4486
#if defined (TODO)
4487
    /* PowerPC 401B3                                                         */
4488
    POWERPC_DEF("401B3",       CPU_POWERPC_401B3,       0xFFFFFFFF, 401x3),
4489
#endif
4490
    /* PowerPC 401C2                                                         */
4491
    POWERPC_DEF("401C2",       CPU_POWERPC_401C2,       0xFFFFFFFF, 401x2),
4492
    /* PowerPC 401D2                                                         */
4493
    POWERPC_DEF("401D2",       CPU_POWERPC_401D2,       0xFFFFFFFF, 401x2),
4494
    /* PowerPC 401E2                                                         */
4495
    POWERPC_DEF("401E2",       CPU_POWERPC_401E2,       0xFFFFFFFF, 401x2),
4496
    /* PowerPC 401F2                                                         */
4497
    POWERPC_DEF("401F2",       CPU_POWERPC_401F2,       0xFFFFFFFF, 401x2),
4498
    /* PowerPC 401G2                                                         */
4499
    /* XXX: to be checked */
4500
    POWERPC_DEF("401G2",       CPU_POWERPC_401G2,       0xFFFFFFFF, 401x2),
4501
    /* PowerPC 401 microcontrolers                                           */
4502
#if defined (TODO)
4503
    /* PowerPC 401GF                                                         */
4504
    POWERPC_DEF("401GF",       CPU_POWERPC_401GF,       0xFFFFFFFF, 401),
4505
#endif
4506
    /* IOP480 (401 microcontroler)                                           */
4507
    POWERPC_DEF("IOP480",      CPU_POWERPC_IOP480,      0xFFFFFFFF, IOP480),
4508
    /* IBM Processor for Network Resources                                   */
4509
    POWERPC_DEF("Cobra",       CPU_POWERPC_COBRA,       0xFFFFFFFF, 401),
4510
#if defined (TODO)
4511
    POWERPC_DEF("Xipchip",     CPU_POWERPC_XIPCHIP,     0xFFFFFFFF, 401),
4512
#endif
4513
    /* PowerPC 403 family                                                    */
4514
    /* Generic PowerPC 403                                                   */
4515
    POWERPC_DEF("403",         CPU_POWERPC_403,         0xFFFF0000, 403),
4516
    /* PowerPC 403 microcontrolers                                           */
4517
    /* PowerPC 403 GA                                                        */
4518
    POWERPC_DEF("403GA",       CPU_POWERPC_403GA,       0xFFFFFFFF, 403),
4519
    /* PowerPC 403 GB                                                        */
4520
    POWERPC_DEF("403GB",       CPU_POWERPC_403GB,       0xFFFFFFFF, 403),
4521
    /* PowerPC 403 GC                                                        */
4522
    POWERPC_DEF("403GC",       CPU_POWERPC_403GC,       0xFFFFFFFF, 403),
4523
    /* PowerPC 403 GCX                                                       */
4524
    POWERPC_DEF("403GCX",      CPU_POWERPC_403GCX,      0xFFFFFFFF, 403GCX),
4525
#if defined (TODO)
4526
    /* PowerPC 403 GP                                                        */
4527
    POWERPC_DEF("403GP",       CPU_POWERPC_403GP,       0xFFFFFFFF, 403),
4528
#endif
4529
    /* PowerPC 405 family                                                    */
4530
    /* Generic PowerPC 405                                                   */
4531
    POWERPC_DEF("405",         CPU_POWERPC_405,         0xFFFF0000, 405),
4532
    /* PowerPC 405 cores                                                     */
4533
#if defined (TODO)
4534
    /* PowerPC 405 A3                                                        */
4535
    POWERPC_DEF("405A3",       CPU_POWERPC_405A3,       0xFFFFFFFF, 405),
4536
#endif
4537
#if defined (TODO)
4538
    /* PowerPC 405 A4                                                        */
4539
    POWERPC_DEF("405A4",       CPU_POWERPC_405A4,       0xFFFFFFFF, 405),
4540
#endif
4541
#if defined (TODO)
4542
    /* PowerPC 405 B3                                                        */
4543
    POWERPC_DEF("405B3",       CPU_POWERPC_405B3,       0xFFFFFFFF, 405),
4544
#endif
4545
#if defined (TODO)
4546
    /* PowerPC 405 B4                                                        */
4547
    POWERPC_DEF("405B4",       CPU_POWERPC_405B4,       0xFFFFFFFF, 405),
4548
#endif
4549
#if defined (TODO)
4550
    /* PowerPC 405 C3                                                        */
4551
    POWERPC_DEF("405C3",       CPU_POWERPC_405C3,       0xFFFFFFFF, 405),
4552
#endif
4553
#if defined (TODO)
4554
    /* PowerPC 405 C4                                                        */
4555
    POWERPC_DEF("405C4",       CPU_POWERPC_405C4,       0xFFFFFFFF, 405),
4556
#endif
4557
    /* PowerPC 405 D2                                                        */
4558
    POWERPC_DEF("405D2",       CPU_POWERPC_405D2,       0xFFFFFFFF, 405),
4559
#if defined (TODO)
4560
    /* PowerPC 405 D3                                                        */
4561
    POWERPC_DEF("405D3",       CPU_POWERPC_405D3,       0xFFFFFFFF, 405),
4562
#endif
4563
    /* PowerPC 405 D4                                                        */
4564
    POWERPC_DEF("405D4",       CPU_POWERPC_405D4,       0xFFFFFFFF, 405),
4565
#if defined (TODO)
4566
    /* PowerPC 405 D5                                                        */
4567
    POWERPC_DEF("405D5",       CPU_POWERPC_405D5,       0xFFFFFFFF, 405),
4568
#endif
4569
#if defined (TODO)
4570
    /* PowerPC 405 E4                                                        */
4571
    POWERPC_DEF("405E4",       CPU_POWERPC_405E4,       0xFFFFFFFF, 405),
4572
#endif
4573
#if defined (TODO)
4574
    /* PowerPC 405 F4                                                        */
4575
    POWERPC_DEF("405F4",       CPU_POWERPC_405F4,       0xFFFFFFFF, 405),
4576
#endif
4577
#if defined (TODO)
4578
    /* PowerPC 405 F5                                                        */
4579
    POWERPC_DEF("405F5",       CPU_POWERPC_405F5,       0xFFFFFFFF, 405),
4580
#endif
4581
#if defined (TODO)
4582
    /* PowerPC 405 F6                                                        */
4583
    POWERPC_DEF("405F6",       CPU_POWERPC_405F6,       0xFFFFFFFF, 405),
4584
#endif
4585
    /* PowerPC 405 microcontrolers                                           */
4586
    /* PowerPC 405 CR                                                        */
4587
    POWERPC_DEF("405CR",       CPU_POWERPC_405CR,       0xFFFFFFFF, 405),
4588
    /* PowerPC 405 CRa                                                       */
4589
    POWERPC_DEF("405CRa",      CPU_POWERPC_405CRa,      0xFFFFFFFF, 405),
4590
    /* PowerPC 405 CRb                                                       */
4591
    POWERPC_DEF("405CRb",      CPU_POWERPC_405CRb,      0xFFFFFFFF, 405),
4592
    /* PowerPC 405 CRc                                                       */
4593
    POWERPC_DEF("405CRc",      CPU_POWERPC_405CRc,      0xFFFFFFFF, 405),
4594
    /* PowerPC 405 EP                                                        */
4595
    POWERPC_DEF("405EP",       CPU_POWERPC_405EP,       0xFFFFFFFF, 405),
4596
#if defined(TODO)
4597
    /* PowerPC 405 EXr                                                       */
4598
    POWERPC_DEF("405EXr",      CPU_POWERPC_405EXr,      0xFFFFFFFF, 405),
4599
#endif
4600
    /* PowerPC 405 EZ                                                        */
4601
    POWERPC_DEF("405EZ",       CPU_POWERPC_405EZ,       0xFFFFFFFF, 405),
4602
#if defined(TODO)
4603
    /* PowerPC 405 FX                                                        */
4604
    POWERPC_DEF("405FX",       CPU_POWERPC_405FX,       0xFFFFFFFF, 405),
4605
#endif
4606
    /* PowerPC 405 GP                                                        */
4607
    POWERPC_DEF("405GP",       CPU_POWERPC_405GP,       0xFFFFFFFF, 405),
4608
    /* PowerPC 405 GPa                                                       */
4609
    POWERPC_DEF("405GPa",      CPU_POWERPC_405GPa,      0xFFFFFFFF, 405),
4610
    /* PowerPC 405 GPb                                                       */
4611
    POWERPC_DEF("405GPb",      CPU_POWERPC_405GPb,      0xFFFFFFFF, 405),
4612
    /* PowerPC 405 GPc                                                       */
4613
    POWERPC_DEF("405GPc",      CPU_POWERPC_405GPc,      0xFFFFFFFF, 405),
4614
    /* PowerPC 405 GPd                                                       */
4615
    POWERPC_DEF("405GPd",      CPU_POWERPC_405GPd,      0xFFFFFFFF, 405),
4616
    /* PowerPC 405 GPe                                                       */
4617
    POWERPC_DEF("405GPe",      CPU_POWERPC_405GPe,      0xFFFFFFFF, 405),
4618
    /* PowerPC 405 GPR                                                       */
4619
    POWERPC_DEF("405GPR",      CPU_POWERPC_405GPR,      0xFFFFFFFF, 405),
4620
#if defined(TODO)
4621
    /* PowerPC 405 H                                                         */
4622
    POWERPC_DEF("405H",        CPU_POWERPC_405H,        0xFFFFFFFF, 405),
4623
#endif
4624
#if defined(TODO)
4625
    /* PowerPC 405 L                                                         */
4626
    POWERPC_DEF("405L",        CPU_POWERPC_405L,        0xFFFFFFFF, 405),
4627
#endif
4628
    /* PowerPC 405 LP                                                        */
4629
    POWERPC_DEF("405LP",       CPU_POWERPC_405LP,       0xFFFFFFFF, 405),
4630
#if defined(TODO)
4631
    /* PowerPC 405 PM                                                        */
4632
    POWERPC_DEF("405PM",       CPU_POWERPC_405PM,       0xFFFFFFFF, 405),
4633
#endif
4634
#if defined(TODO)
4635
    /* PowerPC 405 PS                                                        */
4636
    POWERPC_DEF("405PS",       CPU_POWERPC_405PS,       0xFFFFFFFF, 405),
4637
#endif
4638
#if defined(TODO)
4639
    /* PowerPC 405 S                                                         */
4640
    POWERPC_DEF("405S",        CPU_POWERPC_405S,        0xFFFFFFFF, 405),
4641
#endif
4642
    /* Npe405 H                                                              */
4643
    POWERPC_DEF("Npe405H",     CPU_POWERPC_NPE405H,     0xFFFFFFFF, 405),
4644
    /* Npe405 H2                                                             */
4645
    POWERPC_DEF("Npe405H2",    CPU_POWERPC_NPE405H2,    0xFFFFFFFF, 405),
4646
    /* Npe405 L                                                              */
4647
    POWERPC_DEF("Npe405L",     CPU_POWERPC_NPE405L,     0xFFFFFFFF, 405),
4648
    /* Npe4GS3                                                               */
4649
    POWERPC_DEF("Npe4GS3",     CPU_POWERPC_NPE4GS3,     0xFFFFFFFF, 405),
4650
#if defined (TODO)
4651
    POWERPC_DEF("Npcxx1",      CPU_POWERPC_NPCxx1,      0xFFFFFFFF, 405),
4652
#endif
4653
#if defined (TODO)
4654
    POWERPC_DEF("Npr161",      CPU_POWERPC_NPR161,      0xFFFFFFFF, 405),
4655
#endif
4656
#if defined (TODO)
4657
    /* PowerPC LC77700 (Sanyo)                                               */
4658
    POWERPC_DEF("LC77700",     CPU_POWERPC_LC77700,     0xFFFFFFFF, 405),
4659
#endif
4660
    /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
4661
#if defined (TODO)
4662
    /* STB010000                                                             */
4663
    POWERPC_DEF("STB01000",    CPU_POWERPC_STB01000,    0xFFFFFFFF, 401x2),
4664
#endif
4665
#if defined (TODO)
4666
    /* STB01010                                                              */
4667
    POWERPC_DEF("STB01010",    CPU_POWERPC_STB01010,    0xFFFFFFFF, 401x2),
4668
#endif
4669
#if defined (TODO)
4670
    /* STB0210                                                               */
4671
    POWERPC_DEF("STB0210",     CPU_POWERPC_STB0210,     0xFFFFFFFF, 401x3),