Revision e189e748 target-mips/op.c

b/target-mips/op.c
1847 1847
        (val & (1 << CP0St_UM)))
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        env->hflags |= MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
1850
    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
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        ((env->hflags & MIPS_HFLAG_UM) &&
1850
    if  ((env->hflags & MIPS_HFLAG_UM) &&
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        !(val & (1 << CP0St_PX)) &&
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        !(val & (1 << CP0St_UX))))
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        !(val & (1 << CP0St_UX)))
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        env->hflags &= ~MIPS_HFLAG_64;
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#endif
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    if (val & (1 << CP0St_CU1))
......
1906 1905
{
1907 1906
    uint32_t mask = 0x00C00300;
1908 1907

  
1909
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
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    if (env->insn_flags & ISA_MIPS32R2)
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        mask |= 1 << CP0Ca_DC;
1911 1910

  
1912 1911
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
......
3014 3013
        (env->CP0_Status & (1 << CP0St_UM)))
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        env->hflags |= MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
3017
    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
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        ((env->hflags & MIPS_HFLAG_UM) &&
3016
     if ((env->hflags & MIPS_HFLAG_UM) &&
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        !(env->CP0_Status & (1 << CP0St_PX)) &&
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        !(env->CP0_Status & (1 << CP0St_UX))))
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        !(env->CP0_Status & (1 << CP0St_UX)))
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        env->hflags &= ~MIPS_HFLAG_64;
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#endif
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    if (loglevel & CPU_LOG_EXEC)
......
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        (env->CP0_Status & (1 << CP0St_UM)))
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        env->hflags |= MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
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    if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
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        ((env->hflags & MIPS_HFLAG_UM) &&
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    if ((env->hflags & MIPS_HFLAG_UM) &&
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        !(env->CP0_Status & (1 << CP0St_PX)) &&
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        !(env->CP0_Status & (1 << CP0St_UX))))
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        !(env->CP0_Status & (1 << CP0St_UX)))
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        env->hflags &= ~MIPS_HFLAG_64;
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#endif
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    if (loglevel & CPU_LOG_EXEC)

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