Revision e189e748 target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
|---|---|---|
| 80 | 80 |
int32_t CP0_SRSConf3; |
| 81 | 81 |
int32_t CP0_SRSConf4_rw_bitmask; |
| 82 | 82 |
int32_t CP0_SRSConf4; |
| 83 |
int insn_flags; |
|
| 83 | 84 |
}; |
| 84 | 85 |
|
| 85 | 86 |
/*****************************************************************************/ |
| ... | ... | |
| 98 | 99 |
.SYNCI_Step = 32, |
| 99 | 100 |
.CCRes = 2, |
| 100 | 101 |
.CP0_Status_rw_bitmask = 0x1278FF17, |
| 102 |
.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
|
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}, |
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{
|
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.name = "4KEcR1", |
| ... | ... | |
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.SYNCI_Step = 32, |
| 112 | 114 |
.CCRes = 2, |
| 113 | 115 |
.CP0_Status_rw_bitmask = 0x1278FF17, |
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.insn_flags = CPU_MIPS32 | ASE_MIPS16, |
|
| 114 | 117 |
}, |
| 115 | 118 |
{
|
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.name = "4KEc", |
| ... | ... | |
| 124 | 127 |
.SYNCI_Step = 32, |
| 125 | 128 |
.CCRes = 2, |
| 126 | 129 |
.CP0_Status_rw_bitmask = 0x1278FF17, |
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
|
| 127 | 131 |
}, |
| 128 | 132 |
{
|
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.name = "24Kc", |
| ... | ... | |
| 138 | 142 |
.CCRes = 2, |
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/* No DSP implemented. */ |
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.CP0_Status_rw_bitmask = 0x1278FF17, |
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, |
|
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}, |
| 142 | 147 |
{
|
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.name = "24Kf", |
| ... | ... | |
| 154 | 159 |
.CP0_Status_rw_bitmask = 0x3678FF17, |
| 155 | 160 |
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 156 | 161 |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
| 162 |
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, |
|
| 157 | 163 |
}, |
| 158 | 164 |
{
|
| 159 | 165 |
.name = "34Kf", |
| ... | ... | |
| 193 | 199 |
.CP0_SRSConf4_rw_bitmask = 0x3fffffff, |
| 194 | 200 |
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | |
| 195 | 201 |
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, |
|
| 196 | 203 |
}, |
| 197 | 204 |
#ifdef TARGET_MIPS64 |
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{
|
| ... | ... | |
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/* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */ |
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.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 212 | 219 |
.SEGBITS = 40, |
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.insn_flags = CPU_MIPS3, |
|
| 213 | 221 |
}, |
| 214 | 222 |
{
|
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.name = "5Kc", |
| ... | ... | |
| 225 | 233 |
.CCRes = 2, |
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.CP0_Status_rw_bitmask = 0x32F8FFFF, |
| 227 | 235 |
.SEGBITS = 42, |
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.insn_flags = CPU_MIPS64, |
|
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}, |
| 229 | 238 |
{
|
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.name = "5Kf", |
| ... | ... | |
| 243 | 252 |
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
| 244 | 253 |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 245 | 254 |
.SEGBITS = 42, |
| 255 |
.insn_flags = CPU_MIPS64, |
|
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}, |
| 247 | 257 |
{
|
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.name = "20Kc", |
| ... | ... | |
| 264 | 274 |
(1 << FCR0_D) | (1 << FCR0_S) | |
| 265 | 275 |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 266 | 276 |
.SEGBITS = 40, |
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.insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
|
| 267 | 278 |
}, |
| 268 | 279 |
#endif |
| 269 | 280 |
}; |
| ... | ... | |
| 406 | 417 |
env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask; |
| 407 | 418 |
env->CP0_SRSCtl = def->CP0_SRSCtl; |
| 408 | 419 |
#ifdef TARGET_MIPS64 |
| 409 |
if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
|
|
| 420 |
if (def->insn_flags & ISA_MIPS3)
|
|
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{
|
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env->hflags |= MIPS_HFLAG_64; |
| 412 | 423 |
env->SEGBITS = def->SEGBITS; |
| ... | ... | |
| 426 | 437 |
env->CP0_SRSConf3 = def->CP0_SRSConf3; |
| 427 | 438 |
env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask; |
| 428 | 439 |
env->CP0_SRSConf4 = def->CP0_SRSConf4; |
| 440 |
env->insn_flags = def->insn_flags; |
|
| 429 | 441 |
|
| 430 | 442 |
#ifndef CONFIG_USER_ONLY |
| 431 | 443 |
mmu_init(env, def); |
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