| 35 |
35 |
struct m48t59_t {
|
| 36 |
36 |
/* Hardware parameters */
|
| 37 |
37 |
int IRQ;
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|
38 |
int mem_index;
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|
39 |
uint32_t mem_base;
|
| 38 |
40 |
uint32_t io_base;
|
| 39 |
41 |
uint16_t size;
|
| 40 |
42 |
/* RTC management */
|
| ... | ... | |
| 481 |
483 |
return retval;
|
| 482 |
484 |
}
|
| 483 |
485 |
|
|
486 |
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
487 |
{
|
|
488 |
m48t59_t *NVRAM = opaque;
|
|
489 |
|
|
490 |
addr -= NVRAM->mem_base;
|
|
491 |
if (addr < 0x1FF0)
|
|
492 |
NVRAM->buffer[addr] = value;
|
|
493 |
}
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|
494 |
|
|
495 |
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
496 |
{
|
|
497 |
m48t59_t *NVRAM = opaque;
|
|
498 |
|
|
499 |
addr -= NVRAM->mem_base;
|
|
500 |
if (addr < 0x1FF0) {
|
|
501 |
NVRAM->buffer[addr] = value >> 8;
|
|
502 |
NVRAM->buffer[addr + 1] = value;
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|
503 |
}
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|
504 |
}
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|
505 |
|
|
506 |
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
507 |
{
|
|
508 |
m48t59_t *NVRAM = opaque;
|
|
509 |
|
|
510 |
addr -= NVRAM->mem_base;
|
|
511 |
if (addr < 0x1FF0) {
|
|
512 |
NVRAM->buffer[addr] = value >> 24;
|
|
513 |
NVRAM->buffer[addr + 1] = value >> 16;
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|
514 |
NVRAM->buffer[addr + 2] = value >> 8;
|
|
515 |
NVRAM->buffer[addr + 3] = value;
|
|
516 |
}
|
|
517 |
}
|
|
518 |
|
|
519 |
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
|
|
520 |
{
|
|
521 |
m48t59_t *NVRAM = opaque;
|
|
522 |
uint32_t retval = 0;
|
|
523 |
|
|
524 |
addr -= NVRAM->mem_base;
|
|
525 |
if (addr < 0x1FF0)
|
|
526 |
retval = NVRAM->buffer[addr];
|
|
527 |
|
|
528 |
return retval;
|
|
529 |
}
|
|
530 |
|
|
531 |
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
|
|
532 |
{
|
|
533 |
m48t59_t *NVRAM = opaque;
|
|
534 |
uint32_t retval = 0;
|
|
535 |
|
|
536 |
addr -= NVRAM->mem_base;
|
|
537 |
if (addr < 0x1FF0) {
|
|
538 |
retval = NVRAM->buffer[addr] << 8;
|
|
539 |
retval |= NVRAM->buffer[addr + 1];
|
|
540 |
}
|
|
541 |
|
|
542 |
return retval;
|
|
543 |
}
|
|
544 |
|
|
545 |
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
|
|
546 |
{
|
|
547 |
m48t59_t *NVRAM = opaque;
|
|
548 |
uint32_t retval = 0;
|
|
549 |
|
|
550 |
addr -= NVRAM->mem_base;
|
|
551 |
if (addr < 0x1FF0) {
|
|
552 |
retval = NVRAM->buffer[addr] << 24;
|
|
553 |
retval |= NVRAM->buffer[addr + 1] << 16;
|
|
554 |
retval |= NVRAM->buffer[addr + 2] << 8;
|
|
555 |
retval |= NVRAM->buffer[addr + 3];
|
|
556 |
}
|
|
557 |
|
|
558 |
return retval;
|
|
559 |
}
|
|
560 |
|
|
561 |
static CPUWriteMemoryFunc *nvram_write[] = {
|
|
562 |
&nvram_writeb,
|
|
563 |
&nvram_writew,
|
|
564 |
&nvram_writel,
|
|
565 |
};
|
|
566 |
|
|
567 |
static CPUReadMemoryFunc *nvram_read[] = {
|
|
568 |
&nvram_readb,
|
|
569 |
&nvram_readw,
|
|
570 |
&nvram_readl,
|
|
571 |
};
|
| 484 |
572 |
/* Initialisation routine */
|
| 485 |
|
m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
|
|
573 |
m48t59_t *m48t59_init (int IRQ, uint32_t mem_base,
|
|
574 |
uint32_t io_base, uint16_t size)
|
| 486 |
575 |
{
|
| 487 |
576 |
m48t59_t *s;
|
| 488 |
577 |
|
| ... | ... | |
| 496 |
585 |
}
|
| 497 |
586 |
s->IRQ = IRQ;
|
| 498 |
587 |
s->size = size;
|
|
588 |
s->mem_base = mem_base;
|
| 499 |
589 |
s->io_base = io_base;
|
| 500 |
590 |
s->addr = 0;
|
| 501 |
591 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
|
| 502 |
592 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
|
|
593 |
if (mem_base != 0) {
|
|
594 |
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
|
595 |
cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
|
|
596 |
}
|
| 503 |
597 |
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
|
| 504 |
598 |
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
|
| 505 |
599 |
s->lock = 0;
|