Revision e1c6bbab

b/Makefile.target
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# OldWorld PowerMac
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obj-ppc-y += heathrow_pic.o grackle_pci.o ppc_oldworld.o
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# NewWorld PowerMac
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obj-ppc-y += unin_pci.o ppc_newworld.o
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obj-ppc-y += unin_pci.o ppc_newworld.o dec_pci.o
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# PowerPC 4xx boards
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obj-ppc-y += pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
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obj-ppc-y += ppc440.o ppc440_bamboo.o
b/hw/dec_pci.c
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/*
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 * QEMU DEC 21154 PCI bridge
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 *
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 * Copyright (c) 2006-2007 Fabrice Bellard
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 * Copyright (c) 2007 Jocelyn Mayer
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "sysbus.h"
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#include "pci.h"
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#include "pci_host.h"
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/* debug DEC */
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//#define DEBUG_DEC
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#ifdef DEBUG_DEC
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#define DEC_DPRINTF(fmt, ...)                               \
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    do { printf("DEC: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DEC_DPRINTF(fmt, ...)
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#endif
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typedef struct DECState {
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    SysBusDevice busdev;
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    PCIHostState host_state;
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} DECState;
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static int pci_dec_21154_init_device(SysBusDevice *dev)
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{
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    DECState *s;
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    int pci_mem_config, pci_mem_data;
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    s = FROM_SYSBUS(DECState, dev);
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    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
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    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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    return 0;
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}
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static int dec_21154_pci_host_init(PCIDevice *d)
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{
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    /* PCI2PCI bridge same values as PearPC - check this */
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
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    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
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    d->config[0x08] = 0x02; // revision
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    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
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    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
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    return 0;
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}
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static PCIDeviceInfo dec_21154_pci_host_info = {
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    .qdev.name = "dec-21154",
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    .qdev.size = sizeof(PCIDevice),
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    .init      = dec_21154_pci_host_init,
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    .header_type  = PCI_HEADER_TYPE_BRIDGE,
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};
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static void dec_register_devices(void)
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{
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    sysbus_register_dev("dec-21154", sizeof(DECState),
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                        pci_dec_21154_init_device);
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    pci_qdev_register(&dec_21154_pci_host_info);
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}
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device_init(dec_register_devices)
b/hw/grackle_pci.c
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    return 0;
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}
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static int pci_dec_21154_init_device(SysBusDevice *dev)
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{
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    GrackleState *s;
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    int pci_mem_config, pci_mem_data;
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    s = FROM_SYSBUS(GrackleState, dev);
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    pci_mem_config = pci_host_conf_register_mmio(&s->host_state);
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    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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    return 0;
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}
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static int grackle_pci_host_init(PCIDevice *d)
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{
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
......
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    return 0;
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}
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static int dec_21154_pci_host_init(PCIDevice *d)
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{
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    /* PCI2PCI bridge same values as PearPC - check this */
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
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    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
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    d->config[0x08] = 0x02; // revision
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    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
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    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
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    d->config[0x18] = 0x0;  // primary_bus
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    d->config[0x19] = 0x1;  // secondary_bus
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    d->config[0x1a] = 0x1;  // subordinate_bus
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    d->config[0x1c] = 0x10; // io_base
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    d->config[0x1d] = 0x20; // io_limit
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    d->config[0x20] = 0x80; // memory_base
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    d->config[0x21] = 0x80;
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    d->config[0x22] = 0x90; // memory_limit
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    d->config[0x23] = 0x80;
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    d->config[0x24] = 0x00; // prefetchable_memory_base
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    d->config[0x25] = 0x84;
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    d->config[0x26] = 0x00; // prefetchable_memory_limit
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    d->config[0x27] = 0x85;
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    return 0;
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}
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static PCIDeviceInfo grackle_pci_host_info = {
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    .qdev.name = "grackle",
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    .qdev.size = sizeof(PCIDevice),
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    .init      = grackle_pci_host_init,
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};
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static PCIDeviceInfo dec_21154_pci_host_info = {
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    .qdev.name = "dec-21154",
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    .qdev.size = sizeof(PCIDevice),
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    .init      = dec_21154_pci_host_init,
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    .header_type  = PCI_HEADER_TYPE_BRIDGE,
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};
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static void grackle_register_devices(void)
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{
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    sysbus_register_dev("grackle", sizeof(GrackleState),
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                        pci_grackle_init_device);
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    pci_qdev_register(&grackle_pci_host_info);
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    sysbus_register_dev("dec-21154", sizeof(GrackleState),
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                        pci_dec_21154_init_device);
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    pci_qdev_register(&dec_21154_pci_host_info);
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}
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device_init(grackle_register_devices)
b/hw/unin_pci.c
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    return 0;
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}
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static int pci_dec_21154_init_device(SysBusDevice *dev)
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{
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    UNINState *s;
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    int pci_mem_config, pci_mem_data;
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    /* Uninorth bridge */
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    s = FROM_SYSBUS(UNINState, dev);
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    // XXX: s = &pci_bridge[2];
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    pci_mem_config = pci_host_conf_register_mmio_noswap(&s->host_state);
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    pci_mem_data = pci_host_data_register_mmio(&s->host_state);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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    return 0;
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}
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static int pci_unin_agp_init_device(SysBusDevice *dev)
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{
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    UNINState *s;
......
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    return 0;
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}
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static int dec_21154_pci_host_init(PCIDevice *d)
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{
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    /* pci-to-pci bridge */
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
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    pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
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    d->config[0x08] = 0x05; // revision
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    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
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    d->config[0x0C] = 0x08; // cache_line_size
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    d->config[0x0D] = 0x20; // latency_timer
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    d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
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    d->config[0x18] = 0x01; // primary_bus
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    d->config[0x19] = 0x02; // secondary_bus
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    d->config[0x1A] = 0x02; // subordinate_bus
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    d->config[0x1B] = 0x20; // secondary_latency_timer
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    d->config[0x1C] = 0x11; // io_base
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    d->config[0x1D] = 0x01; // io_limit
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    d->config[0x20] = 0x00; // memory_base
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    d->config[0x21] = 0x80;
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    d->config[0x22] = 0x00; // memory_limit
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    d->config[0x23] = 0x80;
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    d->config[0x24] = 0x01; // prefetchable_memory_base
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    d->config[0x25] = 0x80;
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    d->config[0x26] = 0xF1; // prefectchable_memory_limit
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    d->config[0x27] = 0x7F;
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    // d->config[0x34] = 0xdc // capabilities_pointer
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    return 0;
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}
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static int unin_agp_pci_host_init(PCIDevice *d)
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{
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    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
......
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    .init      = unin_main_pci_host_init,
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};
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static PCIDeviceInfo dec_21154_pci_host_info = {
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    .qdev.name = "dec-21154",
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    .qdev.size = sizeof(PCIDevice),
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    .init      = dec_21154_pci_host_init,
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    .header_type  = PCI_HEADER_TYPE_BRIDGE,
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};
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static PCIDeviceInfo unin_agp_pci_host_info = {
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    .qdev.name = "uni-north-agp",
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    .qdev.size = sizeof(PCIDevice),
......
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    sysbus_register_dev("uni-north", sizeof(UNINState),
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                        pci_unin_main_init_device);
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    pci_qdev_register(&unin_main_pci_host_info);
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    sysbus_register_dev("dec-21154", sizeof(UNINState),
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                        pci_dec_21154_init_device);
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    pci_qdev_register(&dec_21154_pci_host_info);
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    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
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                        pci_unin_agp_init_device);
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    pci_qdev_register(&unin_agp_pci_host_info);

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