Revision e1d177b9 target-arm/translate.c

b/target-arm/translate.c
7038 7038
                        if (insn & (1 << 5))
7039 7039
                            gen_swap_half(tmp2);
7040 7040
                        gen_smul_dual(tmp, tmp2);
7041
                        /* This addition cannot overflow.  */
7042 7041
                        if (insn & (1 << 6)) {
7042
                            /* This subtraction cannot overflow. */
7043 7043
                            tcg_gen_sub_i32(tmp, tmp, tmp2);
7044 7044
                        } else {
7045
                            tcg_gen_add_i32(tmp, tmp, tmp2);
7045
                            /* This addition cannot overflow 32 bits;
7046
                             * however it may overflow considered as a signed
7047
                             * operation, in which case we must set the Q flag.
7048
                             */
7049
                            gen_helper_add_setq(tmp, tmp, tmp2);
7046 7050
                        }
7047 7051
                        tcg_temp_free_i32(tmp2);
7048 7052
                        if (insn & (1 << 22)) {
......
7860 7864
                if (op)
7861 7865
                    gen_swap_half(tmp2);
7862 7866
                gen_smul_dual(tmp, tmp2);
7863
                /* This addition cannot overflow.  */
7864 7867
                if (insn & (1 << 22)) {
7868
                    /* This subtraction cannot overflow. */
7865 7869
                    tcg_gen_sub_i32(tmp, tmp, tmp2);
7866 7870
                } else {
7867
                    tcg_gen_add_i32(tmp, tmp, tmp2);
7871
                    /* This addition cannot overflow 32 bits;
7872
                     * however it may overflow considered as a signed
7873
                     * operation, in which case we must set the Q flag.
7874
                     */
7875
                    gen_helper_add_setq(tmp, tmp, tmp2);
7868 7876
                }
7869 7877
                tcg_temp_free_i32(tmp2);
7870 7878
                if (rs != 15)

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