Revision e1f8c729
| b/hw/mainstone.c | ||
|---|---|---|
| 140 | 140 |
} |
| 141 | 141 |
|
| 142 | 142 |
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
|
| 143 |
cpu->pic[PXA2XX_PIC_GPIO_0]);
|
|
| 143 |
qdev_get_gpio_in(cpu->pic, PXA2XX_PIC_GPIO_0));
|
|
| 144 | 144 |
|
| 145 | 145 |
/* setup keypad */ |
| 146 | 146 |
printf("map addr %p\n", &map);
|
| b/hw/pxa.h | ||
|---|---|---|
| 63 | 63 |
# define PXA2XX_INTERNAL_SIZE 0x40000 |
| 64 | 64 |
|
| 65 | 65 |
/* pxa2xx_pic.c */ |
| 66 |
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
|
|
| 66 |
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
|
|
| 67 | 67 |
|
| 68 | 68 |
/* pxa2xx_timer.c */ |
| 69 |
void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
|
|
| 70 |
void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
|
|
| 69 |
void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic);
|
|
| 70 |
void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic);
|
|
| 71 | 71 |
|
| 72 | 72 |
/* pxa2xx_gpio.c */ |
| 73 | 73 |
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, |
| 74 |
CPUState *env, qemu_irq *pic, int lines);
|
|
| 74 |
CPUState *env, DeviceState *pic, int lines);
|
|
| 75 | 75 |
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); |
| 76 | 76 |
|
| 77 | 77 |
/* pxa2xx_dma.c */ |
| ... | ... | |
| 125 | 125 |
|
| 126 | 126 |
typedef struct {
|
| 127 | 127 |
CPUState *env; |
| 128 |
qemu_irq *pic;
|
|
| 128 |
DeviceState *pic;
|
|
| 129 | 129 |
qemu_irq reset; |
| 130 | 130 |
PXA2xxDMAState *dma; |
| 131 | 131 |
DeviceState *gpio; |
| ... | ... | |
| 180 | 180 |
QEMUTimer *rtc_swal1; |
| 181 | 181 |
QEMUTimer *rtc_swal2; |
| 182 | 182 |
QEMUTimer *rtc_pi; |
| 183 |
qemu_irq rtc_irq; |
|
| 183 | 184 |
} PXA2xxState; |
| 184 | 185 |
|
| 185 | 186 |
struct PXA2xxI2SState {
|
| b/hw/pxa2xx.c | ||
|---|---|---|
| 888 | 888 |
|
| 889 | 889 |
static inline void pxa2xx_rtc_int_update(PXA2xxState *s) |
| 890 | 890 |
{
|
| 891 |
qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
|
|
| 891 |
qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
|
|
| 892 | 892 |
} |
| 893 | 893 |
|
| 894 | 894 |
static void pxa2xx_rtc_hzupdate(PXA2xxState *s) |
| ... | ... | |
| 1197 | 1197 |
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s); |
| 1198 | 1198 |
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s); |
| 1199 | 1199 |
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
| 1200 |
|
|
| 1201 |
s->rtc_irq = qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM); |
|
| 1200 | 1202 |
} |
| 1201 | 1203 |
|
| 1202 | 1204 |
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque) |
| ... | ... | |
| 2095 | 2097 |
|
| 2096 | 2098 |
s->pic = pxa2xx_pic_init(0x40d00000, s->env); |
| 2097 | 2099 |
|
| 2098 |
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); |
|
| 2100 |
s->dma = pxa27x_dma_init(0x40000000, |
|
| 2101 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); |
|
| 2099 | 2102 |
|
| 2100 |
pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], |
|
| 2101 |
s->pic[PXA27X_PIC_OST_4_11]); |
|
| 2103 |
pxa27x_timer_init(0x40a00000, s->pic); |
|
| 2102 | 2104 |
|
| 2103 | 2105 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); |
| 2104 | 2106 |
|
| ... | ... | |
| 2108 | 2110 |
exit(1); |
| 2109 | 2111 |
} |
| 2110 | 2112 |
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv, |
| 2111 |
s->pic[PXA2XX_PIC_MMC], s->dma);
|
|
| 2113 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
|
|
| 2112 | 2114 |
|
| 2113 | 2115 |
for (i = 0; pxa270_serial[i].io_base; i ++) |
| 2114 | 2116 |
if (serial_hds[i]) |
| 2115 | 2117 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 2116 | 2118 |
serial_mm_init(pxa270_serial[i].io_base, 2, |
| 2117 |
s->pic[pxa270_serial[i].irqn], 14857000/16,
|
|
| 2118 |
serial_hds[i], 1, 1); |
|
| 2119 |
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
|
|
| 2120 |
14857000 / 16, serial_hds[i], 1, 1);
|
|
| 2119 | 2121 |
#else |
| 2120 | 2122 |
serial_mm_init(pxa270_serial[i].io_base, 2, |
| 2121 |
s->pic[pxa270_serial[i].irqn], 14857000/16,
|
|
| 2122 |
serial_hds[i], 1, 0); |
|
| 2123 |
qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
|
|
| 2124 |
14857000 / 16, serial_hds[i], 1, 0);
|
|
| 2123 | 2125 |
#endif |
| 2124 | 2126 |
else |
| 2125 | 2127 |
break; |
| 2126 | 2128 |
if (serial_hds[i]) |
| 2127 |
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP], |
|
| 2129 |
s->fir = pxa2xx_fir_init(0x40800000, |
|
| 2130 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
|
| 2128 | 2131 |
s->dma, serial_hds[i]); |
| 2129 | 2132 |
|
| 2130 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]); |
|
| 2133 |
s->lcd = pxa2xx_lcdc_init(0x44000000, |
|
| 2134 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
|
| 2131 | 2135 |
|
| 2132 | 2136 |
s->cm_base = 0x41300000; |
| 2133 | 2137 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
| ... | ... | |
| 2159 | 2163 |
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
|
| 2160 | 2164 |
DeviceState *dev; |
| 2161 | 2165 |
dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
|
| 2162 |
s->pic[pxa27x_ssp[i].irqn]);
|
|
| 2166 |
qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
|
|
| 2163 | 2167 |
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); |
| 2164 | 2168 |
} |
| 2165 | 2169 |
|
| 2166 | 2170 |
if (usb_enabled) {
|
| 2167 | 2171 |
sysbus_create_simple("sysbus-ohci", 0x4c000000,
|
| 2168 |
s->pic[PXA2XX_PIC_USBH1]);
|
|
| 2172 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
|
|
| 2169 | 2173 |
} |
| 2170 | 2174 |
|
| 2171 | 2175 |
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
| ... | ... | |
| 2179 | 2183 |
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, |
| 2180 | 2184 |
pxa2xx_rtc_load, s); |
| 2181 | 2185 |
|
| 2182 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff); |
|
| 2183 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff); |
|
| 2186 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
|
| 2187 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); |
|
| 2188 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, |
|
| 2189 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); |
|
| 2184 | 2190 |
|
| 2185 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma); |
|
| 2191 |
s->i2s = pxa2xx_i2s_init(0x40400000, |
|
| 2192 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma); |
|
| 2186 | 2193 |
|
| 2187 |
s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]); |
|
| 2194 |
s->kp = pxa27x_keypad_init(0x41500000, |
|
| 2195 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); |
|
| 2188 | 2196 |
|
| 2189 | 2197 |
/* GPIO1 resets the processor */ |
| 2190 | 2198 |
/* The handler can be overridden by board-specific code */ |
| ... | ... | |
| 2218 | 2226 |
|
| 2219 | 2227 |
s->pic = pxa2xx_pic_init(0x40d00000, s->env); |
| 2220 | 2228 |
|
| 2221 |
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]); |
|
| 2229 |
s->dma = pxa255_dma_init(0x40000000, |
|
| 2230 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); |
|
| 2222 | 2231 |
|
| 2223 |
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
|
|
| 2232 |
pxa25x_timer_init(0x40a00000, s->pic);
|
|
| 2224 | 2233 |
|
| 2225 | 2234 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85); |
| 2226 | 2235 |
|
| ... | ... | |
| 2230 | 2239 |
exit(1); |
| 2231 | 2240 |
} |
| 2232 | 2241 |
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv, |
| 2233 |
s->pic[PXA2XX_PIC_MMC], s->dma);
|
|
| 2242 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
|
|
| 2234 | 2243 |
|
| 2235 | 2244 |
for (i = 0; pxa255_serial[i].io_base; i ++) |
| 2236 | 2245 |
if (serial_hds[i]) {
|
| 2237 | 2246 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 2238 | 2247 |
serial_mm_init(pxa255_serial[i].io_base, 2, |
| 2239 |
s->pic[pxa255_serial[i].irqn], 14745600/16,
|
|
| 2240 |
serial_hds[i], 1, 1); |
|
| 2248 |
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
|
|
| 2249 |
14745600 / 16, serial_hds[i], 1, 1);
|
|
| 2241 | 2250 |
#else |
| 2242 | 2251 |
serial_mm_init(pxa255_serial[i].io_base, 2, |
| 2243 |
s->pic[pxa255_serial[i].irqn], 14745600/16,
|
|
| 2244 |
serial_hds[i], 1, 0); |
|
| 2252 |
qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
|
|
| 2253 |
14745600 / 16, serial_hds[i], 1, 0);
|
|
| 2245 | 2254 |
#endif |
| 2246 | 2255 |
} else {
|
| 2247 | 2256 |
break; |
| 2248 | 2257 |
} |
| 2249 | 2258 |
if (serial_hds[i]) |
| 2250 |
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP], |
|
| 2259 |
s->fir = pxa2xx_fir_init(0x40800000, |
|
| 2260 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
|
| 2251 | 2261 |
s->dma, serial_hds[i]); |
| 2252 | 2262 |
|
| 2253 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]); |
|
| 2263 |
s->lcd = pxa2xx_lcdc_init(0x44000000, |
|
| 2264 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
|
| 2254 | 2265 |
|
| 2255 | 2266 |
s->cm_base = 0x41300000; |
| 2256 | 2267 |
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
| ... | ... | |
| 2282 | 2293 |
for (i = 0; pxa255_ssp[i].io_base; i ++) {
|
| 2283 | 2294 |
DeviceState *dev; |
| 2284 | 2295 |
dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
|
| 2285 |
s->pic[pxa255_ssp[i].irqn]);
|
|
| 2296 |
qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
|
|
| 2286 | 2297 |
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); |
| 2287 | 2298 |
} |
| 2288 | 2299 |
|
| 2289 | 2300 |
if (usb_enabled) {
|
| 2290 | 2301 |
sysbus_create_simple("sysbus-ohci", 0x4c000000,
|
| 2291 |
s->pic[PXA2XX_PIC_USBH1]);
|
|
| 2302 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
|
|
| 2292 | 2303 |
} |
| 2293 | 2304 |
|
| 2294 | 2305 |
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
| ... | ... | |
| 2302 | 2313 |
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save, |
| 2303 | 2314 |
pxa2xx_rtc_load, s); |
| 2304 | 2315 |
|
| 2305 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff); |
|
| 2306 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff); |
|
| 2316 |
s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
|
| 2317 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); |
|
| 2318 |
s->i2c[1] = pxa2xx_i2c_init(0x40f00100, |
|
| 2319 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); |
|
| 2307 | 2320 |
|
| 2308 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma); |
|
| 2321 |
s->i2s = pxa2xx_i2s_init(0x40400000, |
|
| 2322 |
qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma); |
|
| 2309 | 2323 |
|
| 2310 | 2324 |
/* GPIO1 resets the processor */ |
| 2311 | 2325 |
/* The handler can be overridden by board-specific code */ |
| b/hw/pxa2xx_gpio.c | ||
|---|---|---|
| 253 | 253 |
}; |
| 254 | 254 |
|
| 255 | 255 |
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, |
| 256 |
CPUState *env, qemu_irq *pic, int lines)
|
|
| 256 |
CPUState *env, DeviceState *pic, int lines)
|
|
| 257 | 257 |
{
|
| 258 | 258 |
DeviceState *dev; |
| 259 | 259 |
|
| ... | ... | |
| 263 | 263 |
qdev_init_nofail(dev); |
| 264 | 264 |
|
| 265 | 265 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); |
| 266 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PIC_GPIO_0]); |
|
| 267 |
sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PIC_GPIO_1]); |
|
| 268 |
sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PIC_GPIO_X]); |
|
| 266 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, |
|
| 267 |
qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); |
|
| 268 |
sysbus_connect_irq(sysbus_from_qdev(dev), 1, |
|
| 269 |
qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); |
|
| 270 |
sysbus_connect_irq(sysbus_from_qdev(dev), 2, |
|
| 271 |
qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); |
|
| 269 | 272 |
|
| 270 | 273 |
return dev; |
| 271 | 274 |
} |
| b/hw/pxa2xx_pic.c | ||
|---|---|---|
| 10 | 10 |
|
| 11 | 11 |
#include "hw.h" |
| 12 | 12 |
#include "pxa.h" |
| 13 |
#include "sysbus.h" |
|
| 13 | 14 |
|
| 14 | 15 |
#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ |
| 15 | 16 |
#define ICMR 0x04 /* Interrupt Controller Mask register */ |
| ... | ... | |
| 31 | 32 |
#define PXA2XX_PIC_SRCS 40 |
| 32 | 33 |
|
| 33 | 34 |
typedef struct {
|
| 35 |
SysBusDevice busdev; |
|
| 34 | 36 |
CPUState *cpu_env; |
| 35 | 37 |
uint32_t int_enabled[2]; |
| 36 | 38 |
uint32_t int_pending[2]; |
| ... | ... | |
| 241 | 243 |
pxa2xx_pic_mem_write, |
| 242 | 244 |
}; |
| 243 | 245 |
|
| 244 |
static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
|
|
| 246 |
static int pxa2xx_pic_post_load(void *opaque, int version_id)
|
|
| 245 | 247 |
{
|
| 246 |
PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
|
| 247 |
int i; |
|
| 248 |
|
|
| 249 |
for (i = 0; i < 2; i ++) |
|
| 250 |
qemu_put_be32s(f, &s->int_enabled[i]); |
|
| 251 |
for (i = 0; i < 2; i ++) |
|
| 252 |
qemu_put_be32s(f, &s->int_pending[i]); |
|
| 253 |
for (i = 0; i < 2; i ++) |
|
| 254 |
qemu_put_be32s(f, &s->is_fiq[i]); |
|
| 255 |
qemu_put_be32s(f, &s->int_idle); |
|
| 256 |
for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
|
| 257 |
qemu_put_be32s(f, &s->priority[i]); |
|
| 258 |
} |
|
| 259 |
|
|
| 260 |
static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) |
|
| 261 |
{
|
|
| 262 |
PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
|
| 263 |
int i; |
|
| 264 |
|
|
| 265 |
for (i = 0; i < 2; i ++) |
|
| 266 |
qemu_get_be32s(f, &s->int_enabled[i]); |
|
| 267 |
for (i = 0; i < 2; i ++) |
|
| 268 |
qemu_get_be32s(f, &s->int_pending[i]); |
|
| 269 |
for (i = 0; i < 2; i ++) |
|
| 270 |
qemu_get_be32s(f, &s->is_fiq[i]); |
|
| 271 |
qemu_get_be32s(f, &s->int_idle); |
|
| 272 |
for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
|
| 273 |
qemu_get_be32s(f, &s->priority[i]); |
|
| 274 |
|
|
| 275 | 248 |
pxa2xx_pic_update(opaque); |
| 276 | 249 |
return 0; |
| 277 | 250 |
} |
| 278 | 251 |
|
| 279 |
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
|
|
| 252 |
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
|
|
| 280 | 253 |
{
|
| 281 |
PXA2xxPICState *s;
|
|
| 254 |
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
|
|
| 282 | 255 |
int iomemtype; |
| 283 |
qemu_irq *qi; |
|
| 284 |
|
|
| 285 |
s = (PXA2xxPICState *) |
|
| 286 |
qemu_mallocz(sizeof(PXA2xxPICState)); |
|
| 287 |
if (!s) |
|
| 288 |
return NULL; |
|
| 256 |
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev)); |
|
| 289 | 257 |
|
| 290 | 258 |
s->cpu_env = env; |
| 291 | 259 |
|
| ... | ... | |
| 296 | 264 |
s->is_fiq[0] = 0; |
| 297 | 265 |
s->is_fiq[1] = 0; |
| 298 | 266 |
|
| 299 |
qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS); |
|
| 267 |
qdev_init_nofail(dev); |
|
| 268 |
|
|
| 269 |
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); |
|
| 300 | 270 |
|
| 301 | 271 |
/* Enable IC memory-mapped registers access. */ |
| 302 | 272 |
iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn, |
| 303 | 273 |
pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN); |
| 304 |
cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
|
| 274 |
sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype);
|
|
| 305 | 275 |
|
| 306 | 276 |
/* Enable IC coprocessor access. */ |
| 307 | 277 |
cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); |
| 308 | 278 |
|
| 309 |
register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save, |
|
| 310 |
pxa2xx_pic_load, s); |
|
| 279 |
return dev; |
|
| 280 |
} |
|
| 281 |
|
|
| 282 |
static VMStateDescription vmstate_pxa2xx_pic_regs = {
|
|
| 283 |
.name = "pxa2xx_pic", |
|
| 284 |
.version_id = 0, |
|
| 285 |
.minimum_version_id = 0, |
|
| 286 |
.minimum_version_id_old = 0, |
|
| 287 |
.post_load = pxa2xx_pic_post_load, |
|
| 288 |
.fields = (VMStateField[]) {
|
|
| 289 |
VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2), |
|
| 290 |
VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2), |
|
| 291 |
VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2), |
|
| 292 |
VMSTATE_UINT32(int_idle, PXA2xxPICState), |
|
| 293 |
VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS), |
|
| 294 |
VMSTATE_END_OF_LIST(), |
|
| 295 |
}, |
|
| 296 |
}; |
|
| 311 | 297 |
|
| 312 |
return qi; |
|
| 298 |
static int pxa2xx_pic_initfn(SysBusDevice *dev) |
|
| 299 |
{
|
|
| 300 |
return 0; |
|
| 301 |
} |
|
| 302 |
|
|
| 303 |
static SysBusDeviceInfo pxa2xx_pic_info = {
|
|
| 304 |
.init = pxa2xx_pic_initfn, |
|
| 305 |
.qdev.name = "pxa2xx_pic", |
|
| 306 |
.qdev.desc = "PXA2xx PIC", |
|
| 307 |
.qdev.size = sizeof(PXA2xxPICState), |
|
| 308 |
.qdev.vmsd = &vmstate_pxa2xx_pic_regs, |
|
| 309 |
}; |
|
| 310 |
|
|
| 311 |
static void pxa2xx_pic_register(void) |
|
| 312 |
{
|
|
| 313 |
sysbus_register_withprop(&pxa2xx_pic_info); |
|
| 313 | 314 |
} |
| 315 |
device_init(pxa2xx_pic_register); |
|
| b/hw/pxa2xx_timer.c | ||
|---|---|---|
| 10 | 10 |
#include "hw.h" |
| 11 | 11 |
#include "qemu-timer.h" |
| 12 | 12 |
#include "sysemu.h" |
| 13 |
#include "qdev.h" |
|
| 13 | 14 |
#include "pxa.h" |
| 14 | 15 |
|
| 15 | 16 |
#define OSMR0 0x00 |
| ... | ... | |
| 428 | 429 |
} |
| 429 | 430 |
|
| 430 | 431 |
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base, |
| 431 |
qemu_irq *irqs)
|
|
| 432 |
DeviceState *pic)
|
|
| 432 | 433 |
{
|
| 433 | 434 |
int i; |
| 434 | 435 |
int iomemtype; |
| ... | ... | |
| 443 | 444 |
|
| 444 | 445 |
for (i = 0; i < 4; i ++) {
|
| 445 | 446 |
s->timer[i].value = 0; |
| 446 |
s->timer[i].irq = irqs[i];
|
|
| 447 |
s->timer[i].irq = qdev_get_gpio_in(pic, PXA2XX_PIC_OST_0 + i);
|
|
| 447 | 448 |
s->timer[i].info = s; |
| 448 | 449 |
s->timer[i].num = i; |
| 449 | 450 |
s->timer[i].level = 0; |
| ... | ... | |
| 461 | 462 |
return s; |
| 462 | 463 |
} |
| 463 | 464 |
|
| 464 |
void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
|
|
| 465 |
void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic)
|
|
| 465 | 466 |
{
|
| 466 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
|
|
| 467 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
|
|
| 467 | 468 |
s->freq = PXA25X_FREQ; |
| 468 | 469 |
s->tm4 = NULL; |
| 469 | 470 |
} |
| 470 | 471 |
|
| 471 |
void pxa27x_timer_init(target_phys_addr_t base, |
|
| 472 |
qemu_irq *irqs, qemu_irq irq4) |
|
| 472 |
void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic) |
|
| 473 | 473 |
{
|
| 474 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
|
|
| 474 |
pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
|
|
| 475 | 475 |
int i; |
| 476 | 476 |
s->freq = PXA27X_FREQ; |
| 477 | 477 |
s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 * |
| 478 | 478 |
sizeof(PXA2xxTimer4)); |
| 479 | 479 |
for (i = 0; i < 8; i ++) {
|
| 480 | 480 |
s->tm4[i].tm.value = 0; |
| 481 |
s->tm4[i].tm.irq = irq4;
|
|
| 481 |
s->tm4[i].tm.irq = qdev_get_gpio_in(pic, PXA27X_PIC_OST_4_11);
|
|
| 482 | 482 |
s->tm4[i].tm.info = s; |
| 483 | 483 |
s->tm4[i].tm.num = i + 4; |
| 484 | 484 |
s->tm4[i].tm.level = 0; |
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