Revision e1f8c729 hw/pxa.h
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| 63 | 63 |
# define PXA2XX_INTERNAL_SIZE 0x40000 |
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/* pxa2xx_pic.c */ |
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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/* pxa2xx_timer.c */ |
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void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
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void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
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void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic);
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void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic);
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| 71 | 71 |
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/* pxa2xx_gpio.c */ |
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, |
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CPUState *env, qemu_irq *pic, int lines);
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CPUState *env, DeviceState *pic, int lines);
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); |
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/* pxa2xx_dma.c */ |
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typedef struct {
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CPUState *env; |
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qemu_irq *pic;
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DeviceState *pic;
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qemu_irq reset; |
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PXA2xxDMAState *dma; |
| 131 | 131 |
DeviceState *gpio; |
| ... | ... | |
| 180 | 180 |
QEMUTimer *rtc_swal1; |
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QEMUTimer *rtc_swal2; |
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QEMUTimer *rtc_pi; |
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qemu_irq rtc_irq; |
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} PXA2xxState; |
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struct PXA2xxI2SState {
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