Revision e1f8c729 hw/pxa2xx_pic.c
| b/hw/pxa2xx_pic.c | ||
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#include "hw.h" |
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#include "pxa.h" |
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#include "sysbus.h" |
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#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ |
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#define ICMR 0x04 /* Interrupt Controller Mask register */ |
| ... | ... | |
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#define PXA2XX_PIC_SRCS 40 |
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typedef struct {
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SysBusDevice busdev; |
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CPUState *cpu_env; |
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uint32_t int_enabled[2]; |
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uint32_t int_pending[2]; |
| ... | ... | |
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pxa2xx_pic_mem_write, |
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}; |
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static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
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static int pxa2xx_pic_post_load(void *opaque, int version_id)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
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int i; |
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for (i = 0; i < 2; i ++) |
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qemu_put_be32s(f, &s->int_enabled[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_put_be32s(f, &s->int_pending[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_put_be32s(f, &s->is_fiq[i]); |
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qemu_put_be32s(f, &s->int_idle); |
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for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
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qemu_put_be32s(f, &s->priority[i]); |
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} |
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static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id) |
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
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int i; |
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for (i = 0; i < 2; i ++) |
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qemu_get_be32s(f, &s->int_enabled[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_get_be32s(f, &s->int_pending[i]); |
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for (i = 0; i < 2; i ++) |
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qemu_get_be32s(f, &s->is_fiq[i]); |
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qemu_get_be32s(f, &s->int_idle); |
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for (i = 0; i < PXA2XX_PIC_SRCS; i ++) |
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qemu_get_be32s(f, &s->priority[i]); |
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pxa2xx_pic_update(opaque); |
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return 0; |
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} |
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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{
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PXA2xxPICState *s;
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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int iomemtype; |
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qemu_irq *qi; |
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s = (PXA2xxPICState *) |
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qemu_mallocz(sizeof(PXA2xxPICState)); |
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if (!s) |
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return NULL; |
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev)); |
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s->cpu_env = env; |
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|
| ... | ... | |
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s->is_fiq[0] = 0; |
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s->is_fiq[1] = 0; |
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qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS); |
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qdev_init_nofail(dev); |
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qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); |
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/* Enable IC memory-mapped registers access. */ |
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iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn, |
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pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN); |
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cpu_register_physical_memory(base, 0x00100000, iomemtype);
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sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype);
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/* Enable IC coprocessor access. */ |
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cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); |
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register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save, |
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pxa2xx_pic_load, s); |
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return dev; |
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} |
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static VMStateDescription vmstate_pxa2xx_pic_regs = {
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.name = "pxa2xx_pic", |
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.version_id = 0, |
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.minimum_version_id = 0, |
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.minimum_version_id_old = 0, |
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.post_load = pxa2xx_pic_post_load, |
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2), |
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VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2), |
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VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2), |
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VMSTATE_UINT32(int_idle, PXA2xxPICState), |
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VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS), |
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VMSTATE_END_OF_LIST(), |
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}, |
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}; |
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return qi; |
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static int pxa2xx_pic_initfn(SysBusDevice *dev) |
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{
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return 0; |
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} |
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static SysBusDeviceInfo pxa2xx_pic_info = {
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.init = pxa2xx_pic_initfn, |
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.qdev.name = "pxa2xx_pic", |
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.qdev.desc = "PXA2xx PIC", |
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.qdev.size = sizeof(PXA2xxPICState), |
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.qdev.vmsd = &vmstate_pxa2xx_pic_regs, |
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}; |
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static void pxa2xx_pic_register(void) |
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{
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sysbus_register_withprop(&pxa2xx_pic_info); |
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} |
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device_init(pxa2xx_pic_register); |
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