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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "monitor.h" |
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#include "net.h" |
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#include "sysemu.h" |
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...) printf(format, __VA_ARGS__)
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0) |
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#endif
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struct PCIBus {
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BusState qbus; |
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int bus_num;
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int devfn_min;
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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pci_hotplug_fn hotplug; |
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uint32_t config_reg; /* XXX: suppress */
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev; |
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PCIBus *next; |
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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}; |
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
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static struct BusInfo pci_bus_info = { |
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print, |
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.props = (Property[]) { |
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
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|
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target_phys_addr_t pci_mem_base; |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static PCIBus *first_bus;
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static const VMStateDescription vmstate_pcibus = { |
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_EQUAL(nirq, PCIBus), |
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VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static inline int pci_bar(int reg) |
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{ |
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return reg == PCI_ROM_SLOT ? PCI_ROM_ADDRESS : PCI_BASE_ADDRESS_0 + reg * 4; |
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} |
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|
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static void pci_device_reset(PCIDevice *dev) |
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{ |
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int r;
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memset(dev->irq_state, 0, sizeof dev->irq_state); |
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dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
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PCI_COMMAND_MASTER); |
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
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if (!dev->io_regions[r].size) {
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continue;
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} |
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pci_set_long(dev->config + pci_bar(r), dev->io_regions[r].type); |
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} |
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pci_update_mappings(dev); |
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} |
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static void pci_bus_reset(void *opaque) |
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{ |
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PCIBus *bus = opaque; |
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int i;
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
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if (bus->devices[i]) {
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pci_device_reset(bus->devices[i]); |
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} |
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} |
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} |
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, int devfn_min) |
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{ |
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static int nbus = 0; |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
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bus->devfn_min = devfn_min; |
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bus->next = first_bus; |
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first_bus = bus; |
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vmstate_register(nbus++, &vmstate_pcibus, bus); |
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qemu_register_reset(pci_bus_reset, bus); |
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} |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) |
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(*bus));
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bus->qbus.qdev_allocated = 1;
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pci_bus_new_inplace(bus, parent, name, devfn_min); |
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return bus;
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} |
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq) |
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{ |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = irq_opaque; |
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bus->nirq = nirq; |
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
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} |
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
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{ |
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bus->qbus.allow_hotplug = 1;
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bus->hotplug = hotplug; |
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} |
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque, int devfn_min, int nirq) |
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{ |
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PCIBus *bus; |
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bus = pci_bus_new(parent, name, devfn_min); |
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pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
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return bus;
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} |
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static void pci_register_secondary_bus(PCIBus *bus, |
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PCIDevice *dev, |
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pci_map_irq_fn map_irq, |
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const char *name) |
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{ |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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bus->next = dev->bus->next; |
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dev->bus->next = bus; |
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} |
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int pci_bus_num(PCIBus *s)
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{ |
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return s->bus_num;
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} |
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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, config); |
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uint8_t config[PCI_CONFIG_SPACE_SIZE]; |
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int i;
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assert(size == sizeof config);
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qemu_get_buffer(f, config, sizeof config);
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for (i = 0; i < sizeof config; ++i) |
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
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return -EINVAL;
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memcpy(s->config, config, sizeof config);
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pci_update_mappings(s); |
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return 0; |
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} |
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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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const uint8_t *v = pv;
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qemu_put_buffer(f, v, size); |
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} |
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static VMStateInfo vmstate_info_pci_config = {
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.name = "pci config",
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.get = get_pci_config_device, |
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.put = put_pci_config_device, |
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}; |
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const VMStateDescription vmstate_pci_device = {
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.name = "PCIDevice",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_LE(version_id, PCIDevice), |
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VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
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typeof_field(PCIDevice,config)), |
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VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{ |
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vmstate_save_state(f, &vmstate_pci_device, s); |
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} |
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{ |
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return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
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} |
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
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{ |
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uint16_t *id; |
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id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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id[1] = cpu_to_le16(pci_default_sub_device_id);
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return 0; |
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} |
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/*
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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*/
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
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{ |
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const char *p; |
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char *e;
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unsigned long val; |
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unsigned long dom = 0, bus = 0; |
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unsigned slot = 0; |
267 |
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p = addr; |
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
272 |
if (*e == ':') { |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
278 |
if (*e == ':') { |
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dom = bus; |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
285 |
} |
286 |
} |
287 |
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if (dom > 0xffff || bus > 0xff || val > 0x1f) |
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return -1; |
290 |
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slot = val; |
292 |
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if (*e)
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return -1; |
295 |
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/* Note: QEMU doesn't implement domains other than 0 */
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if (dom != 0 || pci_find_bus(bus) == NULL) |
298 |
return -1; |
299 |
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*domp = dom; |
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*busp = bus; |
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*slotp = slot; |
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return 0; |
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} |
305 |
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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
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unsigned *slotp)
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{ |
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/* strip legacy tag */
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if (!strncmp(addr, "pci_addr=", 9)) { |
311 |
addr += 9;
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312 |
} |
313 |
if (pci_parse_devaddr(addr, domp, busp, slotp)) {
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monitor_printf(mon, "Invalid pci address\n");
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return -1; |
316 |
} |
317 |
return 0; |
318 |
} |
319 |
|
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PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
321 |
{ |
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int dom, bus;
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unsigned slot;
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324 |
|
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if (!devaddr) {
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*devfnp = -1;
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return pci_find_bus(0); |
328 |
} |
329 |
|
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
331 |
return NULL; |
332 |
} |
333 |
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334 |
*devfnp = slot << 3;
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return pci_find_bus(bus);
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} |
337 |
|
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static void pci_init_cmask(PCIDevice *dev) |
339 |
{ |
340 |
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
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pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
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dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
343 |
dev->cmask[PCI_REVISION_ID] = 0xff;
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344 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
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pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
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dev->cmask[PCI_HEADER_TYPE] = 0xff;
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dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
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} |
349 |
|
350 |
static void pci_init_wmask(PCIDevice *dev) |
351 |
{ |
352 |
int i;
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dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
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dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
356 |
| PCI_COMMAND_MASTER; |
357 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
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358 |
dev->wmask[i] = 0xff;
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359 |
} |
360 |
|
361 |
/* -1 for devfn means auto assign */
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362 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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363 |
const char *name, int devfn, |
364 |
PCIConfigReadFunc *config_read, |
365 |
PCIConfigWriteFunc *config_write) |
366 |
{ |
367 |
if (devfn < 0) { |
368 |
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
369 |
if (!bus->devices[devfn])
|
370 |
goto found;
|
371 |
} |
372 |
return NULL; |
373 |
found: ;
|
374 |
} else if (bus->devices[devfn]) { |
375 |
return NULL; |
376 |
} |
377 |
pci_dev->bus = bus; |
378 |
pci_dev->devfn = devfn; |
379 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
380 |
memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
381 |
pci_set_default_subsystem_id(pci_dev); |
382 |
pci_init_cmask(pci_dev); |
383 |
pci_init_wmask(pci_dev); |
384 |
|
385 |
if (!config_read)
|
386 |
config_read = pci_default_read_config; |
387 |
if (!config_write)
|
388 |
config_write = pci_default_write_config; |
389 |
pci_dev->config_read = config_read; |
390 |
pci_dev->config_write = config_write; |
391 |
bus->devices[devfn] = pci_dev; |
392 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
|
393 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
394 |
return pci_dev;
|
395 |
} |
396 |
|
397 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
398 |
int instance_size, int devfn, |
399 |
PCIConfigReadFunc *config_read, |
400 |
PCIConfigWriteFunc *config_write) |
401 |
{ |
402 |
PCIDevice *pci_dev; |
403 |
|
404 |
pci_dev = qemu_mallocz(instance_size); |
405 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
406 |
config_read, config_write); |
407 |
return pci_dev;
|
408 |
} |
409 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
410 |
{ |
411 |
return addr + pci_mem_base;
|
412 |
} |
413 |
|
414 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
415 |
{ |
416 |
PCIIORegion *r; |
417 |
int i;
|
418 |
|
419 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
420 |
r = &pci_dev->io_regions[i]; |
421 |
if (!r->size || r->addr == -1) |
422 |
continue;
|
423 |
if (r->type == PCI_ADDRESS_SPACE_IO) {
|
424 |
isa_unassign_ioport(r->addr, r->size); |
425 |
} else {
|
426 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
427 |
r->size, |
428 |
IO_MEM_UNASSIGNED); |
429 |
} |
430 |
} |
431 |
} |
432 |
|
433 |
static int pci_unregister_device(DeviceState *dev) |
434 |
{ |
435 |
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
436 |
PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
437 |
int ret = 0; |
438 |
|
439 |
if (info->exit)
|
440 |
ret = info->exit(pci_dev); |
441 |
if (ret)
|
442 |
return ret;
|
443 |
|
444 |
pci_unregister_io_regions(pci_dev); |
445 |
|
446 |
qemu_free_irqs(pci_dev->irq); |
447 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
448 |
return 0; |
449 |
} |
450 |
|
451 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
452 |
uint32_t size, int type,
|
453 |
PCIMapIORegionFunc *map_func) |
454 |
{ |
455 |
PCIIORegion *r; |
456 |
uint32_t addr; |
457 |
uint32_t wmask; |
458 |
|
459 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
460 |
return;
|
461 |
|
462 |
if (size & (size-1)) { |
463 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
464 |
"type=0x%x, size=0x%x\n", type, size);
|
465 |
exit(1);
|
466 |
} |
467 |
|
468 |
r = &pci_dev->io_regions[region_num]; |
469 |
r->addr = -1;
|
470 |
r->size = size; |
471 |
r->type = type; |
472 |
r->map_func = map_func; |
473 |
|
474 |
wmask = ~(size - 1);
|
475 |
addr = pci_bar(region_num); |
476 |
if (region_num == PCI_ROM_SLOT) {
|
477 |
/* ROM enable bit is writeable */
|
478 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
479 |
} |
480 |
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
481 |
*(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
482 |
*(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
|
483 |
} |
484 |
|
485 |
static void pci_update_mappings(PCIDevice *d) |
486 |
{ |
487 |
PCIIORegion *r; |
488 |
int cmd, i;
|
489 |
uint32_t last_addr, new_addr; |
490 |
|
491 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
492 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
493 |
r = &d->io_regions[i]; |
494 |
if (r->size != 0) { |
495 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
496 |
if (cmd & PCI_COMMAND_IO) {
|
497 |
new_addr = pci_get_long(d->config + pci_bar(i)); |
498 |
new_addr = new_addr & ~(r->size - 1);
|
499 |
last_addr = new_addr + r->size - 1;
|
500 |
/* NOTE: we have only 64K ioports on PC */
|
501 |
if (last_addr <= new_addr || new_addr == 0 || |
502 |
last_addr >= 0x10000) {
|
503 |
new_addr = -1;
|
504 |
} |
505 |
} else {
|
506 |
new_addr = -1;
|
507 |
} |
508 |
} else {
|
509 |
if (cmd & PCI_COMMAND_MEMORY) {
|
510 |
new_addr = pci_get_long(d->config + pci_bar(i)); |
511 |
/* the ROM slot has a specific enable bit */
|
512 |
if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
|
513 |
goto no_mem_map;
|
514 |
new_addr = new_addr & ~(r->size - 1);
|
515 |
last_addr = new_addr + r->size - 1;
|
516 |
/* NOTE: we do not support wrapping */
|
517 |
/* XXX: as we cannot support really dynamic
|
518 |
mappings, we handle specific values as invalid
|
519 |
mappings. */
|
520 |
if (last_addr <= new_addr || new_addr == 0 || |
521 |
last_addr == -1) {
|
522 |
new_addr = -1;
|
523 |
} |
524 |
} else {
|
525 |
no_mem_map:
|
526 |
new_addr = -1;
|
527 |
} |
528 |
} |
529 |
/* now do the real mapping */
|
530 |
if (new_addr != r->addr) {
|
531 |
if (r->addr != -1) { |
532 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
533 |
int class;
|
534 |
/* NOTE: specific hack for IDE in PC case:
|
535 |
only one byte must be mapped. */
|
536 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
537 |
if (class == 0x0101 && r->size == 4) { |
538 |
isa_unassign_ioport(r->addr + 2, 1); |
539 |
} else {
|
540 |
isa_unassign_ioport(r->addr, r->size); |
541 |
} |
542 |
} else {
|
543 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
544 |
r->size, |
545 |
IO_MEM_UNASSIGNED); |
546 |
qemu_unregister_coalesced_mmio(r->addr, r->size); |
547 |
} |
548 |
} |
549 |
r->addr = new_addr; |
550 |
if (r->addr != -1) { |
551 |
r->map_func(d, i, r->addr, r->size, r->type); |
552 |
} |
553 |
} |
554 |
} |
555 |
} |
556 |
} |
557 |
|
558 |
uint32_t pci_default_read_config(PCIDevice *d, |
559 |
uint32_t address, int len)
|
560 |
{ |
561 |
uint32_t val; |
562 |
|
563 |
switch(len) {
|
564 |
default:
|
565 |
case 4: |
566 |
if (address <= 0xfc) { |
567 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
568 |
break;
|
569 |
} |
570 |
/* fall through */
|
571 |
case 2: |
572 |
if (address <= 0xfe) { |
573 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
574 |
break;
|
575 |
} |
576 |
/* fall through */
|
577 |
case 1: |
578 |
val = d->config[address]; |
579 |
break;
|
580 |
} |
581 |
return val;
|
582 |
} |
583 |
|
584 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
585 |
{ |
586 |
uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
587 |
int i;
|
588 |
|
589 |
/* not efficient, but simple */
|
590 |
memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
591 |
for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { |
592 |
uint8_t wmask = d->wmask[addr]; |
593 |
d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); |
594 |
} |
595 |
if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
596 |
|| ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) |
597 |
& (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) |
598 |
pci_update_mappings(d); |
599 |
} |
600 |
|
601 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
602 |
{ |
603 |
PCIBus *s = opaque; |
604 |
PCIDevice *pci_dev; |
605 |
int config_addr, bus_num;
|
606 |
|
607 |
#if 0
|
608 |
PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
|
609 |
addr, val, len);
|
610 |
#endif
|
611 |
bus_num = (addr >> 16) & 0xff; |
612 |
while (s && s->bus_num != bus_num)
|
613 |
s = s->next; |
614 |
if (!s)
|
615 |
return;
|
616 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
617 |
if (!pci_dev)
|
618 |
return;
|
619 |
config_addr = addr & 0xff;
|
620 |
PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
621 |
pci_dev->name, config_addr, val, len); |
622 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
623 |
} |
624 |
|
625 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
626 |
{ |
627 |
PCIBus *s = opaque; |
628 |
PCIDevice *pci_dev; |
629 |
int config_addr, bus_num;
|
630 |
uint32_t val; |
631 |
|
632 |
bus_num = (addr >> 16) & 0xff; |
633 |
while (s && s->bus_num != bus_num)
|
634 |
s= s->next; |
635 |
if (!s)
|
636 |
goto fail;
|
637 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
638 |
if (!pci_dev) {
|
639 |
fail:
|
640 |
switch(len) {
|
641 |
case 1: |
642 |
val = 0xff;
|
643 |
break;
|
644 |
case 2: |
645 |
val = 0xffff;
|
646 |
break;
|
647 |
default:
|
648 |
case 4: |
649 |
val = 0xffffffff;
|
650 |
break;
|
651 |
} |
652 |
goto the_end;
|
653 |
} |
654 |
config_addr = addr & 0xff;
|
655 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
656 |
PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
657 |
pci_dev->name, config_addr, val, len); |
658 |
the_end:
|
659 |
#if 0
|
660 |
PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
|
661 |
addr, val, len);
|
662 |
#endif
|
663 |
return val;
|
664 |
} |
665 |
|
666 |
/***********************************************************/
|
667 |
/* generic PCI irq support */
|
668 |
|
669 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
670 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
671 |
{ |
672 |
PCIDevice *pci_dev = opaque; |
673 |
PCIBus *bus; |
674 |
int change;
|
675 |
|
676 |
change = level - pci_dev->irq_state[irq_num]; |
677 |
if (!change)
|
678 |
return;
|
679 |
|
680 |
pci_dev->irq_state[irq_num] = level; |
681 |
for (;;) {
|
682 |
bus = pci_dev->bus; |
683 |
irq_num = bus->map_irq(pci_dev, irq_num); |
684 |
if (bus->set_irq)
|
685 |
break;
|
686 |
pci_dev = bus->parent_dev; |
687 |
} |
688 |
bus->irq_count[irq_num] += change; |
689 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
690 |
} |
691 |
|
692 |
/***********************************************************/
|
693 |
/* monitor info on PCI */
|
694 |
|
695 |
typedef struct { |
696 |
uint16_t class; |
697 |
const char *desc; |
698 |
} pci_class_desc; |
699 |
|
700 |
static const pci_class_desc pci_class_descriptions[] = |
701 |
{ |
702 |
{ 0x0100, "SCSI controller"}, |
703 |
{ 0x0101, "IDE controller"}, |
704 |
{ 0x0102, "Floppy controller"}, |
705 |
{ 0x0103, "IPI controller"}, |
706 |
{ 0x0104, "RAID controller"}, |
707 |
{ 0x0106, "SATA controller"}, |
708 |
{ 0x0107, "SAS controller"}, |
709 |
{ 0x0180, "Storage controller"}, |
710 |
{ 0x0200, "Ethernet controller"}, |
711 |
{ 0x0201, "Token Ring controller"}, |
712 |
{ 0x0202, "FDDI controller"}, |
713 |
{ 0x0203, "ATM controller"}, |
714 |
{ 0x0280, "Network controller"}, |
715 |
{ 0x0300, "VGA controller"}, |
716 |
{ 0x0301, "XGA controller"}, |
717 |
{ 0x0302, "3D controller"}, |
718 |
{ 0x0380, "Display controller"}, |
719 |
{ 0x0400, "Video controller"}, |
720 |
{ 0x0401, "Audio controller"}, |
721 |
{ 0x0402, "Phone"}, |
722 |
{ 0x0480, "Multimedia controller"}, |
723 |
{ 0x0500, "RAM controller"}, |
724 |
{ 0x0501, "Flash controller"}, |
725 |
{ 0x0580, "Memory controller"}, |
726 |
{ 0x0600, "Host bridge"}, |
727 |
{ 0x0601, "ISA bridge"}, |
728 |
{ 0x0602, "EISA bridge"}, |
729 |
{ 0x0603, "MC bridge"}, |
730 |
{ 0x0604, "PCI bridge"}, |
731 |
{ 0x0605, "PCMCIA bridge"}, |
732 |
{ 0x0606, "NUBUS bridge"}, |
733 |
{ 0x0607, "CARDBUS bridge"}, |
734 |
{ 0x0608, "RACEWAY bridge"}, |
735 |
{ 0x0680, "Bridge"}, |
736 |
{ 0x0c03, "USB controller"}, |
737 |
{ 0, NULL} |
738 |
}; |
739 |
|
740 |
static void pci_info_device(PCIDevice *d) |
741 |
{ |
742 |
Monitor *mon = cur_mon; |
743 |
int i, class;
|
744 |
PCIIORegion *r; |
745 |
const pci_class_desc *desc;
|
746 |
|
747 |
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
748 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
749 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
750 |
monitor_printf(mon, " ");
|
751 |
desc = pci_class_descriptions; |
752 |
while (desc->desc && class != desc->class)
|
753 |
desc++; |
754 |
if (desc->desc) {
|
755 |
monitor_printf(mon, "%s", desc->desc);
|
756 |
} else {
|
757 |
monitor_printf(mon, "Class %04x", class);
|
758 |
} |
759 |
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
760 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
761 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
762 |
|
763 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
764 |
monitor_printf(mon, " IRQ %d.\n",
|
765 |
d->config[PCI_INTERRUPT_LINE]); |
766 |
} |
767 |
if (class == 0x0604) { |
768 |
monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
769 |
} |
770 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
771 |
r = &d->io_regions[i]; |
772 |
if (r->size != 0) { |
773 |
monitor_printf(mon, " BAR%d: ", i);
|
774 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
775 |
monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
|
776 |
r->addr, r->addr + r->size - 1);
|
777 |
} else {
|
778 |
monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
|
779 |
r->addr, r->addr + r->size - 1);
|
780 |
} |
781 |
} |
782 |
} |
783 |
monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
784 |
if (class == 0x0604 && d->config[0x19] != 0) { |
785 |
pci_for_each_device(d->config[0x19], pci_info_device);
|
786 |
} |
787 |
} |
788 |
|
789 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
790 |
{ |
791 |
PCIBus *bus = first_bus; |
792 |
PCIDevice *d; |
793 |
int devfn;
|
794 |
|
795 |
while (bus && bus->bus_num != bus_num)
|
796 |
bus = bus->next; |
797 |
if (bus) {
|
798 |
for(devfn = 0; devfn < 256; devfn++) { |
799 |
d = bus->devices[devfn]; |
800 |
if (d)
|
801 |
fn(d); |
802 |
} |
803 |
} |
804 |
} |
805 |
|
806 |
void pci_info(Monitor *mon)
|
807 |
{ |
808 |
pci_for_each_device(0, pci_info_device);
|
809 |
} |
810 |
|
811 |
static const char * const pci_nic_models[] = { |
812 |
"ne2k_pci",
|
813 |
"i82551",
|
814 |
"i82557b",
|
815 |
"i82559er",
|
816 |
"rtl8139",
|
817 |
"e1000",
|
818 |
"pcnet",
|
819 |
"virtio",
|
820 |
NULL
|
821 |
}; |
822 |
|
823 |
static const char * const pci_nic_names[] = { |
824 |
"ne2k_pci",
|
825 |
"i82551",
|
826 |
"i82557b",
|
827 |
"i82559er",
|
828 |
"rtl8139",
|
829 |
"e1000",
|
830 |
"pcnet",
|
831 |
"virtio-net-pci",
|
832 |
NULL
|
833 |
}; |
834 |
|
835 |
/* Initialize a PCI NIC. */
|
836 |
/* FIXME callers should check for failure, but don't */
|
837 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
838 |
const char *default_devaddr) |
839 |
{ |
840 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
841 |
PCIBus *bus; |
842 |
int devfn;
|
843 |
PCIDevice *pci_dev; |
844 |
DeviceState *dev; |
845 |
int i;
|
846 |
|
847 |
i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
848 |
if (i < 0) |
849 |
return NULL; |
850 |
|
851 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
852 |
if (!bus) {
|
853 |
qemu_error("Invalid PCI device address %s for device %s\n",
|
854 |
devaddr, pci_nic_names[i]); |
855 |
return NULL; |
856 |
} |
857 |
|
858 |
pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
859 |
dev = &pci_dev->qdev; |
860 |
if (nd->id)
|
861 |
dev->id = qemu_strdup(nd->id); |
862 |
dev->nd = nd; |
863 |
if (qdev_init(dev) < 0) |
864 |
return NULL; |
865 |
nd->private = dev; |
866 |
return pci_dev;
|
867 |
} |
868 |
|
869 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
870 |
const char *default_devaddr) |
871 |
{ |
872 |
PCIDevice *res; |
873 |
|
874 |
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
875 |
exit(0);
|
876 |
|
877 |
res = pci_nic_init(nd, default_model, default_devaddr); |
878 |
if (!res)
|
879 |
exit(1);
|
880 |
return res;
|
881 |
} |
882 |
|
883 |
typedef struct { |
884 |
PCIDevice dev; |
885 |
PCIBus bus; |
886 |
uint32_t vid; |
887 |
uint32_t did; |
888 |
} PCIBridge; |
889 |
|
890 |
static void pci_bridge_write_config(PCIDevice *d, |
891 |
uint32_t address, uint32_t val, int len)
|
892 |
{ |
893 |
PCIBridge *s = (PCIBridge *)d; |
894 |
|
895 |
pci_default_write_config(d, address, val, len); |
896 |
s->bus.bus_num = d->config[PCI_SECONDARY_BUS]; |
897 |
} |
898 |
|
899 |
PCIBus *pci_find_bus(int bus_num)
|
900 |
{ |
901 |
PCIBus *bus = first_bus; |
902 |
|
903 |
while (bus && bus->bus_num != bus_num)
|
904 |
bus = bus->next; |
905 |
|
906 |
return bus;
|
907 |
} |
908 |
|
909 |
PCIDevice *pci_find_device(int bus_num, int slot, int function) |
910 |
{ |
911 |
PCIBus *bus = pci_find_bus(bus_num); |
912 |
|
913 |
if (!bus)
|
914 |
return NULL; |
915 |
|
916 |
return bus->devices[PCI_DEVFN(slot, function)];
|
917 |
} |
918 |
|
919 |
static int pci_bridge_initfn(PCIDevice *dev) |
920 |
{ |
921 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
922 |
|
923 |
pci_config_set_vendor_id(s->dev.config, s->vid); |
924 |
pci_config_set_device_id(s->dev.config, s->did); |
925 |
|
926 |
s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
927 |
s->dev.config[0x05] = 0x00; |
928 |
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
929 |
s->dev.config[0x07] = 0x00; // status = fast devsel |
930 |
s->dev.config[0x08] = 0x00; // revision |
931 |
s->dev.config[0x09] = 0x00; // programming i/f |
932 |
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
933 |
s->dev.config[0x0D] = 0x10; // latency_timer |
934 |
s->dev.config[PCI_HEADER_TYPE] = |
935 |
PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
|
936 |
s->dev.config[0x1E] = 0xa0; // secondary status |
937 |
return 0; |
938 |
} |
939 |
|
940 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
941 |
pci_map_irq_fn map_irq, const char *name) |
942 |
{ |
943 |
PCIDevice *dev; |
944 |
PCIBridge *s; |
945 |
|
946 |
dev = pci_create(bus, devfn, "pci-bridge");
|
947 |
qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
|
948 |
qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
|
949 |
qdev_init_nofail(&dev->qdev); |
950 |
|
951 |
s = DO_UPCAST(PCIBridge, dev, dev); |
952 |
pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name); |
953 |
return &s->bus;
|
954 |
} |
955 |
|
956 |
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
957 |
{ |
958 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
959 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
960 |
PCIBus *bus; |
961 |
int devfn, rc;
|
962 |
|
963 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
964 |
devfn = pci_dev->devfn; |
965 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
966 |
info->config_read, info->config_write); |
967 |
assert(pci_dev); |
968 |
rc = info->init(pci_dev); |
969 |
if (rc != 0) |
970 |
return rc;
|
971 |
if (qdev->hotplugged)
|
972 |
bus->hotplug(pci_dev, 1);
|
973 |
return 0; |
974 |
} |
975 |
|
976 |
static int pci_unplug_device(DeviceState *qdev) |
977 |
{ |
978 |
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
979 |
|
980 |
dev->bus->hotplug(dev, 0);
|
981 |
return 0; |
982 |
} |
983 |
|
984 |
void pci_qdev_register(PCIDeviceInfo *info)
|
985 |
{ |
986 |
info->qdev.init = pci_qdev_init; |
987 |
info->qdev.unplug = pci_unplug_device; |
988 |
info->qdev.exit = pci_unregister_device; |
989 |
info->qdev.bus_info = &pci_bus_info; |
990 |
qdev_register(&info->qdev); |
991 |
} |
992 |
|
993 |
void pci_qdev_register_many(PCIDeviceInfo *info)
|
994 |
{ |
995 |
while (info->qdev.name) {
|
996 |
pci_qdev_register(info); |
997 |
info++; |
998 |
} |
999 |
} |
1000 |
|
1001 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1002 |
{ |
1003 |
DeviceState *dev; |
1004 |
|
1005 |
dev = qdev_create(&bus->qbus, name); |
1006 |
qdev_prop_set_uint32(dev, "addr", devfn);
|
1007 |
return DO_UPCAST(PCIDevice, qdev, dev);
|
1008 |
} |
1009 |
|
1010 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1011 |
{ |
1012 |
PCIDevice *dev = pci_create(bus, devfn, name); |
1013 |
qdev_init_nofail(&dev->qdev); |
1014 |
return dev;
|
1015 |
} |
1016 |
|
1017 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
1018 |
{ |
1019 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
1020 |
int i;
|
1021 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
|
1022 |
if (pdev->used[i])
|
1023 |
offset = i + 1;
|
1024 |
else if (i - offset + 1 == size) |
1025 |
return offset;
|
1026 |
return 0; |
1027 |
} |
1028 |
|
1029 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
1030 |
uint8_t *prev_p) |
1031 |
{ |
1032 |
uint8_t next, prev; |
1033 |
|
1034 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
1035 |
return 0; |
1036 |
|
1037 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1038 |
prev = next + PCI_CAP_LIST_NEXT) |
1039 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
1040 |
break;
|
1041 |
|
1042 |
if (prev_p)
|
1043 |
*prev_p = prev; |
1044 |
return next;
|
1045 |
} |
1046 |
|
1047 |
/* Reserve space and add capability to the linked list in pci config space */
|
1048 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1049 |
{ |
1050 |
uint8_t offset = pci_find_space(pdev, size); |
1051 |
uint8_t *config = pdev->config + offset; |
1052 |
if (!offset)
|
1053 |
return -ENOSPC;
|
1054 |
config[PCI_CAP_LIST_ID] = cap_id; |
1055 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
1056 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
1057 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
1058 |
memset(pdev->used + offset, 0xFF, size);
|
1059 |
/* Make capability read-only by default */
|
1060 |
memset(pdev->wmask + offset, 0, size);
|
1061 |
/* Check capability by default */
|
1062 |
memset(pdev->cmask + offset, 0xFF, size);
|
1063 |
return offset;
|
1064 |
} |
1065 |
|
1066 |
/* Unlink capability from the pci config space. */
|
1067 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1068 |
{ |
1069 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
1070 |
if (!offset)
|
1071 |
return;
|
1072 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
1073 |
/* Make capability writeable again */
|
1074 |
memset(pdev->wmask + offset, 0xff, size);
|
1075 |
/* Clear cmask as device-specific registers can't be checked */
|
1076 |
memset(pdev->cmask + offset, 0, size);
|
1077 |
memset(pdev->used + offset, 0, size);
|
1078 |
|
1079 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
1080 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
1081 |
} |
1082 |
|
1083 |
/* Reserve space for capability at a known offset (to call after load). */
|
1084 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
1085 |
{ |
1086 |
memset(pdev->used + offset, 0xff, size);
|
1087 |
} |
1088 |
|
1089 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
1090 |
{ |
1091 |
return pci_find_capability_list(pdev, cap_id, NULL); |
1092 |
} |
1093 |
|
1094 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
1095 |
{ |
1096 |
PCIDevice *d = (PCIDevice *)dev; |
1097 |
const pci_class_desc *desc;
|
1098 |
char ctxt[64]; |
1099 |
PCIIORegion *r; |
1100 |
int i, class;
|
1101 |
|
1102 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
1103 |
desc = pci_class_descriptions; |
1104 |
while (desc->desc && class != desc->class)
|
1105 |
desc++; |
1106 |
if (desc->desc) {
|
1107 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
1108 |
} else {
|
1109 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
1110 |
} |
1111 |
|
1112 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
1113 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
1114 |
indent, "", ctxt,
|
1115 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7, |
1116 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
1117 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))), |
1118 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))), |
1119 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID)))); |
1120 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1121 |
r = &d->io_regions[i]; |
1122 |
if (!r->size)
|
1123 |
continue;
|
1124 |
monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "", |
1125 |
i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem", |
1126 |
r->addr, r->addr + r->size - 1);
|
1127 |
} |
1128 |
} |
1129 |
|
1130 |
static PCIDeviceInfo bridge_info = {
|
1131 |
.qdev.name = "pci-bridge",
|
1132 |
.qdev.size = sizeof(PCIBridge),
|
1133 |
.init = pci_bridge_initfn, |
1134 |
.config_write = pci_bridge_write_config, |
1135 |
.qdev.props = (Property[]) { |
1136 |
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), |
1137 |
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), |
1138 |
DEFINE_PROP_END_OF_LIST(), |
1139 |
} |
1140 |
}; |
1141 |
|
1142 |
static void pci_register_devices(void) |
1143 |
{ |
1144 |
pci_qdev_register(&bridge_info); |
1145 |
} |
1146 |
|
1147 |
device_init(pci_register_devices) |