Revision e24dc9fe
| b/tcg/tci/tcg-target.c | ||
|---|---|---|
| 122 | 122 |
{ INDEX_op_rotl_i32, { R, RI, RI } },
|
| 123 | 123 |
{ INDEX_op_rotr_i32, { R, RI, RI } },
|
| 124 | 124 |
#endif |
| 125 |
#if TCG_TARGET_HAS_deposit_i32 |
|
| 126 |
{ INDEX_op_deposit_i32, { R, "0", R } },
|
|
| 127 |
#endif |
|
| 125 | 128 |
|
| 126 | 129 |
{ INDEX_op_brcond_i32, { R, RI } },
|
| 127 | 130 |
|
| ... | ... | |
| 200 | 203 |
{ INDEX_op_rotl_i64, { R, RI, RI } },
|
| 201 | 204 |
{ INDEX_op_rotr_i64, { R, RI, RI } },
|
| 202 | 205 |
#endif |
| 206 |
#if TCG_TARGET_HAS_deposit_i64 |
|
| 207 |
{ INDEX_op_deposit_i64, { R, "0", R } },
|
|
| 208 |
#endif |
|
| 203 | 209 |
{ INDEX_op_brcond_i64, { R, RI } },
|
| 204 | 210 |
|
| 205 | 211 |
#if TCG_TARGET_HAS_ext8s_i64 |
| ... | ... | |
| 653 | 659 |
tcg_out_ri32(s, const_args[1], args[1]); |
| 654 | 660 |
tcg_out_ri32(s, const_args[2], args[2]); |
| 655 | 661 |
break; |
| 662 |
case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ |
|
| 663 |
tcg_out_r(s, args[0]); |
|
| 664 |
tcg_out_r(s, args[1]); |
|
| 665 |
tcg_out_r(s, args[2]); |
|
| 666 |
assert(args[3] <= UINT8_MAX); |
|
| 667 |
tcg_out8(s, args[3]); |
|
| 668 |
assert(args[4] <= UINT8_MAX); |
|
| 669 |
tcg_out8(s, args[4]); |
|
| 670 |
break; |
|
| 656 | 671 |
|
| 657 | 672 |
#if TCG_TARGET_REG_BITS == 64 |
| 658 | 673 |
case INDEX_op_mov_i64: |
| ... | ... | |
| 680 | 695 |
tcg_out_ri64(s, const_args[1], args[1]); |
| 681 | 696 |
tcg_out_ri64(s, const_args[2], args[2]); |
| 682 | 697 |
break; |
| 698 |
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ |
|
| 699 |
tcg_out_r(s, args[0]); |
|
| 700 |
tcg_out_r(s, args[1]); |
|
| 701 |
tcg_out_r(s, args[2]); |
|
| 702 |
assert(args[3] <= UINT8_MAX); |
|
| 703 |
tcg_out8(s, args[3]); |
|
| 704 |
assert(args[4] <= UINT8_MAX); |
|
| 705 |
tcg_out8(s, args[4]); |
|
| 706 |
break; |
|
| 683 | 707 |
case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
| 684 | 708 |
case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
| 685 | 709 |
case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
| b/tcg/tci/tcg-target.h | ||
|---|---|---|
| 67 | 67 |
#define TCG_TARGET_HAS_ext8u_i32 1 |
| 68 | 68 |
#define TCG_TARGET_HAS_ext16u_i32 1 |
| 69 | 69 |
#define TCG_TARGET_HAS_andc_i32 0 |
| 70 |
#define TCG_TARGET_HAS_deposit_i32 0
|
|
| 70 |
#define TCG_TARGET_HAS_deposit_i32 1
|
|
| 71 | 71 |
#define TCG_TARGET_HAS_eqv_i32 0 |
| 72 | 72 |
#define TCG_TARGET_HAS_nand_i32 0 |
| 73 | 73 |
#define TCG_TARGET_HAS_nor_i32 0 |
| ... | ... | |
| 81 | 81 |
#define TCG_TARGET_HAS_bswap16_i64 1 |
| 82 | 82 |
#define TCG_TARGET_HAS_bswap32_i64 1 |
| 83 | 83 |
#define TCG_TARGET_HAS_bswap64_i64 1 |
| 84 |
#define TCG_TARGET_HAS_deposit_i64 0
|
|
| 84 |
#define TCG_TARGET_HAS_deposit_i64 1
|
|
| 85 | 85 |
/* Not more than one of the next two defines must be 1. */ |
| 86 | 86 |
#define TCG_TARGET_HAS_div_i64 0 |
| 87 | 87 |
#define TCG_TARGET_HAS_div2_i64 0 |
| b/tci.c | ||
|---|---|---|
| 689 | 689 |
tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2))); |
| 690 | 690 |
break; |
| 691 | 691 |
#endif |
| 692 |
#if TCG_TARGET_HAS_deposit_i32 |
|
| 693 |
case INDEX_op_deposit_i32: |
|
| 694 |
t0 = *tb_ptr++; |
|
| 695 |
t1 = tci_read_r32(&tb_ptr); |
|
| 696 |
t2 = tci_read_r32(&tb_ptr); |
|
| 697 |
tmp16 = *tb_ptr++; |
|
| 698 |
tmp8 = *tb_ptr++; |
|
| 699 |
tmp32 = (((1 << tmp8) - 1) << tmp16); |
|
| 700 |
tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); |
|
| 701 |
break; |
|
| 702 |
#endif |
|
| 692 | 703 |
case INDEX_op_brcond_i32: |
| 693 | 704 |
t0 = tci_read_r32(&tb_ptr); |
| 694 | 705 |
t1 = tci_read_ri32(&tb_ptr); |
| ... | ... | |
| 936 | 947 |
TODO(); |
| 937 | 948 |
break; |
| 938 | 949 |
#endif |
| 950 |
#if TCG_TARGET_HAS_deposit_i64 |
|
| 951 |
case INDEX_op_deposit_i64: |
|
| 952 |
t0 = *tb_ptr++; |
|
| 953 |
t1 = tci_read_r64(&tb_ptr); |
|
| 954 |
t2 = tci_read_r64(&tb_ptr); |
|
| 955 |
tmp16 = *tb_ptr++; |
|
| 956 |
tmp8 = *tb_ptr++; |
|
| 957 |
tmp64 = (((1ULL << tmp8) - 1) << tmp16); |
|
| 958 |
tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); |
|
| 959 |
break; |
|
| 960 |
#endif |
|
| 939 | 961 |
case INDEX_op_brcond_i64: |
| 940 | 962 |
t0 = tci_read_r64(&tb_ptr); |
| 941 | 963 |
t1 = tci_read_ri64(&tb_ptr); |
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