root / tcg / tci / tcg-target.c @ e24dc9fe
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009, 2011 Stefan Weil
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* TODO list:
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* - See TODO comments in code.
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*/
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/* Marker for missing code. */
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#define TODO() \
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do { \
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fprintf(stderr, "TODO %s:%u: %s()\n", \
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__FILE__, __LINE__, __func__); \ |
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tcg_abort(); \ |
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} while (0) |
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/* Single bit n. */
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#define BIT(n) (1 << (n)) |
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/* Bitfield n...m (in 32 bit value). */
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* Used for function call generation. */
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#define TCG_REG_CALL_STACK TCG_REG_R4
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#define TCG_TARGET_STACK_ALIGN 16 |
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#define TCG_TARGET_CALL_STACK_OFFSET 0 |
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/* TODO: documentation. */
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static uint8_t *tb_ret_addr;
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/* Macros used in tcg_target_op_defs. */
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#define R "r" |
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#define RI "ri" |
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#if TCG_TARGET_REG_BITS == 32 |
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# define R64 "r", "r" |
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#else
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# define R64 "r" |
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#endif
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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# define L "L", "L" |
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# define S "S", "S" |
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#else
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# define L "L" |
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# define S "S" |
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#endif
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/* TODO: documentation. */
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static const TCGTargetOpDef tcg_target_op_defs[] = { |
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{ INDEX_op_exit_tb, { NULL } },
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{ INDEX_op_goto_tb, { NULL } },
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{ INDEX_op_call, { RI } }, |
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{ INDEX_op_br, { NULL } },
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{ INDEX_op_mov_i32, { R, R } }, |
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{ INDEX_op_movi_i32, { R } }, |
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{ INDEX_op_ld8u_i32, { R, R } }, |
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{ INDEX_op_ld8s_i32, { R, R } }, |
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{ INDEX_op_ld16u_i32, { R, R } }, |
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{ INDEX_op_ld16s_i32, { R, R } }, |
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{ INDEX_op_ld_i32, { R, R } }, |
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{ INDEX_op_st8_i32, { R, R } }, |
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{ INDEX_op_st16_i32, { R, R } }, |
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{ INDEX_op_st_i32, { R, R } }, |
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{ INDEX_op_add_i32, { R, RI, RI } }, |
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{ INDEX_op_sub_i32, { R, RI, RI } }, |
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{ INDEX_op_mul_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_div_i32
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{ INDEX_op_div_i32, { R, R, R } }, |
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{ INDEX_op_divu_i32, { R, R, R } }, |
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{ INDEX_op_rem_i32, { R, R, R } }, |
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{ INDEX_op_remu_i32, { R, R, R } }, |
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#elif TCG_TARGET_HAS_div2_i32
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{ INDEX_op_div2_i32, { R, R, "0", "1", R } }, |
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{ INDEX_op_divu2_i32, { R, R, "0", "1", R } }, |
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#endif
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/* TODO: Does R, RI, RI result in faster code than R, R, RI?
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If both operands are constants, we can optimize. */
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{ INDEX_op_and_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_andc_i32
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{ INDEX_op_andc_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_eqv_i32
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{ INDEX_op_eqv_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nand_i32
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{ INDEX_op_nand_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nor_i32
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{ INDEX_op_nor_i32, { R, RI, RI } }, |
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#endif
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{ INDEX_op_or_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_orc_i32
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{ INDEX_op_orc_i32, { R, RI, RI } }, |
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#endif
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{ INDEX_op_xor_i32, { R, RI, RI } }, |
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{ INDEX_op_shl_i32, { R, RI, RI } }, |
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{ INDEX_op_shr_i32, { R, RI, RI } }, |
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{ INDEX_op_sar_i32, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_rot_i32
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{ INDEX_op_rotl_i32, { R, RI, RI } }, |
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{ INDEX_op_rotr_i32, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_deposit_i32
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{ INDEX_op_deposit_i32, { R, "0", R } },
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#endif
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{ INDEX_op_brcond_i32, { R, RI } }, |
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{ INDEX_op_setcond_i32, { R, R, RI } }, |
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#if TCG_TARGET_REG_BITS == 64 |
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{ INDEX_op_setcond_i64, { R, R, RI } }, |
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#endif /* TCG_TARGET_REG_BITS == 64 */ |
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#if TCG_TARGET_REG_BITS == 32 |
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/* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
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{ INDEX_op_add2_i32, { R, R, R, R, R, R } }, |
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{ INDEX_op_sub2_i32, { R, R, R, R, R, R } }, |
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{ INDEX_op_brcond2_i32, { R, R, RI, RI } }, |
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{ INDEX_op_mulu2_i32, { R, R, R, R } }, |
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{ INDEX_op_setcond2_i32, { R, R, R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_not_i32
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{ INDEX_op_not_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_neg_i32
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{ INDEX_op_neg_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_REG_BITS == 64 |
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{ INDEX_op_mov_i64, { R, R } }, |
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{ INDEX_op_movi_i64, { R } }, |
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{ INDEX_op_ld8u_i64, { R, R } }, |
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{ INDEX_op_ld8s_i64, { R, R } }, |
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{ INDEX_op_ld16u_i64, { R, R } }, |
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{ INDEX_op_ld16s_i64, { R, R } }, |
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{ INDEX_op_ld32u_i64, { R, R } }, |
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{ INDEX_op_ld32s_i64, { R, R } }, |
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{ INDEX_op_ld_i64, { R, R } }, |
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{ INDEX_op_st8_i64, { R, R } }, |
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{ INDEX_op_st16_i64, { R, R } }, |
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{ INDEX_op_st32_i64, { R, R } }, |
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{ INDEX_op_st_i64, { R, R } }, |
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{ INDEX_op_add_i64, { R, RI, RI } }, |
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{ INDEX_op_sub_i64, { R, RI, RI } }, |
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{ INDEX_op_mul_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_div_i64
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{ INDEX_op_div_i64, { R, R, R } }, |
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{ INDEX_op_divu_i64, { R, R, R } }, |
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{ INDEX_op_rem_i64, { R, R, R } }, |
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{ INDEX_op_remu_i64, { R, R, R } }, |
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#elif TCG_TARGET_HAS_div2_i64
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{ INDEX_op_div2_i64, { R, R, "0", "1", R } }, |
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{ INDEX_op_divu2_i64, { R, R, "0", "1", R } }, |
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#endif
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{ INDEX_op_and_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_andc_i64
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{ INDEX_op_andc_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_eqv_i64
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{ INDEX_op_eqv_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nand_i64
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{ INDEX_op_nand_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_nor_i64
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{ INDEX_op_nor_i64, { R, RI, RI } }, |
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#endif
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{ INDEX_op_or_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_orc_i64
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{ INDEX_op_orc_i64, { R, RI, RI } }, |
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#endif
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{ INDEX_op_xor_i64, { R, RI, RI } }, |
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{ INDEX_op_shl_i64, { R, RI, RI } }, |
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{ INDEX_op_shr_i64, { R, RI, RI } }, |
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{ INDEX_op_sar_i64, { R, RI, RI } }, |
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#if TCG_TARGET_HAS_rot_i64
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{ INDEX_op_rotl_i64, { R, RI, RI } }, |
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{ INDEX_op_rotr_i64, { R, RI, RI } }, |
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#endif
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#if TCG_TARGET_HAS_deposit_i64
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{ INDEX_op_deposit_i64, { R, "0", R } },
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#endif
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{ INDEX_op_brcond_i64, { R, RI } }, |
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#if TCG_TARGET_HAS_ext8s_i64
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{ INDEX_op_ext8s_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16s_i64
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{ INDEX_op_ext16s_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext32s_i64
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{ INDEX_op_ext32s_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext8u_i64
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{ INDEX_op_ext8u_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16u_i64
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{ INDEX_op_ext16u_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext32u_i64
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{ INDEX_op_ext32u_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap16_i64
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{ INDEX_op_bswap16_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap32_i64
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{ INDEX_op_bswap32_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap64_i64
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{ INDEX_op_bswap64_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_not_i64
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{ INDEX_op_not_i64, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_neg_i64
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{ INDEX_op_neg_i64, { R, R } }, |
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#endif
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#endif /* TCG_TARGET_REG_BITS == 64 */ |
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{ INDEX_op_qemu_ld8u, { R, L } }, |
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{ INDEX_op_qemu_ld8s, { R, L } }, |
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{ INDEX_op_qemu_ld16u, { R, L } }, |
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{ INDEX_op_qemu_ld16s, { R, L } }, |
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{ INDEX_op_qemu_ld32, { R, L } }, |
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#if TCG_TARGET_REG_BITS == 64 |
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{ INDEX_op_qemu_ld32u, { R, L } }, |
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{ INDEX_op_qemu_ld32s, { R, L } }, |
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#endif
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{ INDEX_op_qemu_ld64, { R64, L } }, |
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{ INDEX_op_qemu_st8, { R, S } }, |
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{ INDEX_op_qemu_st16, { R, S } }, |
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{ INDEX_op_qemu_st32, { R, S } }, |
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{ INDEX_op_qemu_st64, { R64, S } }, |
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#if TCG_TARGET_HAS_ext8s_i32
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{ INDEX_op_ext8s_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16s_i32
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{ INDEX_op_ext16s_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext8u_i32
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{ INDEX_op_ext8u_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_ext16u_i32
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{ INDEX_op_ext16u_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap16_i32
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{ INDEX_op_bswap16_i32, { R, R } }, |
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#endif
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#if TCG_TARGET_HAS_bswap32_i32
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{ INDEX_op_bswap32_i32, { R, R } }, |
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#endif
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{ -1 },
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}; |
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_R0, |
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TCG_REG_R1, |
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TCG_REG_R2, |
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TCG_REG_R3, |
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
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#endif
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TCG_REG_R5, |
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TCG_REG_R6, |
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TCG_REG_R7, |
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#if TCG_TARGET_NB_REGS >= 16 |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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TCG_REG_R11, |
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TCG_REG_R12, |
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TCG_REG_R13, |
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TCG_REG_R14, |
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TCG_REG_R15, |
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#endif
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}; |
307 |
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#if MAX_OPC_PARAM_IARGS != 5 |
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# error Fix needed, number of supported input arguments changed!
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#endif
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static const int tcg_target_call_iarg_regs[] = { |
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TCG_REG_R0, |
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TCG_REG_R1, |
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TCG_REG_R2, |
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TCG_REG_R3, |
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
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#endif
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TCG_REG_R5, |
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#if TCG_TARGET_REG_BITS == 32 |
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/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
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TCG_REG_R6, |
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TCG_REG_R7, |
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#if TCG_TARGET_NB_REGS >= 16 |
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TCG_REG_R8, |
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TCG_REG_R9, |
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TCG_REG_R10, |
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#else
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# error Too few input registers available
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#endif
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#endif
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}; |
334 |
|
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static const int tcg_target_call_oarg_regs[] = { |
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TCG_REG_R0, |
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#if TCG_TARGET_REG_BITS == 32 |
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TCG_REG_R1 |
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#endif
|
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}; |
341 |
|
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#ifndef NDEBUG
|
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static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
344 |
"r00",
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"r01",
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"r02",
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"r03",
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"r04",
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"r05",
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"r06",
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"r07",
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#if TCG_TARGET_NB_REGS >= 16 |
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"r08",
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"r09",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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#if TCG_TARGET_NB_REGS >= 32 |
362 |
"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
|
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"r30",
|
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"r31"
|
378 |
#endif
|
379 |
#endif
|
380 |
}; |
381 |
#endif
|
382 |
|
383 |
static void patch_reloc(uint8_t *code_ptr, int type, |
384 |
tcg_target_long value, tcg_target_long addend) |
385 |
{ |
386 |
/* tcg_out_reloc always uses the same type, addend. */
|
387 |
assert(type == sizeof(tcg_target_long));
|
388 |
assert(addend == 0);
|
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assert(value != 0);
|
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*(tcg_target_long *)code_ptr = value; |
391 |
} |
392 |
|
393 |
/* Parse target specific constraints. */
|
394 |
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
395 |
{ |
396 |
const char *ct_str = *pct_str; |
397 |
switch (ct_str[0]) { |
398 |
case 'r': |
399 |
case 'L': /* qemu_ld constraint */ |
400 |
case 'S': /* qemu_st constraint */ |
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ct->ct |= TCG_CT_REG; |
402 |
tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1); |
403 |
break;
|
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default:
|
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return -1; |
406 |
} |
407 |
ct_str++; |
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*pct_str = ct_str; |
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return 0; |
410 |
} |
411 |
|
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#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
|
413 |
/* Show current bytecode. Used by tcg interpreter. */
|
414 |
void tci_disas(uint8_t opc)
|
415 |
{ |
416 |
const TCGOpDef *def = &tcg_op_defs[opc];
|
417 |
fprintf(stderr, "TCG %s %u, %u, %u\n",
|
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def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs); |
419 |
} |
420 |
#endif
|
421 |
|
422 |
/* Write value (native size). */
|
423 |
static void tcg_out_i(TCGContext *s, tcg_target_ulong v) |
424 |
{ |
425 |
*(tcg_target_ulong *)s->code_ptr = v; |
426 |
s->code_ptr += sizeof(tcg_target_ulong);
|
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} |
428 |
|
429 |
/* Write 64 bit value. */
|
430 |
static void tcg_out64(TCGContext *s, uint64_t v) |
431 |
{ |
432 |
*(uint64_t *)s->code_ptr = v; |
433 |
s->code_ptr += sizeof(v);
|
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} |
435 |
|
436 |
/* Write opcode. */
|
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static void tcg_out_op_t(TCGContext *s, TCGOpcode op) |
438 |
{ |
439 |
tcg_out8(s, op); |
440 |
tcg_out8(s, 0);
|
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} |
442 |
|
443 |
/* Write register. */
|
444 |
static void tcg_out_r(TCGContext *s, TCGArg t0) |
445 |
{ |
446 |
assert(t0 < TCG_TARGET_NB_REGS); |
447 |
tcg_out8(s, t0); |
448 |
} |
449 |
|
450 |
/* Write register or constant (native size). */
|
451 |
static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg) |
452 |
{ |
453 |
if (const_arg) {
|
454 |
assert(const_arg == 1);
|
455 |
tcg_out8(s, TCG_CONST); |
456 |
tcg_out_i(s, arg); |
457 |
} else {
|
458 |
tcg_out_r(s, arg); |
459 |
} |
460 |
} |
461 |
|
462 |
/* Write register or constant (32 bit). */
|
463 |
static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg) |
464 |
{ |
465 |
if (const_arg) {
|
466 |
assert(const_arg == 1);
|
467 |
tcg_out8(s, TCG_CONST); |
468 |
tcg_out32(s, arg); |
469 |
} else {
|
470 |
tcg_out_r(s, arg); |
471 |
} |
472 |
} |
473 |
|
474 |
#if TCG_TARGET_REG_BITS == 64 |
475 |
/* Write register or constant (64 bit). */
|
476 |
static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg) |
477 |
{ |
478 |
if (const_arg) {
|
479 |
assert(const_arg == 1);
|
480 |
tcg_out8(s, TCG_CONST); |
481 |
tcg_out64(s, arg); |
482 |
} else {
|
483 |
tcg_out_r(s, arg); |
484 |
} |
485 |
} |
486 |
#endif
|
487 |
|
488 |
/* Write label. */
|
489 |
static void tci_out_label(TCGContext *s, TCGArg arg) |
490 |
{ |
491 |
TCGLabel *label = &s->labels[arg]; |
492 |
if (label->has_value) {
|
493 |
tcg_out_i(s, label->u.value); |
494 |
assert(label->u.value); |
495 |
} else {
|
496 |
tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), arg, 0); |
497 |
s->code_ptr += sizeof(tcg_target_ulong);
|
498 |
} |
499 |
} |
500 |
|
501 |
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, |
502 |
tcg_target_long arg2) |
503 |
{ |
504 |
uint8_t *old_code_ptr = s->code_ptr; |
505 |
if (type == TCG_TYPE_I32) {
|
506 |
tcg_out_op_t(s, INDEX_op_ld_i32); |
507 |
tcg_out_r(s, ret); |
508 |
tcg_out_r(s, arg1); |
509 |
tcg_out32(s, arg2); |
510 |
} else {
|
511 |
assert(type == TCG_TYPE_I64); |
512 |
#if TCG_TARGET_REG_BITS == 64 |
513 |
tcg_out_op_t(s, INDEX_op_ld_i64); |
514 |
tcg_out_r(s, ret); |
515 |
tcg_out_r(s, arg1); |
516 |
assert(arg2 == (uint32_t)arg2); |
517 |
tcg_out32(s, arg2); |
518 |
#else
|
519 |
TODO(); |
520 |
#endif
|
521 |
} |
522 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
523 |
} |
524 |
|
525 |
static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
526 |
{ |
527 |
uint8_t *old_code_ptr = s->code_ptr; |
528 |
assert(ret != arg); |
529 |
#if TCG_TARGET_REG_BITS == 32 |
530 |
tcg_out_op_t(s, INDEX_op_mov_i32); |
531 |
#else
|
532 |
tcg_out_op_t(s, INDEX_op_mov_i64); |
533 |
#endif
|
534 |
tcg_out_r(s, ret); |
535 |
tcg_out_r(s, arg); |
536 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
537 |
} |
538 |
|
539 |
static void tcg_out_movi(TCGContext *s, TCGType type, |
540 |
TCGReg t0, tcg_target_long arg) |
541 |
{ |
542 |
uint8_t *old_code_ptr = s->code_ptr; |
543 |
uint32_t arg32 = arg; |
544 |
if (type == TCG_TYPE_I32 || arg == arg32) {
|
545 |
tcg_out_op_t(s, INDEX_op_movi_i32); |
546 |
tcg_out_r(s, t0); |
547 |
tcg_out32(s, arg32); |
548 |
} else {
|
549 |
assert(type == TCG_TYPE_I64); |
550 |
#if TCG_TARGET_REG_BITS == 64 |
551 |
tcg_out_op_t(s, INDEX_op_movi_i64); |
552 |
tcg_out_r(s, t0); |
553 |
tcg_out64(s, arg); |
554 |
#else
|
555 |
TODO(); |
556 |
#endif
|
557 |
} |
558 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
559 |
} |
560 |
|
561 |
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
562 |
const int *const_args) |
563 |
{ |
564 |
uint8_t *old_code_ptr = s->code_ptr; |
565 |
|
566 |
tcg_out_op_t(s, opc); |
567 |
|
568 |
switch (opc) {
|
569 |
case INDEX_op_exit_tb:
|
570 |
tcg_out64(s, args[0]);
|
571 |
break;
|
572 |
case INDEX_op_goto_tb:
|
573 |
if (s->tb_jmp_offset) {
|
574 |
/* Direct jump method. */
|
575 |
assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
|
576 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
577 |
tcg_out32(s, 0);
|
578 |
} else {
|
579 |
/* Indirect jump method. */
|
580 |
TODO(); |
581 |
} |
582 |
assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
|
583 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
584 |
break;
|
585 |
case INDEX_op_br:
|
586 |
tci_out_label(s, args[0]);
|
587 |
break;
|
588 |
case INDEX_op_call:
|
589 |
tcg_out_ri(s, const_args[0], args[0]); |
590 |
break;
|
591 |
case INDEX_op_setcond_i32:
|
592 |
tcg_out_r(s, args[0]);
|
593 |
tcg_out_r(s, args[1]);
|
594 |
tcg_out_ri32(s, const_args[2], args[2]); |
595 |
tcg_out8(s, args[3]); /* condition */ |
596 |
break;
|
597 |
#if TCG_TARGET_REG_BITS == 32 |
598 |
case INDEX_op_setcond2_i32:
|
599 |
/* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
|
600 |
tcg_out_r(s, args[0]);
|
601 |
tcg_out_r(s, args[1]);
|
602 |
tcg_out_r(s, args[2]);
|
603 |
tcg_out_ri32(s, const_args[3], args[3]); |
604 |
tcg_out_ri32(s, const_args[4], args[4]); |
605 |
tcg_out8(s, args[5]); /* condition */ |
606 |
break;
|
607 |
#elif TCG_TARGET_REG_BITS == 64 |
608 |
case INDEX_op_setcond_i64:
|
609 |
tcg_out_r(s, args[0]);
|
610 |
tcg_out_r(s, args[1]);
|
611 |
tcg_out_ri64(s, const_args[2], args[2]); |
612 |
tcg_out8(s, args[3]); /* condition */ |
613 |
break;
|
614 |
#endif
|
615 |
case INDEX_op_movi_i32:
|
616 |
TODO(); /* Handled by tcg_out_movi? */
|
617 |
break;
|
618 |
case INDEX_op_ld8u_i32:
|
619 |
case INDEX_op_ld8s_i32:
|
620 |
case INDEX_op_ld16u_i32:
|
621 |
case INDEX_op_ld16s_i32:
|
622 |
case INDEX_op_ld_i32:
|
623 |
case INDEX_op_st8_i32:
|
624 |
case INDEX_op_st16_i32:
|
625 |
case INDEX_op_st_i32:
|
626 |
case INDEX_op_ld8u_i64:
|
627 |
case INDEX_op_ld8s_i64:
|
628 |
case INDEX_op_ld16u_i64:
|
629 |
case INDEX_op_ld16s_i64:
|
630 |
case INDEX_op_ld32u_i64:
|
631 |
case INDEX_op_ld32s_i64:
|
632 |
case INDEX_op_ld_i64:
|
633 |
case INDEX_op_st8_i64:
|
634 |
case INDEX_op_st16_i64:
|
635 |
case INDEX_op_st32_i64:
|
636 |
case INDEX_op_st_i64:
|
637 |
tcg_out_r(s, args[0]);
|
638 |
tcg_out_r(s, args[1]);
|
639 |
assert(args[2] == (uint32_t)args[2]); |
640 |
tcg_out32(s, args[2]);
|
641 |
break;
|
642 |
case INDEX_op_add_i32:
|
643 |
case INDEX_op_sub_i32:
|
644 |
case INDEX_op_mul_i32:
|
645 |
case INDEX_op_and_i32:
|
646 |
case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ |
647 |
case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ |
648 |
case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ |
649 |
case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ |
650 |
case INDEX_op_or_i32:
|
651 |
case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ |
652 |
case INDEX_op_xor_i32:
|
653 |
case INDEX_op_shl_i32:
|
654 |
case INDEX_op_shr_i32:
|
655 |
case INDEX_op_sar_i32:
|
656 |
case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ |
657 |
case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ |
658 |
tcg_out_r(s, args[0]);
|
659 |
tcg_out_ri32(s, const_args[1], args[1]); |
660 |
tcg_out_ri32(s, const_args[2], args[2]); |
661 |
break;
|
662 |
case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ |
663 |
tcg_out_r(s, args[0]);
|
664 |
tcg_out_r(s, args[1]);
|
665 |
tcg_out_r(s, args[2]);
|
666 |
assert(args[3] <= UINT8_MAX);
|
667 |
tcg_out8(s, args[3]);
|
668 |
assert(args[4] <= UINT8_MAX);
|
669 |
tcg_out8(s, args[4]);
|
670 |
break;
|
671 |
|
672 |
#if TCG_TARGET_REG_BITS == 64 |
673 |
case INDEX_op_mov_i64:
|
674 |
case INDEX_op_movi_i64:
|
675 |
TODO(); |
676 |
break;
|
677 |
case INDEX_op_add_i64:
|
678 |
case INDEX_op_sub_i64:
|
679 |
case INDEX_op_mul_i64:
|
680 |
case INDEX_op_and_i64:
|
681 |
case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ |
682 |
case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ |
683 |
case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ |
684 |
case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ |
685 |
case INDEX_op_or_i64:
|
686 |
case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ |
687 |
case INDEX_op_xor_i64:
|
688 |
case INDEX_op_shl_i64:
|
689 |
case INDEX_op_shr_i64:
|
690 |
case INDEX_op_sar_i64:
|
691 |
/* TODO: Implementation of rotl_i64, rotr_i64 missing in tci.c. */
|
692 |
case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ |
693 |
case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ |
694 |
tcg_out_r(s, args[0]);
|
695 |
tcg_out_ri64(s, const_args[1], args[1]); |
696 |
tcg_out_ri64(s, const_args[2], args[2]); |
697 |
break;
|
698 |
case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ |
699 |
tcg_out_r(s, args[0]);
|
700 |
tcg_out_r(s, args[1]);
|
701 |
tcg_out_r(s, args[2]);
|
702 |
assert(args[3] <= UINT8_MAX);
|
703 |
tcg_out8(s, args[3]);
|
704 |
assert(args[4] <= UINT8_MAX);
|
705 |
tcg_out8(s, args[4]);
|
706 |
break;
|
707 |
case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
708 |
case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
709 |
case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
710 |
case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ |
711 |
TODO(); |
712 |
break;
|
713 |
case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ |
714 |
case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */ |
715 |
TODO(); |
716 |
break;
|
717 |
case INDEX_op_brcond_i64:
|
718 |
tcg_out_r(s, args[0]);
|
719 |
tcg_out_ri64(s, const_args[1], args[1]); |
720 |
tcg_out8(s, args[2]); /* condition */ |
721 |
tci_out_label(s, args[3]);
|
722 |
break;
|
723 |
case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */ |
724 |
case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */ |
725 |
case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ |
726 |
case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ |
727 |
case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ |
728 |
case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ |
729 |
case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ |
730 |
case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ |
731 |
case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ |
732 |
case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ |
733 |
case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ |
734 |
#endif /* TCG_TARGET_REG_BITS == 64 */ |
735 |
case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ |
736 |
case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ |
737 |
case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ |
738 |
case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ |
739 |
case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ |
740 |
case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ |
741 |
case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */ |
742 |
case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ |
743 |
tcg_out_r(s, args[0]);
|
744 |
tcg_out_r(s, args[1]);
|
745 |
break;
|
746 |
case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
747 |
case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
748 |
case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
749 |
case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ |
750 |
tcg_out_r(s, args[0]);
|
751 |
tcg_out_ri32(s, const_args[1], args[1]); |
752 |
tcg_out_ri32(s, const_args[2], args[2]); |
753 |
break;
|
754 |
case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ |
755 |
case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */ |
756 |
TODO(); |
757 |
break;
|
758 |
#if TCG_TARGET_REG_BITS == 32 |
759 |
case INDEX_op_add2_i32:
|
760 |
case INDEX_op_sub2_i32:
|
761 |
tcg_out_r(s, args[0]);
|
762 |
tcg_out_r(s, args[1]);
|
763 |
tcg_out_r(s, args[2]);
|
764 |
tcg_out_r(s, args[3]);
|
765 |
tcg_out_r(s, args[4]);
|
766 |
tcg_out_r(s, args[5]);
|
767 |
break;
|
768 |
case INDEX_op_brcond2_i32:
|
769 |
tcg_out_r(s, args[0]);
|
770 |
tcg_out_r(s, args[1]);
|
771 |
tcg_out_ri32(s, const_args[2], args[2]); |
772 |
tcg_out_ri32(s, const_args[3], args[3]); |
773 |
tcg_out8(s, args[4]); /* condition */ |
774 |
tci_out_label(s, args[5]);
|
775 |
break;
|
776 |
case INDEX_op_mulu2_i32:
|
777 |
tcg_out_r(s, args[0]);
|
778 |
tcg_out_r(s, args[1]);
|
779 |
tcg_out_r(s, args[2]);
|
780 |
tcg_out_r(s, args[3]);
|
781 |
break;
|
782 |
#endif
|
783 |
case INDEX_op_brcond_i32:
|
784 |
tcg_out_r(s, args[0]);
|
785 |
tcg_out_ri32(s, const_args[1], args[1]); |
786 |
tcg_out8(s, args[2]); /* condition */ |
787 |
tci_out_label(s, args[3]);
|
788 |
break;
|
789 |
case INDEX_op_qemu_ld8u:
|
790 |
case INDEX_op_qemu_ld8s:
|
791 |
case INDEX_op_qemu_ld16u:
|
792 |
case INDEX_op_qemu_ld16s:
|
793 |
case INDEX_op_qemu_ld32:
|
794 |
#if TCG_TARGET_REG_BITS == 64 |
795 |
case INDEX_op_qemu_ld32s:
|
796 |
case INDEX_op_qemu_ld32u:
|
797 |
#endif
|
798 |
tcg_out_r(s, *args++); |
799 |
tcg_out_r(s, *args++); |
800 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
801 |
tcg_out_r(s, *args++); |
802 |
#endif
|
803 |
#ifdef CONFIG_SOFTMMU
|
804 |
tcg_out_i(s, *args); |
805 |
#endif
|
806 |
break;
|
807 |
case INDEX_op_qemu_ld64:
|
808 |
tcg_out_r(s, *args++); |
809 |
#if TCG_TARGET_REG_BITS == 32 |
810 |
tcg_out_r(s, *args++); |
811 |
#endif
|
812 |
tcg_out_r(s, *args++); |
813 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
814 |
tcg_out_r(s, *args++); |
815 |
#endif
|
816 |
#ifdef CONFIG_SOFTMMU
|
817 |
tcg_out_i(s, *args); |
818 |
#endif
|
819 |
break;
|
820 |
case INDEX_op_qemu_st8:
|
821 |
case INDEX_op_qemu_st16:
|
822 |
case INDEX_op_qemu_st32:
|
823 |
tcg_out_r(s, *args++); |
824 |
tcg_out_r(s, *args++); |
825 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
826 |
tcg_out_r(s, *args++); |
827 |
#endif
|
828 |
#ifdef CONFIG_SOFTMMU
|
829 |
tcg_out_i(s, *args); |
830 |
#endif
|
831 |
break;
|
832 |
case INDEX_op_qemu_st64:
|
833 |
tcg_out_r(s, *args++); |
834 |
#if TCG_TARGET_REG_BITS == 32 |
835 |
tcg_out_r(s, *args++); |
836 |
#endif
|
837 |
tcg_out_r(s, *args++); |
838 |
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
839 |
tcg_out_r(s, *args++); |
840 |
#endif
|
841 |
#ifdef CONFIG_SOFTMMU
|
842 |
tcg_out_i(s, *args); |
843 |
#endif
|
844 |
break;
|
845 |
case INDEX_op_end:
|
846 |
TODO(); |
847 |
break;
|
848 |
default:
|
849 |
fprintf(stderr, "Missing: %s\n", tcg_op_defs[opc].name);
|
850 |
tcg_abort(); |
851 |
} |
852 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
853 |
} |
854 |
|
855 |
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, |
856 |
tcg_target_long arg2) |
857 |
{ |
858 |
uint8_t *old_code_ptr = s->code_ptr; |
859 |
if (type == TCG_TYPE_I32) {
|
860 |
tcg_out_op_t(s, INDEX_op_st_i32); |
861 |
tcg_out_r(s, arg); |
862 |
tcg_out_r(s, arg1); |
863 |
tcg_out32(s, arg2); |
864 |
} else {
|
865 |
assert(type == TCG_TYPE_I64); |
866 |
#if TCG_TARGET_REG_BITS == 64 |
867 |
tcg_out_op_t(s, INDEX_op_st_i64); |
868 |
tcg_out_r(s, arg); |
869 |
tcg_out_r(s, arg1); |
870 |
tcg_out32(s, arg2); |
871 |
#else
|
872 |
TODO(); |
873 |
#endif
|
874 |
} |
875 |
old_code_ptr[1] = s->code_ptr - old_code_ptr;
|
876 |
} |
877 |
|
878 |
/* Test if a constant matches the constraint. */
|
879 |
static int tcg_target_const_match(tcg_target_long val, |
880 |
const TCGArgConstraint *arg_ct)
|
881 |
{ |
882 |
/* No need to return 0 or 1, 0 or != 0 is good enough. */
|
883 |
return arg_ct->ct & TCG_CT_CONST;
|
884 |
} |
885 |
|
886 |
static void tcg_target_init(TCGContext *s) |
887 |
{ |
888 |
#if defined(CONFIG_DEBUG_TCG_INTERPRETER)
|
889 |
const char *envval = getenv("DEBUG_TCG"); |
890 |
if (envval) {
|
891 |
cpu_set_log(strtol(envval, NULL, 0)); |
892 |
} |
893 |
#endif
|
894 |
|
895 |
/* The current code uses uint8_t for tcg operations. */
|
896 |
assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX); |
897 |
|
898 |
/* Registers available for 32 bit operations. */
|
899 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
|
900 |
BIT(TCG_TARGET_NB_REGS) - 1);
|
901 |
/* Registers available for 64 bit operations. */
|
902 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
|
903 |
BIT(TCG_TARGET_NB_REGS) - 1);
|
904 |
/* TODO: Which registers should be set here? */
|
905 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
906 |
BIT(TCG_TARGET_NB_REGS) - 1);
|
907 |
tcg_regset_clear(s->reserved_regs); |
908 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); |
909 |
tcg_add_target_add_op_defs(tcg_target_op_defs); |
910 |
tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf), |
911 |
CPU_TEMP_BUF_NLONGS * sizeof(long)); |
912 |
} |
913 |
|
914 |
/* Generate global QEMU prologue and epilogue code. */
|
915 |
static void tcg_target_qemu_prologue(TCGContext *s) |
916 |
{ |
917 |
tb_ret_addr = s->code_ptr; |
918 |
} |