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tcg-target.c 52.2 kB
tcg-target.h 2.6 kB

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# Date Author Comment
e2542fe2 07/27/2009 10:09 pm Juan Quintela

rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN

Signed-off-by: Juan Quintela <>
Signed-off-by: Anthony Liguori <>

cb4e581f 07/18/2009 03:20 pm Laurent Desnogues

this patch improves the ARM back-end in the following way:

- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <>
Signed-off-by: Andrzej Zaborowski <>

379f6698 07/17/2009 03:12 pm Paul Brook

Userspace guest address offsetting

Re-implement GUEST_BASE support.
Offset guest ddress space by default if the guest binary contains
regions below the host mmap_min_addr.
Implement support for i386, x86-64 and arm hosts.

Signed-off-by: Riku Voipio <>...

2d69f359 07/17/2009 01:21 pm Paul Brook

ARM host fixes

Minor TCG cleanups and warning fixes for ARM hosts.

Signed-off-by: Paul Brook <>

66896cb8 03/13/2009 11:34 am aurel32

tcg: rename bswap_i32/i64 functions

Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162

419bafa5 03/10/2009 11:43 pm aurel32

tcg-arm: fix qemu_ld64

Emulating fldl on arm doesn't seem to work too well. It's the way
qemu_ld64 is translated to arm instructions.

tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);...
e63d7abd 03/08/2009 04:45 pm blueswir1

Prune unused TCG_AREGs

Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162

aef3a282 12/08/2008 01:35 am balrog

Fix 64-bit targets compilation on ARM host.

Only fix compilation, probably doesn't run.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162

0c9c3a9e 12/01/2008 01:57 pm balrog

arm: Don't potentially overwrite input registers in add2, sub2.

According to malc TCG will often genereate an add2/sub2/mul2 with low
half of the output in the same register as high half of one of the
inputs, so account for that.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162

fe33867b 12/01/2008 04:17 am balrog

Don't rely on ARM tcg_out_goto() generating just a single insn.

Otherwise when tb_exit generates a jump beyond the pc-relative range,
tcg_out_goto() spans two/three instructions and we load the tb return
value from a wrong address. This is #ifdefed out currently because...

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