Archipelago » qemu

    rn = (insn >> 16) & 0xf;

    rm = insn & 0xf;

    load = (insn & (1 << 21)) != 0;

    if ((insn & (1 << 23)) == 0) {

        /* Load store all elements.  */

        op = (insn >> 8) & 0xf;

        spacing = neon_ls_element_type[op].spacing;

        if (size == 3 && (interleave | spacing) != 1)

            return 1;

        load_reg_var(s, addr, rn);

        stride = (1 << size) * interleave;

        for (reg = 0; reg < nregs; reg++) {

            }

            rd += spacing;

        }

        stride = nregs * 8;

    } else {

        size = (insn >> 10) & 3;

            if (nregs == 3 && a == 1) {

                return 1;

            }

            load_reg_var(s, addr, rn);

            if (nregs == 1) {

                /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */

                    rd += stride;

                }

            }

            stride = (1 << size) * nregs;

        } else {

            /* Single element.  */

                abort();

            }

            nregs = ((insn >> 8) & 3) + 1;

            load_reg_var(s, addr, rn);

            for (reg = 0; reg < nregs; reg++) {

                if (load) {

                rd += stride;

                tcg_gen_addi_i32(addr, addr, 1 << size);

            }

            stride = nregs * (1 << size);

        }

    }

    if (rm != 15) {

        TCGv base;