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Name Size
cpu.h 16.8 kB
exec.h 1.2 kB
helper.c 83.4 kB
helpers.h 17.1 kB
iwmmxt_helper.c 24.7 kB
machine.c 6.7 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 9.5 kB
translate.c 324.2 kB

Latest revisions

# Date Author Comment
8e18cde3 04/01/2011 11:33 pm Peter Maydell

target-arm: Fix VLD of single element to all lanes

Fix several bugs in VLD of single element to all lanes:

The "single element to all lanes" form of VLD1 differs from those for
VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element
should be written to one or two Dregs (rather than being a register...

e318a60b 04/01/2011 11:33 pm Peter Maydell

target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space

Move the allocation and freeing of the TCG temp used for the address for
Neon load/store instructions so that we don't allocate the temporary
until we've done enough decoding to know that the instruction is not...

6aae3df1 03/22/2011 08:59 am Peter Maydell

target-arm: use make_float32() to make constant floats for VRSQRTS

The preferred way to create a constant floating point value is to use
make_float32() rather than doing a runtime int32_to_float32().
Convert the code in the VRSQRTS helper to work this way....

dda3ec49 03/22/2011 08:59 am Peter Maydell

target-arm: Fix VRECPS edge cases handling

Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0

Signed-off-by: Peter Maydell <>...

7d2aabe2 03/22/2011 08:56 am Peter Maydell

target-arm: Fix TCG temporary leaks for scalar VMULL

Fix a TCG temporary leak when translating 32-bit scalar VMULL.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

e1d177b9 03/22/2011 08:56 am Peter Maydell

target-arm: Set Q bit for overflow in SMUAD and SMLAD

SMUAD and SMLAD are supposed to set the Q bit if the addition of
the two 16x16 multiply products and optional accumulator overflows
considered as a signed value. However we were only doing this check
for the addition of the accumulator, not when adding the products,...

db6e2e65 03/22/2011 08:52 am Peter Maydell

target-arm: Fix GE bits for v6media signed modulo arithmetic

Fix the signed modulo arithmetic helpers for the v6media
instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set
the GE bits correctly (based on the result of the add or subtract
before it is truncated to 16 bits, not after)....

2a0308c5 03/22/2011 08:52 am Peter Maydell

target-arm: Fix UNDEF cases in Thumb load/store

Decode of Thumb load/store was merging together the cases of 'bit 11==0'
(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for
valid instruction patterns but meant that we would not UNDEF for the...

eda48c34 03/13/2011 04:44 pm Paolo Bonzini

inline cpu_halted into sole caller

All implementations are now the same, and there is only one caller,
so inline the function there.

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>

ca27c052 03/07/2011 10:46 am Peter Maydell

target-arm: Implement a minimal set of cp14 debug registers

Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug...

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