Revision e36f36e1 hw/cirrus_vga.c
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 25 | 25 |
#include "vl.h" |
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#include "vga_int.h" |
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|
| 28 |
//#define DEBUG_CIRRUS |
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| 29 |
|
|
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/*************************************** |
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* |
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* definitions |
| ... | ... | |
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|
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typedef struct CirrusVGAState {
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/* XXX: we use the anonymous struct/union gcc 3.x extension */ |
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struct VGAState; |
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__extension__ struct VGAState;
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|
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int cirrus_linear_io_addr; |
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int cirrus_mmio_io_addr; |
| ... | ... | |
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uint32_t line_offset; |
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|
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line_offset = s->cr[0x13] |
| 1039 |
| ((s->cr[0x1b] & 0x10) << 8);
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|
| 1041 |
| ((s->cr[0x1b] & 0x10) << 4);
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|
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line_offset <<= 3; |
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*pline_offset = line_offset; |
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|
| ... | ... | |
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|
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/*************************************** |
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* |
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* memory-mapped I/O (vga) |
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* |
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***************************************/ |
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|
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static uint8_t cirrus_mmio_vga_read(CirrusVGAState * s, unsigned address) |
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{
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#ifdef DEBUG_CIRRUS |
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printf("cirrus: mmio vga read (unimplemented) - address 0x%04x\n",
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address); |
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#endif |
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return 0xff; |
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} |
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|
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static void cirrus_mmio_vga_write(CirrusVGAState * s, unsigned address, |
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uint8_t value) |
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{
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#ifdef DEBUG_CIRRUS |
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printf |
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| 1842 |
("cirrus: mmio vga write (unimplemented) - address 0x%04x, value 0x%02x\n",
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| 1843 |
address, value); |
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| 1844 |
#endif |
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| 1845 |
} |
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| 1846 |
|
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| 1847 |
/*************************************** |
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| 1848 |
* |
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* write mode 4/5 |
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* |
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* assume TARGET_PAGE_SIZE >= 16 |
| ... | ... | |
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cirrus_linear_writel, |
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}; |
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| 2224 |
/*************************************** |
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| 2225 |
* |
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* memory-mapped I/O access |
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* |
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***************************************/ |
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|
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static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) |
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{
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CirrusVGAState *s = (CirrusVGAState *) opaque; |
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addr &= CIRRUS_PNPMMIO_SIZE - 1; |
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/* ??? Does CLGD5430 have memory-mapped VGA registers ??? */ |
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return (addr >= 0x100) ? |
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cirrus_mmio_blt_read(s, addr - 0x100) : |
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cirrus_mmio_vga_read(s, addr); |
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} |
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|
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static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t v; |
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#ifdef TARGET_WORDS_BIGENDIAN |
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v = cirrus_mmio_readb(opaque, addr) << 8; |
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v |= cirrus_mmio_readb(opaque, addr + 1); |
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#else |
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v = cirrus_mmio_readb(opaque, addr); |
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v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
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#endif |
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return v; |
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} |
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|
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static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t v; |
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#ifdef TARGET_WORDS_BIGENDIAN |
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v = cirrus_mmio_readb(opaque, addr) << 24; |
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v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
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v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
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v |= cirrus_mmio_readb(opaque, addr + 3); |
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#else |
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v = cirrus_mmio_readb(opaque, addr); |
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v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
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v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
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v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
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#endif |
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return v; |
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} |
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|
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static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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CirrusVGAState *s = (CirrusVGAState *) opaque; |
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addr &= CIRRUS_PNPMMIO_SIZE - 1; |
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/* ??? Does CLGD5430 have memory-mapped VGA registers ??? */ |
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if (addr >= 0x100) {
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cirrus_mmio_blt_write(s, addr - 0x100, val); |
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} else {
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cirrus_mmio_vga_write(s, addr, val); |
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} |
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} |
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|
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static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN |
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cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
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#else |
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cirrus_mmio_writeb(opaque, addr, val & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
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#endif |
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} |
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|
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static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{
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#ifdef TARGET_WORDS_BIGENDIAN |
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cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
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#else |
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cirrus_mmio_writeb(opaque, addr, val & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
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cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
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#endif |
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} |
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static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
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cirrus_mmio_readb, |
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cirrus_mmio_readw, |
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cirrus_mmio_readl, |
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}; |
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|
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static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
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cirrus_mmio_writeb, |
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cirrus_mmio_writew, |
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cirrus_mmio_writel, |
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}; |
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|
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/* I/O ports */ |
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static uint32_t vga_ioport_read(void *opaque, uint32_t addr) |
| ... | ... | |
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/*************************************** |
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* |
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* memory-mapped I/O access |
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* |
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***************************************/ |
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static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) |
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{
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CirrusVGAState *s = (CirrusVGAState *) opaque; |
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addr &= CIRRUS_PNPMMIO_SIZE - 1; |
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if (addr >= 0x100) {
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return cirrus_mmio_blt_read(s, addr - 0x100); |
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} else {
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return vga_ioport_read(s, addr + 0x3c0); |
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} |
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} |
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static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t v; |
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#ifdef TARGET_WORDS_BIGENDIAN |
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v = cirrus_mmio_readb(opaque, addr) << 8; |
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v |= cirrus_mmio_readb(opaque, addr + 1); |
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#else |
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v = cirrus_mmio_readb(opaque, addr); |
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v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
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#endif |
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return v; |
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} |
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|
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static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
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{
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uint32_t v; |
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#ifdef TARGET_WORDS_BIGENDIAN |
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v = cirrus_mmio_readb(opaque, addr) << 24; |
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v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
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| 2484 |
v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
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v |= cirrus_mmio_readb(opaque, addr + 3); |
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#else |
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| 2487 |
v = cirrus_mmio_readb(opaque, addr); |
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| 2488 |
v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
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| 2489 |
v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
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| 2490 |
v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
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#endif |
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return v; |
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} |
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| 2494 |
|
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| 2495 |
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, |
|
| 2496 |
uint32_t val) |
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{
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CirrusVGAState *s = (CirrusVGAState *) opaque; |
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| 2499 |
|
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| 2500 |
addr &= CIRRUS_PNPMMIO_SIZE - 1; |
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| 2501 |
|
|
| 2502 |
if (addr >= 0x100) {
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| 2503 |
cirrus_mmio_blt_write(s, addr - 0x100, val); |
|
| 2504 |
} else {
|
|
| 2505 |
vga_ioport_write(s, addr + 0x3c0, val); |
|
| 2506 |
} |
|
| 2507 |
} |
|
| 2508 |
|
|
| 2509 |
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
|
| 2510 |
uint32_t val) |
|
| 2511 |
{
|
|
| 2512 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2513 |
cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
|
| 2514 |
cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
|
| 2515 |
#else |
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| 2516 |
cirrus_mmio_writeb(opaque, addr, val & 0xff); |
|
| 2517 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
|
| 2518 |
#endif |
|
| 2519 |
} |
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| 2520 |
|
|
| 2521 |
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
|
| 2522 |
uint32_t val) |
|
| 2523 |
{
|
|
| 2524 |
#ifdef TARGET_WORDS_BIGENDIAN |
|
| 2525 |
cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
|
| 2526 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
|
| 2527 |
cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
|
| 2528 |
cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
|
| 2529 |
#else |
|
| 2530 |
cirrus_mmio_writeb(opaque, addr, val & 0xff); |
|
| 2531 |
cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
|
| 2532 |
cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
|
| 2533 |
cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
|
| 2534 |
#endif |
|
| 2535 |
} |
|
| 2536 |
|
|
| 2537 |
|
|
| 2538 |
static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
|
|
| 2539 |
cirrus_mmio_readb, |
|
| 2540 |
cirrus_mmio_readw, |
|
| 2541 |
cirrus_mmio_readl, |
|
| 2542 |
}; |
|
| 2543 |
|
|
| 2544 |
static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
|
|
| 2545 |
cirrus_mmio_writeb, |
|
| 2546 |
cirrus_mmio_writew, |
|
| 2547 |
cirrus_mmio_writel, |
|
| 2548 |
}; |
|
| 2549 |
|
|
| 2550 |
/*************************************** |
|
| 2551 |
* |
|
| 2573 | 2552 |
* initialize |
| 2574 | 2553 |
* |
| 2575 | 2554 |
***************************************/ |
Also available in: Unified diff