root / target-mips / exec.h @ e37e863f
History | View | Annotate | Download (3.8 kB)
1 | 6af0bf9c | bellard | #if !defined(__QEMU_MIPS_EXEC_H__)
|
---|---|---|---|
2 | 6af0bf9c | bellard | #define __QEMU_MIPS_EXEC_H__
|
3 | 6af0bf9c | bellard | |
4 | 6af0bf9c | bellard | #define DEBUG_OP
|
5 | 6af0bf9c | bellard | |
6 | 6af0bf9c | bellard | #include "mips-defs.h" |
7 | 6af0bf9c | bellard | #include "dyngen-exec.h" |
8 | 6af0bf9c | bellard | |
9 | 6af0bf9c | bellard | register struct CPUMIPSState *env asm(AREG0); |
10 | 6af0bf9c | bellard | |
11 | 6af0bf9c | bellard | #if defined (USE_64BITS_REGS)
|
12 | 6af0bf9c | bellard | typedef int64_t host_int_t;
|
13 | 6af0bf9c | bellard | typedef uint64_t host_uint_t;
|
14 | 6af0bf9c | bellard | #else
|
15 | 6af0bf9c | bellard | typedef int32_t host_int_t;
|
16 | 6af0bf9c | bellard | typedef uint32_t host_uint_t;
|
17 | 6af0bf9c | bellard | #endif
|
18 | 6af0bf9c | bellard | |
19 | 6af0bf9c | bellard | register host_uint_t T0 asm(AREG1); |
20 | 6af0bf9c | bellard | register host_uint_t T1 asm(AREG2); |
21 | 6af0bf9c | bellard | register host_uint_t T2 asm(AREG3); |
22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #if defined (USE_HOST_FLOAT_REGS)
|
24 | 6af0bf9c | bellard | register double FT0 asm(FREG0); |
25 | 6af0bf9c | bellard | register double FT1 asm(FREG1); |
26 | 6af0bf9c | bellard | register double FT2 asm(FREG2); |
27 | 6af0bf9c | bellard | #else
|
28 | 6af0bf9c | bellard | #define FT0 (env->ft0.d)
|
29 | 6af0bf9c | bellard | #define FT1 (env->ft1.d)
|
30 | 6af0bf9c | bellard | #define FT2 (env->ft2.d)
|
31 | 6af0bf9c | bellard | #endif
|
32 | 6af0bf9c | bellard | |
33 | 6af0bf9c | bellard | #if defined (DEBUG_OP)
|
34 | 6af0bf9c | bellard | #define RETURN() __asm__ __volatile__("nop"); |
35 | 6af0bf9c | bellard | #else
|
36 | 6af0bf9c | bellard | #define RETURN() __asm__ __volatile__(""); |
37 | 6af0bf9c | bellard | #endif
|
38 | 6af0bf9c | bellard | |
39 | 6af0bf9c | bellard | #include "cpu.h" |
40 | 6af0bf9c | bellard | #include "exec-all.h" |
41 | 6af0bf9c | bellard | |
42 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
|
43 | 6af0bf9c | bellard | |
44 | 6af0bf9c | bellard | #define ldul_user ldl_user
|
45 | 6af0bf9c | bellard | #define ldul_kernel ldl_kernel
|
46 | 6af0bf9c | bellard | |
47 | 6af0bf9c | bellard | #define ACCESS_TYPE 0 |
48 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
|
49 | 6af0bf9c | bellard | #define DATA_SIZE 1 |
50 | 6af0bf9c | bellard | #include "softmmu_header.h" |
51 | 6af0bf9c | bellard | |
52 | 6af0bf9c | bellard | #define DATA_SIZE 2 |
53 | 6af0bf9c | bellard | #include "softmmu_header.h" |
54 | 6af0bf9c | bellard | |
55 | 6af0bf9c | bellard | #define DATA_SIZE 4 |
56 | 6af0bf9c | bellard | #include "softmmu_header.h" |
57 | 6af0bf9c | bellard | |
58 | 6af0bf9c | bellard | #define DATA_SIZE 8 |
59 | 6af0bf9c | bellard | #include "softmmu_header.h" |
60 | 6af0bf9c | bellard | #undef ACCESS_TYPE
|
61 | 6af0bf9c | bellard | #undef MEMSUFFIX
|
62 | 6af0bf9c | bellard | |
63 | 6af0bf9c | bellard | #define ACCESS_TYPE 1 |
64 | 6af0bf9c | bellard | #define MEMSUFFIX _user
|
65 | 6af0bf9c | bellard | #define DATA_SIZE 1 |
66 | 6af0bf9c | bellard | #include "softmmu_header.h" |
67 | 6af0bf9c | bellard | |
68 | 6af0bf9c | bellard | #define DATA_SIZE 2 |
69 | 6af0bf9c | bellard | #include "softmmu_header.h" |
70 | 6af0bf9c | bellard | |
71 | 6af0bf9c | bellard | #define DATA_SIZE 4 |
72 | 6af0bf9c | bellard | #include "softmmu_header.h" |
73 | 6af0bf9c | bellard | |
74 | 6af0bf9c | bellard | #define DATA_SIZE 8 |
75 | 6af0bf9c | bellard | #include "softmmu_header.h" |
76 | 6af0bf9c | bellard | #undef ACCESS_TYPE
|
77 | 6af0bf9c | bellard | #undef MEMSUFFIX
|
78 | 6af0bf9c | bellard | |
79 | 6af0bf9c | bellard | /* these access are slower, they must be as rare as possible */
|
80 | 6af0bf9c | bellard | #define ACCESS_TYPE 2 |
81 | 6af0bf9c | bellard | #define MEMSUFFIX _data
|
82 | 6af0bf9c | bellard | #define DATA_SIZE 1 |
83 | 6af0bf9c | bellard | #include "softmmu_header.h" |
84 | 6af0bf9c | bellard | |
85 | 6af0bf9c | bellard | #define DATA_SIZE 2 |
86 | 6af0bf9c | bellard | #include "softmmu_header.h" |
87 | 6af0bf9c | bellard | |
88 | 6af0bf9c | bellard | #define DATA_SIZE 4 |
89 | 6af0bf9c | bellard | #include "softmmu_header.h" |
90 | 6af0bf9c | bellard | |
91 | 6af0bf9c | bellard | #define DATA_SIZE 8 |
92 | 6af0bf9c | bellard | #include "softmmu_header.h" |
93 | 6af0bf9c | bellard | #undef ACCESS_TYPE
|
94 | 6af0bf9c | bellard | #undef MEMSUFFIX
|
95 | 6af0bf9c | bellard | |
96 | 6af0bf9c | bellard | #define ldub(p) ldub_data(p)
|
97 | 6af0bf9c | bellard | #define ldsb(p) ldsb_data(p)
|
98 | 6af0bf9c | bellard | #define lduw(p) lduw_data(p)
|
99 | 6af0bf9c | bellard | #define ldsw(p) ldsw_data(p)
|
100 | 6af0bf9c | bellard | #define ldl(p) ldl_data(p)
|
101 | 6af0bf9c | bellard | #define ldq(p) ldq_data(p)
|
102 | 6af0bf9c | bellard | |
103 | 6af0bf9c | bellard | #define stb(p, v) stb_data(p, v)
|
104 | 6af0bf9c | bellard | #define stw(p, v) stw_data(p, v)
|
105 | 6af0bf9c | bellard | #define stl(p, v) stl_data(p, v)
|
106 | 6af0bf9c | bellard | #define stq(p, v) stq_data(p, v)
|
107 | 6af0bf9c | bellard | |
108 | 6af0bf9c | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
109 | 6af0bf9c | bellard | |
110 | 6af0bf9c | bellard | static inline void env_to_regs(void) |
111 | 6af0bf9c | bellard | { |
112 | 6af0bf9c | bellard | } |
113 | 6af0bf9c | bellard | |
114 | 6af0bf9c | bellard | static inline void regs_to_env(void) |
115 | 6af0bf9c | bellard | { |
116 | 6af0bf9c | bellard | } |
117 | 6af0bf9c | bellard | |
118 | 6af0bf9c | bellard | #if (HOST_LONG_BITS == 32) |
119 | 6af0bf9c | bellard | void do_mult (void); |
120 | 6af0bf9c | bellard | void do_multu (void); |
121 | 6af0bf9c | bellard | void do_madd (void); |
122 | 6af0bf9c | bellard | void do_maddu (void); |
123 | 6af0bf9c | bellard | void do_msub (void); |
124 | 6af0bf9c | bellard | void do_msubu (void); |
125 | 6af0bf9c | bellard | #endif
|
126 | 6af0bf9c | bellard | __attribute__ (( regparm(2) ))
|
127 | 6af0bf9c | bellard | void do_mfc0(int reg, int sel); |
128 | 6af0bf9c | bellard | __attribute__ (( regparm(2) ))
|
129 | 6af0bf9c | bellard | void do_mtc0(int reg, int sel); |
130 | 6af0bf9c | bellard | void do_tlbwi (void); |
131 | 6af0bf9c | bellard | void do_tlbwr (void); |
132 | 6af0bf9c | bellard | void do_tlbp (void); |
133 | 6af0bf9c | bellard | void do_tlbr (void); |
134 | 6af0bf9c | bellard | void do_lwl_raw (void); |
135 | 6af0bf9c | bellard | void do_lwr_raw (void); |
136 | 6af0bf9c | bellard | void do_swl_raw (void); |
137 | 6af0bf9c | bellard | void do_swr_raw (void); |
138 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
|
139 | 6af0bf9c | bellard | void do_lwl_user (void); |
140 | 6af0bf9c | bellard | void do_lwl_kernel (void); |
141 | 6af0bf9c | bellard | void do_lwr_user (void); |
142 | 6af0bf9c | bellard | void do_lwr_kernel (void); |
143 | 6af0bf9c | bellard | void do_swl_user (void); |
144 | 6af0bf9c | bellard | void do_swl_kernel (void); |
145 | 6af0bf9c | bellard | void do_swr_user (void); |
146 | 6af0bf9c | bellard | void do_swr_kernel (void); |
147 | 6af0bf9c | bellard | #endif
|
148 | 6af0bf9c | bellard | __attribute__ (( regparm(1) ))
|
149 | 6af0bf9c | bellard | void do_pmon (int function); |
150 | 6af0bf9c | bellard | |
151 | 6af0bf9c | bellard | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
152 | 6af0bf9c | bellard | int is_user, int is_softmmu); |
153 | 6af0bf9c | bellard | void do_interrupt (CPUState *env);
|
154 | 6af0bf9c | bellard | |
155 | 6af0bf9c | bellard | void cpu_loop_exit(void); |
156 | 6af0bf9c | bellard | __attribute__ (( regparm(2) ))
|
157 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code); |
158 | 6af0bf9c | bellard | __attribute__ (( regparm(1) ))
|
159 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception);
|
160 | 6af0bf9c | bellard | |
161 | 6af0bf9c | bellard | void cpu_dump_state(CPUState *env, FILE *f,
|
162 | 6af0bf9c | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
163 | 6af0bf9c | bellard | int flags);
|
164 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void); |
165 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env); |
166 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env); |
167 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value);
|
168 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value);
|
169 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env);
|
170 | 6af0bf9c | bellard | |
171 | 6af0bf9c | bellard | #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |