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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "monitor.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "msix.h" |
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|
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...) printf(format, __VA_ARGS__)
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0) |
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#endif
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struct PCIBus {
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BusState qbus; |
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int bus_num;
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int devfn_min;
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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uint32_t config_reg; /* XXX: suppress */
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev; |
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PCIBus *next; |
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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}; |
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|
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
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|
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static struct BusInfo pci_bus_info = { |
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print, |
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.props = (Property[]) { |
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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|
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
69 |
|
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target_phys_addr_t pci_mem_base; |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static PCIBus *first_bus;
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|
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static const VMStateDescription vmstate_pcibus = { |
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_EQUAL(nirq, PCIBus), |
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VMSTATE_INT32_VARRAY(irq_count, PCIBus, nirq), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
86 |
|
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static void pci_bus_reset(void *opaque) |
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{ |
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PCIBus *bus = opaque; |
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int i;
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < 256; i++) { |
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if (bus->devices[i])
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memset(bus->devices[i]->irq_state, 0,
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sizeof(bus->devices[i]->irq_state));
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} |
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} |
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|
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, int devfn_min) |
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{ |
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static int nbus = 0; |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
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bus->devfn_min = devfn_min; |
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bus->next = first_bus; |
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first_bus = bus; |
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vmstate_register(nbus++, &vmstate_pcibus, bus); |
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qemu_register_reset(pci_bus_reset, bus); |
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} |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) |
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(*bus));
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bus->qbus.qdev_allocated = 1;
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pci_bus_new_inplace(bus, parent, name, devfn_min); |
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return bus;
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} |
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq) |
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{ |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = irq_opaque; |
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bus->nirq = nirq; |
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
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} |
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|
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque, int devfn_min, int nirq) |
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{ |
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PCIBus *bus; |
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bus = pci_bus_new(parent, name, devfn_min); |
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pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
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return bus;
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} |
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static void pci_register_secondary_bus(PCIBus *bus, |
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PCIDevice *dev, |
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pci_map_irq_fn map_irq, |
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const char *name) |
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{ |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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bus->next = dev->bus->next; |
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dev->bus->next = bus; |
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} |
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int pci_bus_num(PCIBus *s)
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{ |
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return s->bus_num;
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} |
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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, config); |
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uint8_t config[size]; |
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int i;
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qemu_get_buffer(f, config, size); |
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for (i = 0; i < size; ++i) |
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
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return -EINVAL;
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memcpy(s->config, config, size); |
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pci_update_mappings(s); |
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return 0; |
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} |
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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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const uint8_t *v = pv;
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qemu_put_buffer(f, v, size); |
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} |
186 |
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static VMStateInfo vmstate_info_pci_config = {
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.name = "pci config",
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.get = get_pci_config_device, |
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.put = put_pci_config_device, |
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}; |
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const VMStateDescription vmstate_pci_device = {
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.name = "PCIDevice",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_LE(version_id, PCIDevice), |
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VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
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typeof_field(PCIDevice,config)), |
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VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, 4, 2), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{ |
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vmstate_save_state(f, &vmstate_pci_device, s); |
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} |
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{ |
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return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
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} |
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
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{ |
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uint16_t *id; |
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id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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id[1] = cpu_to_le16(pci_default_sub_device_id);
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return 0; |
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} |
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/*
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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*/
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
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{ |
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const char *p; |
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char *e;
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unsigned long val; |
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unsigned long dom = 0, bus = 0; |
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unsigned slot = 0; |
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p = addr; |
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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if (*e == ':') { |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
248 |
if (*e == ':') { |
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dom = bus; |
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bus = val; |
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1; |
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} |
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} |
257 |
|
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if (dom > 0xffff || bus > 0xff || val > 0x1f) |
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return -1; |
260 |
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slot = val; |
262 |
|
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if (*e)
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return -1; |
265 |
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/* Note: QEMU doesn't implement domains other than 0 */
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if (dom != 0 || pci_find_bus(bus) == NULL) |
268 |
return -1; |
269 |
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*domp = dom; |
271 |
*busp = bus; |
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*slotp = slot; |
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return 0; |
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} |
275 |
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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
277 |
unsigned *slotp)
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{ |
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/* strip legacy tag */
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if (!strncmp(addr, "pci_addr=", 9)) { |
281 |
addr += 9;
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} |
283 |
if (pci_parse_devaddr(addr, domp, busp, slotp)) {
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monitor_printf(mon, "Invalid pci address\n");
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return -1; |
286 |
} |
287 |
return 0; |
288 |
} |
289 |
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static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
291 |
{ |
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int dom, bus;
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unsigned slot;
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294 |
|
295 |
if (!devaddr) {
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*devfnp = -1;
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return pci_find_bus(0); |
298 |
} |
299 |
|
300 |
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
301 |
return NULL; |
302 |
} |
303 |
|
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*devfnp = slot << 3;
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return pci_find_bus(bus);
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} |
307 |
|
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static void pci_init_cmask(PCIDevice *dev) |
309 |
{ |
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pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
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pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
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312 |
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
313 |
dev->cmask[PCI_REVISION_ID] = 0xff;
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314 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
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315 |
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
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316 |
dev->cmask[PCI_HEADER_TYPE] = 0xff;
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317 |
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
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318 |
} |
319 |
|
320 |
static void pci_init_wmask(PCIDevice *dev) |
321 |
{ |
322 |
int i;
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dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
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324 |
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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325 |
dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
326 |
| PCI_COMMAND_MASTER; |
327 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
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328 |
dev->wmask[i] = 0xff;
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329 |
} |
330 |
|
331 |
/* -1 for devfn means auto assign */
|
332 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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333 |
const char *name, int devfn, |
334 |
PCIConfigReadFunc *config_read, |
335 |
PCIConfigWriteFunc *config_write) |
336 |
{ |
337 |
if (devfn < 0) { |
338 |
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
339 |
if (!bus->devices[devfn])
|
340 |
goto found;
|
341 |
} |
342 |
return NULL; |
343 |
found: ;
|
344 |
} else if (bus->devices[devfn]) { |
345 |
return NULL; |
346 |
} |
347 |
pci_dev->bus = bus; |
348 |
pci_dev->devfn = devfn; |
349 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
350 |
memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
351 |
pci_set_default_subsystem_id(pci_dev); |
352 |
pci_init_cmask(pci_dev); |
353 |
pci_init_wmask(pci_dev); |
354 |
|
355 |
if (!config_read)
|
356 |
config_read = pci_default_read_config; |
357 |
if (!config_write)
|
358 |
config_write = pci_default_write_config; |
359 |
pci_dev->config_read = config_read; |
360 |
pci_dev->config_write = config_write; |
361 |
bus->devices[devfn] = pci_dev; |
362 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
|
363 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
364 |
return pci_dev;
|
365 |
} |
366 |
|
367 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
368 |
int instance_size, int devfn, |
369 |
PCIConfigReadFunc *config_read, |
370 |
PCIConfigWriteFunc *config_write) |
371 |
{ |
372 |
PCIDevice *pci_dev; |
373 |
|
374 |
pci_dev = qemu_mallocz(instance_size); |
375 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
376 |
config_read, config_write); |
377 |
return pci_dev;
|
378 |
} |
379 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
380 |
{ |
381 |
return addr + pci_mem_base;
|
382 |
} |
383 |
|
384 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
385 |
{ |
386 |
PCIIORegion *r; |
387 |
int i;
|
388 |
|
389 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
390 |
r = &pci_dev->io_regions[i]; |
391 |
if (!r->size || r->addr == -1) |
392 |
continue;
|
393 |
if (r->type == PCI_ADDRESS_SPACE_IO) {
|
394 |
isa_unassign_ioport(r->addr, r->size); |
395 |
} else {
|
396 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
397 |
r->size, |
398 |
IO_MEM_UNASSIGNED); |
399 |
} |
400 |
} |
401 |
} |
402 |
|
403 |
static int pci_unregister_device(DeviceState *dev) |
404 |
{ |
405 |
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
406 |
PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
407 |
int ret = 0; |
408 |
|
409 |
if (info->exit)
|
410 |
ret = info->exit(pci_dev); |
411 |
if (ret)
|
412 |
return ret;
|
413 |
|
414 |
msix_uninit(pci_dev); |
415 |
pci_unregister_io_regions(pci_dev); |
416 |
|
417 |
qemu_free_irqs(pci_dev->irq); |
418 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
419 |
return 0; |
420 |
} |
421 |
|
422 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
423 |
uint32_t size, int type,
|
424 |
PCIMapIORegionFunc *map_func) |
425 |
{ |
426 |
PCIIORegion *r; |
427 |
uint32_t addr; |
428 |
uint32_t wmask; |
429 |
|
430 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
431 |
return;
|
432 |
|
433 |
if (size & (size-1)) { |
434 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
435 |
"type=0x%x, size=0x%x\n", type, size);
|
436 |
exit(1);
|
437 |
} |
438 |
|
439 |
r = &pci_dev->io_regions[region_num]; |
440 |
r->addr = -1;
|
441 |
r->size = size; |
442 |
r->type = type; |
443 |
r->map_func = map_func; |
444 |
|
445 |
wmask = ~(size - 1);
|
446 |
if (region_num == PCI_ROM_SLOT) {
|
447 |
addr = 0x30;
|
448 |
/* ROM enable bit is writeable */
|
449 |
wmask |= 1;
|
450 |
} else {
|
451 |
addr = 0x10 + region_num * 4; |
452 |
} |
453 |
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
454 |
*(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask); |
455 |
*(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
|
456 |
} |
457 |
|
458 |
static void pci_update_mappings(PCIDevice *d) |
459 |
{ |
460 |
PCIIORegion *r; |
461 |
int cmd, i;
|
462 |
uint32_t last_addr, new_addr, config_ofs; |
463 |
|
464 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
465 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
466 |
r = &d->io_regions[i]; |
467 |
if (i == PCI_ROM_SLOT) {
|
468 |
config_ofs = 0x30;
|
469 |
} else {
|
470 |
config_ofs = 0x10 + i * 4; |
471 |
} |
472 |
if (r->size != 0) { |
473 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
474 |
if (cmd & PCI_COMMAND_IO) {
|
475 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
476 |
config_ofs)); |
477 |
new_addr = new_addr & ~(r->size - 1);
|
478 |
last_addr = new_addr + r->size - 1;
|
479 |
/* NOTE: we have only 64K ioports on PC */
|
480 |
if (last_addr <= new_addr || new_addr == 0 || |
481 |
last_addr >= 0x10000) {
|
482 |
new_addr = -1;
|
483 |
} |
484 |
} else {
|
485 |
new_addr = -1;
|
486 |
} |
487 |
} else {
|
488 |
if (cmd & PCI_COMMAND_MEMORY) {
|
489 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
490 |
config_ofs)); |
491 |
/* the ROM slot has a specific enable bit */
|
492 |
if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
493 |
goto no_mem_map;
|
494 |
new_addr = new_addr & ~(r->size - 1);
|
495 |
last_addr = new_addr + r->size - 1;
|
496 |
/* NOTE: we do not support wrapping */
|
497 |
/* XXX: as we cannot support really dynamic
|
498 |
mappings, we handle specific values as invalid
|
499 |
mappings. */
|
500 |
if (last_addr <= new_addr || new_addr == 0 || |
501 |
last_addr == -1) {
|
502 |
new_addr = -1;
|
503 |
} |
504 |
} else {
|
505 |
no_mem_map:
|
506 |
new_addr = -1;
|
507 |
} |
508 |
} |
509 |
/* now do the real mapping */
|
510 |
if (new_addr != r->addr) {
|
511 |
if (r->addr != -1) { |
512 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
513 |
int class;
|
514 |
/* NOTE: specific hack for IDE in PC case:
|
515 |
only one byte must be mapped. */
|
516 |
class = d->config[0x0a] | (d->config[0x0b] << 8); |
517 |
if (class == 0x0101 && r->size == 4) { |
518 |
isa_unassign_ioport(r->addr + 2, 1); |
519 |
} else {
|
520 |
isa_unassign_ioport(r->addr, r->size); |
521 |
} |
522 |
} else {
|
523 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
524 |
r->size, |
525 |
IO_MEM_UNASSIGNED); |
526 |
qemu_unregister_coalesced_mmio(r->addr, r->size); |
527 |
} |
528 |
} |
529 |
r->addr = new_addr; |
530 |
if (r->addr != -1) { |
531 |
r->map_func(d, i, r->addr, r->size, r->type); |
532 |
} |
533 |
} |
534 |
} |
535 |
} |
536 |
} |
537 |
|
538 |
uint32_t pci_default_read_config(PCIDevice *d, |
539 |
uint32_t address, int len)
|
540 |
{ |
541 |
uint32_t val; |
542 |
|
543 |
switch(len) {
|
544 |
default:
|
545 |
case 4: |
546 |
if (address <= 0xfc) { |
547 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
548 |
break;
|
549 |
} |
550 |
/* fall through */
|
551 |
case 2: |
552 |
if (address <= 0xfe) { |
553 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
554 |
break;
|
555 |
} |
556 |
/* fall through */
|
557 |
case 1: |
558 |
val = d->config[address]; |
559 |
break;
|
560 |
} |
561 |
return val;
|
562 |
} |
563 |
|
564 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
565 |
{ |
566 |
uint8_t orig[PCI_CONFIG_SPACE_SIZE]; |
567 |
int i;
|
568 |
|
569 |
/* not efficient, but simple */
|
570 |
memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE); |
571 |
for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) { |
572 |
uint8_t wmask = d->wmask[addr]; |
573 |
d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask); |
574 |
} |
575 |
if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24) |
576 |
|| ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND]) |
577 |
& (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))) |
578 |
pci_update_mappings(d); |
579 |
} |
580 |
|
581 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
582 |
{ |
583 |
PCIBus *s = opaque; |
584 |
PCIDevice *pci_dev; |
585 |
int config_addr, bus_num;
|
586 |
|
587 |
#if 0
|
588 |
PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
|
589 |
addr, val, len);
|
590 |
#endif
|
591 |
bus_num = (addr >> 16) & 0xff; |
592 |
while (s && s->bus_num != bus_num)
|
593 |
s = s->next; |
594 |
if (!s)
|
595 |
return;
|
596 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
597 |
if (!pci_dev)
|
598 |
return;
|
599 |
config_addr = addr & 0xff;
|
600 |
PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
601 |
pci_dev->name, config_addr, val, len); |
602 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
603 |
} |
604 |
|
605 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
606 |
{ |
607 |
PCIBus *s = opaque; |
608 |
PCIDevice *pci_dev; |
609 |
int config_addr, bus_num;
|
610 |
uint32_t val; |
611 |
|
612 |
bus_num = (addr >> 16) & 0xff; |
613 |
while (s && s->bus_num != bus_num)
|
614 |
s= s->next; |
615 |
if (!s)
|
616 |
goto fail;
|
617 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
618 |
if (!pci_dev) {
|
619 |
fail:
|
620 |
switch(len) {
|
621 |
case 1: |
622 |
val = 0xff;
|
623 |
break;
|
624 |
case 2: |
625 |
val = 0xffff;
|
626 |
break;
|
627 |
default:
|
628 |
case 4: |
629 |
val = 0xffffffff;
|
630 |
break;
|
631 |
} |
632 |
goto the_end;
|
633 |
} |
634 |
config_addr = addr & 0xff;
|
635 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
636 |
PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
637 |
pci_dev->name, config_addr, val, len); |
638 |
the_end:
|
639 |
#if 0
|
640 |
PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
|
641 |
addr, val, len);
|
642 |
#endif
|
643 |
return val;
|
644 |
} |
645 |
|
646 |
/***********************************************************/
|
647 |
/* generic PCI irq support */
|
648 |
|
649 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
650 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
651 |
{ |
652 |
PCIDevice *pci_dev = opaque; |
653 |
PCIBus *bus; |
654 |
int change;
|
655 |
|
656 |
change = level - pci_dev->irq_state[irq_num]; |
657 |
if (!change)
|
658 |
return;
|
659 |
|
660 |
pci_dev->irq_state[irq_num] = level; |
661 |
for (;;) {
|
662 |
bus = pci_dev->bus; |
663 |
irq_num = bus->map_irq(pci_dev, irq_num); |
664 |
if (bus->set_irq)
|
665 |
break;
|
666 |
pci_dev = bus->parent_dev; |
667 |
} |
668 |
bus->irq_count[irq_num] += change; |
669 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
670 |
} |
671 |
|
672 |
/***********************************************************/
|
673 |
/* monitor info on PCI */
|
674 |
|
675 |
typedef struct { |
676 |
uint16_t class; |
677 |
const char *desc; |
678 |
} pci_class_desc; |
679 |
|
680 |
static const pci_class_desc pci_class_descriptions[] = |
681 |
{ |
682 |
{ 0x0100, "SCSI controller"}, |
683 |
{ 0x0101, "IDE controller"}, |
684 |
{ 0x0102, "Floppy controller"}, |
685 |
{ 0x0103, "IPI controller"}, |
686 |
{ 0x0104, "RAID controller"}, |
687 |
{ 0x0106, "SATA controller"}, |
688 |
{ 0x0107, "SAS controller"}, |
689 |
{ 0x0180, "Storage controller"}, |
690 |
{ 0x0200, "Ethernet controller"}, |
691 |
{ 0x0201, "Token Ring controller"}, |
692 |
{ 0x0202, "FDDI controller"}, |
693 |
{ 0x0203, "ATM controller"}, |
694 |
{ 0x0280, "Network controller"}, |
695 |
{ 0x0300, "VGA controller"}, |
696 |
{ 0x0301, "XGA controller"}, |
697 |
{ 0x0302, "3D controller"}, |
698 |
{ 0x0380, "Display controller"}, |
699 |
{ 0x0400, "Video controller"}, |
700 |
{ 0x0401, "Audio controller"}, |
701 |
{ 0x0402, "Phone"}, |
702 |
{ 0x0480, "Multimedia controller"}, |
703 |
{ 0x0500, "RAM controller"}, |
704 |
{ 0x0501, "Flash controller"}, |
705 |
{ 0x0580, "Memory controller"}, |
706 |
{ 0x0600, "Host bridge"}, |
707 |
{ 0x0601, "ISA bridge"}, |
708 |
{ 0x0602, "EISA bridge"}, |
709 |
{ 0x0603, "MC bridge"}, |
710 |
{ 0x0604, "PCI bridge"}, |
711 |
{ 0x0605, "PCMCIA bridge"}, |
712 |
{ 0x0606, "NUBUS bridge"}, |
713 |
{ 0x0607, "CARDBUS bridge"}, |
714 |
{ 0x0608, "RACEWAY bridge"}, |
715 |
{ 0x0680, "Bridge"}, |
716 |
{ 0x0c03, "USB controller"}, |
717 |
{ 0, NULL} |
718 |
}; |
719 |
|
720 |
static void pci_info_device(PCIDevice *d) |
721 |
{ |
722 |
Monitor *mon = cur_mon; |
723 |
int i, class;
|
724 |
PCIIORegion *r; |
725 |
const pci_class_desc *desc;
|
726 |
|
727 |
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
728 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
729 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
730 |
monitor_printf(mon, " ");
|
731 |
desc = pci_class_descriptions; |
732 |
while (desc->desc && class != desc->class)
|
733 |
desc++; |
734 |
if (desc->desc) {
|
735 |
monitor_printf(mon, "%s", desc->desc);
|
736 |
} else {
|
737 |
monitor_printf(mon, "Class %04x", class);
|
738 |
} |
739 |
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
740 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
741 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
742 |
|
743 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
744 |
monitor_printf(mon, " IRQ %d.\n",
|
745 |
d->config[PCI_INTERRUPT_LINE]); |
746 |
} |
747 |
if (class == 0x0604) { |
748 |
monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
749 |
} |
750 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
751 |
r = &d->io_regions[i]; |
752 |
if (r->size != 0) { |
753 |
monitor_printf(mon, " BAR%d: ", i);
|
754 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
755 |
monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
|
756 |
r->addr, r->addr + r->size - 1);
|
757 |
} else {
|
758 |
monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
|
759 |
r->addr, r->addr + r->size - 1);
|
760 |
} |
761 |
} |
762 |
} |
763 |
monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
764 |
if (class == 0x0604 && d->config[0x19] != 0) { |
765 |
pci_for_each_device(d->config[0x19], pci_info_device);
|
766 |
} |
767 |
} |
768 |
|
769 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
770 |
{ |
771 |
PCIBus *bus = first_bus; |
772 |
PCIDevice *d; |
773 |
int devfn;
|
774 |
|
775 |
while (bus && bus->bus_num != bus_num)
|
776 |
bus = bus->next; |
777 |
if (bus) {
|
778 |
for(devfn = 0; devfn < 256; devfn++) { |
779 |
d = bus->devices[devfn]; |
780 |
if (d)
|
781 |
fn(d); |
782 |
} |
783 |
} |
784 |
} |
785 |
|
786 |
void pci_info(Monitor *mon)
|
787 |
{ |
788 |
pci_for_each_device(0, pci_info_device);
|
789 |
} |
790 |
|
791 |
PCIDevice *pci_create(const char *name, const char *devaddr) |
792 |
{ |
793 |
PCIBus *bus; |
794 |
int devfn;
|
795 |
DeviceState *dev; |
796 |
|
797 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
798 |
if (!bus) {
|
799 |
fprintf(stderr, "Invalid PCI device address %s for device %s\n",
|
800 |
devaddr, name); |
801 |
exit(1);
|
802 |
} |
803 |
|
804 |
dev = qdev_create(&bus->qbus, name); |
805 |
qdev_prop_set_uint32(dev, "addr", devfn);
|
806 |
return (PCIDevice *)dev;
|
807 |
} |
808 |
|
809 |
static const char * const pci_nic_models[] = { |
810 |
"ne2k_pci",
|
811 |
"i82551",
|
812 |
"i82557b",
|
813 |
"i82559er",
|
814 |
"rtl8139",
|
815 |
"e1000",
|
816 |
"pcnet",
|
817 |
"virtio",
|
818 |
NULL
|
819 |
}; |
820 |
|
821 |
static const char * const pci_nic_names[] = { |
822 |
"ne2k_pci",
|
823 |
"i82551",
|
824 |
"i82557b",
|
825 |
"i82559er",
|
826 |
"rtl8139",
|
827 |
"e1000",
|
828 |
"pcnet",
|
829 |
"virtio-net-pci",
|
830 |
NULL
|
831 |
}; |
832 |
|
833 |
int pci_nic_supported(const char *model) |
834 |
{ |
835 |
int i;
|
836 |
|
837 |
for (i = 0; pci_nic_names[i]; i++) |
838 |
if (strcmp(model, pci_nic_names[i]) == 0) |
839 |
return 1; |
840 |
|
841 |
return 0; |
842 |
} |
843 |
|
844 |
/* Initialize a PCI NIC. */
|
845 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
846 |
const char *default_devaddr) |
847 |
{ |
848 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
849 |
PCIDevice *pci_dev; |
850 |
DeviceState *dev; |
851 |
int i;
|
852 |
|
853 |
qemu_check_nic_model_list(nd, pci_nic_models, default_model); |
854 |
|
855 |
for (i = 0; pci_nic_models[i]; i++) { |
856 |
if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
857 |
pci_dev = pci_create(pci_nic_names[i], devaddr); |
858 |
dev = &pci_dev->qdev; |
859 |
if (nd->id)
|
860 |
dev->id = qemu_strdup(nd->id); |
861 |
dev->nd = nd; |
862 |
qdev_init(dev); |
863 |
nd->private = dev; |
864 |
return pci_dev;
|
865 |
} |
866 |
} |
867 |
|
868 |
return NULL; |
869 |
} |
870 |
|
871 |
typedef struct { |
872 |
PCIDevice dev; |
873 |
PCIBus bus; |
874 |
uint32_t vid; |
875 |
uint32_t did; |
876 |
} PCIBridge; |
877 |
|
878 |
static void pci_bridge_write_config(PCIDevice *d, |
879 |
uint32_t address, uint32_t val, int len)
|
880 |
{ |
881 |
PCIBridge *s = (PCIBridge *)d; |
882 |
|
883 |
pci_default_write_config(d, address, val, len); |
884 |
s->bus.bus_num = d->config[PCI_SECONDARY_BUS]; |
885 |
} |
886 |
|
887 |
PCIBus *pci_find_bus(int bus_num)
|
888 |
{ |
889 |
PCIBus *bus = first_bus; |
890 |
|
891 |
while (bus && bus->bus_num != bus_num)
|
892 |
bus = bus->next; |
893 |
|
894 |
return bus;
|
895 |
} |
896 |
|
897 |
PCIDevice *pci_find_device(int bus_num, int slot, int function) |
898 |
{ |
899 |
PCIBus *bus = pci_find_bus(bus_num); |
900 |
|
901 |
if (!bus)
|
902 |
return NULL; |
903 |
|
904 |
return bus->devices[PCI_DEVFN(slot, function)];
|
905 |
} |
906 |
|
907 |
static int pci_bridge_initfn(PCIDevice *dev) |
908 |
{ |
909 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
910 |
|
911 |
pci_config_set_vendor_id(s->dev.config, s->vid); |
912 |
pci_config_set_device_id(s->dev.config, s->did); |
913 |
|
914 |
s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
915 |
s->dev.config[0x05] = 0x00; |
916 |
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
917 |
s->dev.config[0x07] = 0x00; // status = fast devsel |
918 |
s->dev.config[0x08] = 0x00; // revision |
919 |
s->dev.config[0x09] = 0x00; // programming i/f |
920 |
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
921 |
s->dev.config[0x0D] = 0x10; // latency_timer |
922 |
s->dev.config[PCI_HEADER_TYPE] = |
923 |
PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
|
924 |
s->dev.config[0x1E] = 0xa0; // secondary status |
925 |
return 0; |
926 |
} |
927 |
|
928 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
929 |
pci_map_irq_fn map_irq, const char *name) |
930 |
{ |
931 |
PCIDevice *dev; |
932 |
PCIBridge *s; |
933 |
|
934 |
dev = pci_create_noinit(bus, devfn, "pci-bridge");
|
935 |
qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
|
936 |
qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
|
937 |
qdev_init(&dev->qdev); |
938 |
|
939 |
s = DO_UPCAST(PCIBridge, dev, dev); |
940 |
pci_register_secondary_bus(&s->bus, &s->dev, map_irq, name); |
941 |
return &s->bus;
|
942 |
} |
943 |
|
944 |
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
945 |
{ |
946 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
947 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
948 |
PCIBus *bus; |
949 |
int devfn;
|
950 |
|
951 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
952 |
devfn = pci_dev->devfn; |
953 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
954 |
info->config_read, info->config_write); |
955 |
assert(pci_dev); |
956 |
return info->init(pci_dev);
|
957 |
} |
958 |
|
959 |
void pci_qdev_register(PCIDeviceInfo *info)
|
960 |
{ |
961 |
info->qdev.init = pci_qdev_init; |
962 |
info->qdev.exit = pci_unregister_device; |
963 |
info->qdev.bus_info = &pci_bus_info; |
964 |
qdev_register(&info->qdev); |
965 |
} |
966 |
|
967 |
void pci_qdev_register_many(PCIDeviceInfo *info)
|
968 |
{ |
969 |
while (info->qdev.name) {
|
970 |
pci_qdev_register(info); |
971 |
info++; |
972 |
} |
973 |
} |
974 |
|
975 |
PCIDevice *pci_create_noinit(PCIBus *bus, int devfn, const char *name) |
976 |
{ |
977 |
DeviceState *dev; |
978 |
|
979 |
dev = qdev_create(&bus->qbus, name); |
980 |
qdev_prop_set_uint32(dev, "addr", devfn);
|
981 |
return DO_UPCAST(PCIDevice, qdev, dev);
|
982 |
} |
983 |
|
984 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
985 |
{ |
986 |
PCIDevice *dev = pci_create_noinit(bus, devfn, name); |
987 |
qdev_init(&dev->qdev); |
988 |
return dev;
|
989 |
} |
990 |
|
991 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
992 |
{ |
993 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
994 |
int i;
|
995 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
|
996 |
if (pdev->used[i])
|
997 |
offset = i + 1;
|
998 |
else if (i - offset + 1 == size) |
999 |
return offset;
|
1000 |
return 0; |
1001 |
} |
1002 |
|
1003 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
1004 |
uint8_t *prev_p) |
1005 |
{ |
1006 |
uint8_t next, prev; |
1007 |
|
1008 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
1009 |
return 0; |
1010 |
|
1011 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1012 |
prev = next + PCI_CAP_LIST_NEXT) |
1013 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
1014 |
break;
|
1015 |
|
1016 |
if (prev_p)
|
1017 |
*prev_p = prev; |
1018 |
return next;
|
1019 |
} |
1020 |
|
1021 |
/* Reserve space and add capability to the linked list in pci config space */
|
1022 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1023 |
{ |
1024 |
uint8_t offset = pci_find_space(pdev, size); |
1025 |
uint8_t *config = pdev->config + offset; |
1026 |
if (!offset)
|
1027 |
return -ENOSPC;
|
1028 |
config[PCI_CAP_LIST_ID] = cap_id; |
1029 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
1030 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
1031 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
1032 |
memset(pdev->used + offset, 0xFF, size);
|
1033 |
/* Make capability read-only by default */
|
1034 |
memset(pdev->wmask + offset, 0, size);
|
1035 |
/* Check capability by default */
|
1036 |
memset(pdev->cmask + offset, 0xFF, size);
|
1037 |
return offset;
|
1038 |
} |
1039 |
|
1040 |
/* Unlink capability from the pci config space. */
|
1041 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1042 |
{ |
1043 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
1044 |
if (!offset)
|
1045 |
return;
|
1046 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
1047 |
/* Make capability writeable again */
|
1048 |
memset(pdev->wmask + offset, 0xff, size);
|
1049 |
/* Clear cmask as device-specific registers can't be checked */
|
1050 |
memset(pdev->cmask + offset, 0, size);
|
1051 |
memset(pdev->used + offset, 0, size);
|
1052 |
|
1053 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
1054 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
1055 |
} |
1056 |
|
1057 |
/* Reserve space for capability at a known offset (to call after load). */
|
1058 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
1059 |
{ |
1060 |
memset(pdev->used + offset, 0xff, size);
|
1061 |
} |
1062 |
|
1063 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
1064 |
{ |
1065 |
return pci_find_capability_list(pdev, cap_id, NULL); |
1066 |
} |
1067 |
|
1068 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
1069 |
{ |
1070 |
PCIDevice *d = (PCIDevice *)dev; |
1071 |
const pci_class_desc *desc;
|
1072 |
char ctxt[64]; |
1073 |
PCIIORegion *r; |
1074 |
int i, class;
|
1075 |
|
1076 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
1077 |
desc = pci_class_descriptions; |
1078 |
while (desc->desc && class != desc->class)
|
1079 |
desc++; |
1080 |
if (desc->desc) {
|
1081 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
1082 |
} else {
|
1083 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
1084 |
} |
1085 |
|
1086 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
1087 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
1088 |
indent, "", ctxt,
|
1089 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7, |
1090 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
1091 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))), |
1092 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))), |
1093 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID)))); |
1094 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1095 |
r = &d->io_regions[i]; |
1096 |
if (!r->size)
|
1097 |
continue;
|
1098 |
monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "", |
1099 |
i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem", |
1100 |
r->addr, r->addr + r->size - 1);
|
1101 |
} |
1102 |
} |
1103 |
|
1104 |
static PCIDeviceInfo bridge_info = {
|
1105 |
.qdev.name = "pci-bridge",
|
1106 |
.qdev.size = sizeof(PCIBridge),
|
1107 |
.init = pci_bridge_initfn, |
1108 |
.config_write = pci_bridge_write_config, |
1109 |
.qdev.props = (Property[]) { |
1110 |
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), |
1111 |
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), |
1112 |
DEFINE_PROP_END_OF_LIST(), |
1113 |
} |
1114 |
}; |
1115 |
|
1116 |
static void pci_register_devices(void) |
1117 |
{ |
1118 |
pci_qdev_register(&bridge_info); |
1119 |
} |
1120 |
|
1121 |
device_init(pci_register_devices) |