/ - Diff - qemu - Greek Research and Technology Network's projects

     #define CP0C3_MT   2
     #define CP0C3_SM   1
     #define CP0C3_TL   0
         int32_t CP0_Config6;
         int32_t CP0_Config7;
         target_ulong CP0_LLAddr;
         target_ulong CP0_WatchLo;
         int32_t CP0_WatchHi;

b/target-mips/exec.h
152	152	void cpu_loop_exit(void);
153	153	void do_raise_exception_err (uint32_t exception, int error_code);
154	154	void do_raise_exception (uint32_t exception);
	155	void do_raise_exception_direct_err (uint32_t exception, int error_code);
155	156	void do_raise_exception_direct (uint32_t exception);
156	157
157	158	void cpu_dump_state(CPUState env, FILE f,

b/target-mips/op.c
1180	1180	RETURN();
1181	1181	}
1182	1182
	1183	void op_mfc0_config6 (void)
	1184	{
	1185	T0 = env->CP0_Config6;
	1186	RETURN();
	1187	}
	1188
	1189	void op_mfc0_config7 (void)
	1190	{
	1191	T0 = env->CP0_Config7;
	1192	RETURN();
	1193	}
	1194
1183	1195	void op_mfc0_lladdr (void)
1184	1196	{
1185	1197	T0 = (int32_t)env->CP0_LLAddr >> 4;
...	...
1653	1665	void op_cp1_enabled(void)
1654	1666	{
1655	1667	if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1656		CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
	1668	CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 1);
1657	1669	}
1658	1670	RETURN();
1659	1671	}

b/target-mips/op_helper.c
56	56	cpu_restore_state (tb, env, pc, NULL);
57	57	}
58	58
59		void do_raise_exception_direct (uint32_t exception)
	59	void do_raise_exception_direct_err (uint32_t exception, int error_code)
60	60	{
61	61	do_restore_state (GETPC ());
62		do_raise_exception_err (exception, 0);
	62	do_raise_exception_err (exception, error_code);
	63	}
	64
	65	void do_raise_exception_direct (uint32_t exception)
	66	{
	67	do_raise_exception_direct_err (exception, 0);
63	68	}
64	69
65	70	#define MEMSUFFIX _raw

             break;
         default:
             MIPS_INVAL("float load/store");
             generate_exception_err(ctx, EXCP_CpU, 1);
             generate_exception(ctx, EXCP_RI);
             return;
+        }
         MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
-...
         case 16:
             switch (sel) {
             case 0:
                gen_op_mfc0_config0();
                 gen_op_mfc0_config0();
                 rn = "Config";
                 break;
             case 1:
                gen_op_mfc0_config1();
                 gen_op_mfc0_config1();
                 rn = "Config1";
                 break;
             case 2:
                gen_op_mfc0_config2();
                 gen_op_mfc0_config2();
                 rn = "Config2";
                 break;
             case 3:
                gen_op_mfc0_config3();
                 gen_op_mfc0_config3();
                 rn = "Config3";
                 break;
            /* 6,7 are implementation dependent */
             /* 4,5 are reserved */
             /* 6,7 are implementation dependent */
             case 6:
                 gen_op_mfc0_config6();
                 rn = "Config6";
                 break;
             case 7:
                 gen_op_mfc0_config7();
                 rn = "Config7";
                 break;
             default:
                 goto die;
+            }
-...
         case 16:
             switch (sel) {
             case 0:
                gen_op_mtc0_config0();
                 gen_op_mtc0_config0();
                 rn = "Config";
                 break;
             case 1:
                /* ignored */
                 /* ignored, read only */
                 rn = "Config1";
                 break;
             case 2:
                gen_op_mtc0_config2();
                 gen_op_mtc0_config2();
                 rn = "Config2";
                 break;
             case 3:
                /* ignored */
                 /* ignored, read only */
                 rn = "Config3";
                 break;
            /* 6,7 are implementation dependent */
             /* 4,5 are reserved */
             /* 6,7 are implementation dependent */
             case 6:
                 /* ignored */
                 rn = "Config6";
                 break;
             case 7:
                 /* ignored */
                 rn = "Config7";
                 break;
             default:
                 rn = "Invalid config selector";
                 goto die;
+            }
            /* Stop translation as we may have switched the execution mode */
            ctx->bstate = BS_STOP;
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 17:
             switch (sel) {
-...
             break;
         default:
             MIPS_INVAL("cp1 branch/jump");
             generate_exception_err (ctx, EXCP_RI, 1);
             generate_exception (ctx, EXCP_RI);
             return;
+        }
         gen_op_set_bcond();
-...
         case OPC_CFC1:
             if (fs != 0 && fs != 31) {
                 MIPS_INVAL("cfc1 freg");
                 generate_exception_err (ctx, EXCP_RI, 1);
                 generate_exception (ctx, EXCP_RI);
                 return;
+            }
             GEN_LOAD_IMM_TN(T1, fs);
-...
         case OPC_CTC1:
              if (fs != 0 && fs != 31) {
                 MIPS_INVAL("ctc1 freg");
                 generate_exception_err (ctx, EXCP_RI, 1);
                 generate_exception (ctx, EXCP_RI);
                 return;
+            }
             GEN_LOAD_IMM_TN(T1, fs);
-...
                         ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
                         ((ctx->opcode >> 16) & 0x1F));
+            }
             generate_exception_err (ctx, EXCP_RI, 1);
             generate_exception (ctx, EXCP_RI);
             return;
+        }
         MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
-...
      */
     #define CHECK_FR(ctx, freg) do { \
             if (!((ctx)->CP0_Status & (1<<CP0St_FR)) && ((freg) & 1)) { \
                 generate_exception_err (ctx, EXCP_RI, 1); \
                 generate_exception (ctx, EXCP_RI); \
                 return; \
             } \
         } while(0)
-...
                         ctx->opcode, ctx->opcode >> 26, ctx->opcode & 0x3F,
                         ((ctx->opcode >> 16) & 0x1F));
+            }
             generate_exception_err (ctx, EXCP_RI, 1);
             generate_exception (ctx, EXCP_RI);
             return;
+        }
         if (binary)
-...
             case OPC_MOVCI:
                 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
                     save_cpu_state(ctx, 1);
                     gen_op_cp1_enabled();
                     gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
                               (ctx->opcode >> 16) & 1);
                 } else {
                     generate_exception(ctx, EXCP_RI);
                     generate_exception_err(ctx, EXCP_CpU, 1);
+                }
                 break;
-...
                     gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa);
                     break;
                 default:
                     generate_exception_err(ctx, EXCP_RI, 1);
                     generate_exception (ctx, EXCP_RI);
                     break;
+                }
             } else {
-...
         case OPC_CP3:
             if (env->CP0_Config1 & (1 << CP0C1_FP)) {
                 save_cpu_state(ctx, 1);
                 gen_op_cp1_enabled();
                 op1 = MASK_CP3(ctx->opcode);
                 switch (op1) {
                 /* Not implemented */
                 default:
                     generate_exception_err(ctx, EXCP_RI, 1);
                     generate_exception (ctx, EXCP_RI);
                     break;
+                }
             } else {
                 generate_exception(ctx, EXCP_RI);
                 generate_exception_err(ctx, EXCP_CpU, 1);
+            }
             break;

Archipelago » qemu

Revision e397ee33