Archipelago » qemu

    d->devreset = devreset;

    d->opaque = opaque;

    qemu_register_reset((QEMUResetHandler *)devreset, d);

    return d;

}

    *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);

    register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);

    qemu_register_reset(cuda_reset, s);

}

    register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load,

                    &s->host_state);

    qemu_register_reset(pci_grackle_reset, &s->host_state);

    return 0;

}

    register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,

                    heathrow_pic_load, s);

    qemu_register_reset(heathrow_pic_reset, s);

    return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);

}

                                             pmac_ide_write, d);

    vmstate_register(0, &vmstate_pmac, d);

    qemu_register_reset(pmac_ide_reset, d);

    return pmac_ide_memory;

}

    *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);

    register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);

    qemu_register_reset(dbdma_reset, s);

    dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);

    register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,

                    s);

    qemu_register_reset(macio_nvram_reset, s);

    return s;

}

    opp->irq_raise = openpic_irq_raise;

    opp->reset = openpic_reset;

    if (pmem_index)

        *pmem_index = opp->mem_index;

    register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);

    qemu_register_reset(mpic_reset, mpp);

    return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);

    fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,

                                         ref405ep_fpga_write, fpga);

    cpu_register_physical_memory(base, 0x00000100, fpga_memory);

    qemu_register_reset(&ref405ep_fpga_reset, fpga);

}

    cpld_memory = cpu_register_io_memory(taihu_cpld_read,

                                         taihu_cpld_write, cpld);

    cpu_register_physical_memory(base, 0x00000100, cpld_memory);

    qemu_register_reset(&taihu_cpld_reset, cpld);

}

    ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);

    ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);

    ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);

    qemu_register_reset(ppc4xx_plb_reset, plb);

}

    ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);

    ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);

    qemu_register_reset(ppc4xx_pob_reset, pob);

}

/*****************************************************************************/

#endif

    io = cpu_register_io_memory(opba_read, opba_write, opba);

    cpu_register_physical_memory(base, 0x002, io);

    qemu_register_reset(ppc4xx_opba_reset, opba);

}

    ppc4xx_ebc_t *ebc;

    ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));

    qemu_register_reset(&ebc_reset, ebc);

    ppc_dcr_register(env, EBC0_CFGADDR,

                     ebc, &dcr_read_ebc, &dcr_write_ebc);

    dma = qemu_mallocz(sizeof(ppc405_dma_t));

    memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));

    qemu_register_reset(&ppc405_dma_reset, dma);

    ppc_dcr_register(env, DMA0_CR0,

                     dma, &dcr_read_dma, &dcr_write_dma);

#endif

    io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);

    cpu_register_physical_memory(base, 0x038, io);

    qemu_register_reset(&ppc405_gpio_reset, gpio);

}

    ocm = qemu_mallocz(sizeof(ppc405_ocm_t));

    ocm->offset = qemu_ram_alloc(4096);

    qemu_register_reset(&ocm_reset, ocm);

    ppc_dcr_register(env, OCM0_ISARC,

                     ocm, &dcr_read_ocm, &dcr_write_ocm);

#endif

    io = cpu_register_io_memory(i2c_read, i2c_write, i2c);

    cpu_register_physical_memory(base, 0x011, io);

    qemu_register_reset(ppc4xx_i2c_reset, i2c);

}

    io = cpu_register_io_memory(gpt_read, gpt_write, gpt);

    cpu_register_physical_memory(base, 0x0d4, io);

    qemu_register_reset(ppc4xx_gpt_reset, gpt);

}

/*****************************************************************************/

    mal = qemu_mallocz(sizeof(ppc40x_mal_t));

    for (i = 0; i < 4; i++)

        mal->irqs[i] = irqs[i];

    qemu_register_reset(&ppc40x_mal_reset, mal);

    ppc_dcr_register(env, MAL0_CFG,

                     mal, &dcr_read_mal, &dcr_write_mal);

                     &dcr_read_crcpc, &dcr_write_crcpc);

    ppc405cr_clk_init(cpc);

    qemu_register_reset(ppc405cr_cpc_reset, cpc);

}

CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],

           PPC405EP_CLK_NB * sizeof(clk_setup_t));

    cpc->jtagid = 0x20267049;

    cpc->sysclk = sysclk;

    qemu_register_reset(&ppc405ep_cpc_reset, cpc);

    ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,

                     &dcr_read_epcpc, &dcr_write_epcpc);

                         &dcr_read_uic, &dcr_write_uic);

    }

    qemu_register_reset(ppcuic_reset, uic);

    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);

}

    memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));

    memcpy(sdram->ram_sizes, ram_sizes,

           nbanks * sizeof(target_phys_addr_t));

    qemu_register_reset(&sdram_reset, sdram);

    ppc_dcr_register(env, SDRAM0_CFGADDR,

                     sdram, &dcr_read_sdram, &dcr_write_sdram);

    register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state);

    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;

}

    ppc_translate_init();

    env->cpu_model_str = cpu_model;

    cpu_ppc_register_internal(env, def);

    cpu_ppc_reset(env);

    qemu_init_vcpu(env);