Revision e4c7d2ae

b/Makefile.objs
186 186
# PCI watchdog devices
187 187
hw-obj-y += wdt_i6300esb.o
188 188

  
189
hw-obj-y += msix.o
189
hw-obj-y += msix.o msi.o
190 190

  
191 191
# PCI network cards
192 192
hw-obj-y += ne2000.o
b/hw/msi.c
1
/*
2
 * msi.c
3
 *
4
 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5
 *                    VA Linux Systems Japan K.K.
6
 *
7
 * This program is free software; you can redistribute it and/or modify
8
 * it under the terms of the GNU General Public License as published by
9
 * the Free Software Foundation; either version 2 of the License, or
10
 * (at your option) any later version.
11

  
12
 * This program is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
 * GNU General Public License for more details.
16

  
17
 * You should have received a copy of the GNU General Public License along
18
 * with this program; if not, see <http://www.gnu.org/licenses/>.
19
 */
20

  
21
#include "msi.h"
22

  
23
/* Eventually those constants should go to Linux pci_regs.h */
24
#define PCI_MSI_PENDING_32      0x10
25
#define PCI_MSI_PENDING_64      0x14
26

  
27
/* PCI_MSI_ADDRESS_LO */
28
#define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
29

  
30
/* If we get rid of cap allocator, we won't need those. */
31
#define PCI_MSI_32_SIZEOF       0x0a
32
#define PCI_MSI_64_SIZEOF       0x0e
33
#define PCI_MSI_32M_SIZEOF      0x14
34
#define PCI_MSI_64M_SIZEOF      0x18
35

  
36
#define PCI_MSI_VECTORS_MAX     32
37

  
38
/* If we get rid of cap allocator, we won't need this. */
39
static inline uint8_t msi_cap_sizeof(uint16_t flags)
40
{
41
    switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
42
    case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
43
        return PCI_MSI_64M_SIZEOF;
44
    case PCI_MSI_FLAGS_64BIT:
45
        return PCI_MSI_64_SIZEOF;
46
    case PCI_MSI_FLAGS_MASKBIT:
47
        return PCI_MSI_32M_SIZEOF;
48
    case 0:
49
        return PCI_MSI_32_SIZEOF;
50
    default:
51
        abort();
52
        break;
53
    }
54
    return 0;
55
}
56

  
57
//#define MSI_DEBUG
58

  
59
#ifdef MSI_DEBUG
60
# define MSI_DPRINTF(fmt, ...)                                          \
61
    fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
62
#else
63
# define MSI_DPRINTF(fmt, ...)  do { } while (0)
64
#endif
65
#define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
66
    MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
67

  
68
static inline unsigned int msi_nr_vectors(uint16_t flags)
69
{
70
    return 1U <<
71
        ((flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1));
72
}
73

  
74
static inline uint8_t msi_flags_off(const PCIDevice* dev)
75
{
76
    return dev->msi_cap + PCI_MSI_FLAGS;
77
}
78

  
79
static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
80
{
81
    return dev->msi_cap + PCI_MSI_ADDRESS_LO;
82
}
83

  
84
static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
85
{
86
    return dev->msi_cap + PCI_MSI_ADDRESS_HI;
87
}
88

  
89
static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
90
{
91
    return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
92
}
93

  
94
static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
95
{
96
    return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
97
}
98

  
99
static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
100
{
101
    return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
102
}
103

  
104
bool msi_enabled(const PCIDevice *dev)
105
{
106
    return msi_present(dev) &&
107
        (pci_get_word(dev->config + msi_flags_off(dev)) &
108
         PCI_MSI_FLAGS_ENABLE);
109
}
110

  
111
int msi_init(struct PCIDevice *dev, uint8_t offset,
112
             unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
113
{
114
    unsigned int vectors_order;
115
    uint16_t flags;
116
    uint8_t cap_size;
117
    int config_offset;
118
    MSI_DEV_PRINTF(dev,
119
                   "init offset: 0x%"PRIx8" vector: %"PRId8
120
                   " 64bit %d mask %d\n",
121
                   offset, nr_vectors, msi64bit, msi_per_vector_mask);
122

  
123
    assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
124
    assert(nr_vectors > 0);
125
    assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
126
    /* the nr of MSI vectors is up to 32 */
127
    vectors_order = ffs(nr_vectors) - 1;
128

  
129
    flags = vectors_order << (ffs(PCI_MSI_FLAGS_QMASK) - 1);
130
    if (msi64bit) {
131
        flags |= PCI_MSI_FLAGS_64BIT;
132
    }
133
    if (msi_per_vector_mask) {
134
        flags |= PCI_MSI_FLAGS_MASKBIT;
135
    }
136

  
137
    cap_size = msi_cap_sizeof(flags);
138
    config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
139
    if (config_offset < 0) {
140
        return config_offset;
141
    }
142

  
143
    dev->msi_cap = config_offset;
144
    dev->cap_present |= QEMU_PCI_CAP_MSI;
145

  
146
    pci_set_word(dev->config + msi_flags_off(dev), flags);
147
    pci_set_word(dev->wmask + msi_flags_off(dev),
148
                 PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
149
    pci_set_long(dev->wmask + msi_address_lo_off(dev),
150
                 PCI_MSI_ADDRESS_LO_MASK);
151
    if (msi64bit) {
152
        pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
153
    }
154
    pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
155

  
156
    if (msi_per_vector_mask) {
157
        pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
158
                     /* (1U << nr_vectors) - 1 is undefined
159
                        when nr_vectors = 32 */
160
                     0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
161
    }
162
    return config_offset;
163
}
164

  
165
void msi_uninit(struct PCIDevice *dev)
166
{
167
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
168
    uint8_t cap_size = msi_cap_sizeof(flags);
169
    pci_del_capability(dev, PCI_CAP_ID_MSIX, cap_size);
170
    MSI_DEV_PRINTF(dev, "uninit\n");
171
}
172

  
173
void msi_reset(PCIDevice *dev)
174
{
175
    uint16_t flags;
176
    bool msi64bit;
177

  
178
    flags = pci_get_word(dev->config + msi_flags_off(dev));
179
    flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
180
    msi64bit = flags & PCI_MSI_FLAGS_64BIT;
181

  
182
    pci_set_word(dev->config + msi_flags_off(dev), flags);
183
    pci_set_long(dev->config + msi_address_lo_off(dev), 0);
184
    if (msi64bit) {
185
        pci_set_long(dev->config + msi_address_hi_off(dev), 0);
186
    }
187
    pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
188
    if (flags & PCI_MSI_FLAGS_MASKBIT) {
189
        pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
190
        pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
191
    }
192
    MSI_DEV_PRINTF(dev, "reset\n");
193
}
194

  
195
static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
196
{
197
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
198
    uint32_t mask;
199
    assert(vector < PCI_MSI_VECTORS_MAX);
200

  
201
    if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
202
        return false;
203
    }
204

  
205
    mask = pci_get_long(dev->config +
206
                        msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
207
    return mask & (1U << vector);
208
}
209

  
210
void msi_notify(PCIDevice *dev, unsigned int vector)
211
{
212
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
213
    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
214
    unsigned int nr_vectors = msi_nr_vectors(flags);
215
    uint64_t address;
216
    uint32_t data;
217

  
218
    assert(vector < nr_vectors);
219
    if (msi_is_masked(dev, vector)) {
220
        assert(flags & PCI_MSI_FLAGS_MASKBIT);
221
        pci_long_test_and_set_mask(
222
            dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
223
        MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
224
        return;
225
    }
226

  
227
    if (msi64bit){
228
        address = pci_get_quad(dev->config + msi_address_lo_off(dev));
229
    } else {
230
        address = pci_get_long(dev->config + msi_address_lo_off(dev));
231
    }
232

  
233
    /* upper bit 31:16 is zero */
234
    data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
235
    if (nr_vectors > 1) {
236
        data &= ~(nr_vectors - 1);
237
        data |= vector;
238
    }
239

  
240
    MSI_DEV_PRINTF(dev,
241
                   "notify vector 0x%x"
242
                   " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
243
                   vector, address, data);
244
    stl_phys(address, data);
245
}
246

  
247
/* call this function after updating configs by pci_default_write_config(). */
248
void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
249
{
250
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
251
    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
252
    bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
253
    unsigned int nr_vectors;
254
    uint8_t log_num_vecs;
255
    uint8_t log_max_vecs;
256
    unsigned int vector;
257
    uint32_t pending;
258
    int i;
259

  
260
#ifdef MSI_DEBUG
261
    if (ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
262
        MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
263
                       addr, val, len);
264
        MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
265
                       flags,
266
                       pci_get_long(dev->config + msi_address_lo_off(dev)));
267
        if (msi64bit) {
268
            fprintf(stderr, " addrss-hi: 0x%"PRIx32,
269
                    pci_get_long(dev->config + msi_address_hi_off(dev)));
270
        }
271
        fprintf(stderr, " data: 0x%"PRIx16,
272
                pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
273
        if (flags & PCI_MSI_FLAGS_MASKBIT) {
274
            fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
275
                    pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
276
                    pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
277
        }
278
        fprintf(stderr, "\n");
279
    }
280
#endif
281

  
282
    /* Are we modified? */
283
    if (!(ranges_overlap(addr, len, msi_flags_off(dev), 2) ||
284
          (msi_per_vector_mask &&
285
           ranges_overlap(addr, len, msi_mask_off(dev, msi64bit), 4)))) {
286
        return;
287
    }
288

  
289
    if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
290
        return;
291
    }
292

  
293
    /*
294
     * Now MSI is enabled, clear INTx# interrupts.
295
     * the driver is prohibited from writing enable bit to mask
296
     * a service request. But the guest OS could do this.
297
     * So we just discard the interrupts as moderate fallback.
298
     *
299
     * 6.8.3.3. Enabling Operation
300
     *   While enabled for MSI or MSI-X operation, a function is prohibited
301
     *   from using its INTx# pin (if implemented) to request
302
     *   service (MSI, MSI-X, and INTx# are mutually exclusive).
303
     */
304
    for (i = 0; i < PCI_NUM_PINS; ++i) {
305
        qemu_set_irq(dev->irq[i], 0);
306
    }
307

  
308
    /*
309
     * nr_vectors might be set bigger than capable. So clamp it.
310
     * This is not legal by spec, so we can do anything we like,
311
     * just don't crash the host
312
     */
313
    log_num_vecs =
314
        (flags & PCI_MSI_FLAGS_QSIZE) >> (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
315
    log_max_vecs =
316
        (flags & PCI_MSI_FLAGS_QMASK) >> (ffs(PCI_MSI_FLAGS_QMASK) - 1);
317
    if (log_num_vecs > log_max_vecs) {
318
        flags &= ~PCI_MSI_FLAGS_QSIZE;
319
        flags |= log_max_vecs << (ffs(PCI_MSI_FLAGS_QSIZE) - 1);
320
        pci_set_word(dev->config + msi_flags_off(dev), flags);
321
    }
322

  
323
    if (!msi_per_vector_mask) {
324
        /* if per vector masking isn't supported,
325
           there is no pending interrupt. */
326
        return;
327
    }
328

  
329
    nr_vectors = msi_nr_vectors(flags);
330

  
331
    /* This will discard pending interrupts, if any. */
332
    pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
333
    pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
334
    pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
335

  
336
    /* deliver pending interrupts which are unmasked */
337
    for (vector = 0; vector < nr_vectors; ++vector) {
338
        if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
339
            continue;
340
        }
341

  
342
        pci_long_test_and_clear_mask(
343
            dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
344
        msi_notify(dev, vector);
345
    }
346
}
347

  
348
unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
349
{
350
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
351
    return msi_nr_vectors(flags);
352
}
b/hw/msi.h
1
/*
2
 * msi.h
3
 *
4
 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5
 *                    VA Linux Systems Japan K.K.
6
 *
7
 * This program is free software; you can redistribute it and/or modify
8
 * it under the terms of the GNU General Public License as published by
9
 * the Free Software Foundation; either version 2 of the License, or
10
 * (at your option) any later version.
11

  
12
 * This program is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
 * GNU General Public License for more details.
16

  
17
 * You should have received a copy of the GNU General Public License along
18
 * with this program; if not, see <http://www.gnu.org/licenses/>.
19
 */
20

  
21
#ifndef QEMU_MSI_H
22
#define QEMU_MSI_H
23

  
24
#include "qemu-common.h"
25
#include "pci.h"
26

  
27
bool msi_enabled(const PCIDevice *dev);
28
int msi_init(struct PCIDevice *dev, uint8_t offset,
29
             unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask);
30
void msi_uninit(struct PCIDevice *dev);
31
void msi_reset(PCIDevice *dev);
32
void msi_notify(PCIDevice *dev, unsigned int vector);
33
void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len);
34
unsigned int msi_nr_vectors_allocated(const PCIDevice *dev);
35

  
36
static inline bool msi_present(const PCIDevice *dev)
37
{
38
    return dev->cap_present & QEMU_PCI_CAP_MSI;
39
}
40

  
41
#endif /* QEMU_MSI_H */
b/hw/pci.h
109 109

  
110 110
/* Bits in cap_present field. */
111 111
enum {
112
    QEMU_PCI_CAP_MSIX = 0x1,
113
    QEMU_PCI_CAP_EXPRESS = 0x2,
112
    QEMU_PCI_CAP_MSI = 0x1,
113
    QEMU_PCI_CAP_MSIX = 0x2,
114
    QEMU_PCI_CAP_EXPRESS = 0x4,
114 115

  
115 116
    /* multifunction capable device */
116
#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        2
117
#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
117 118
    QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
118 119
};
119 120

  
......
171 172
    /* Version id needed for VMState */
172 173
    int32_t version_id;
173 174

  
175
    /* Offset of MSI capability in config space */
176
    uint8_t msi_cap;
177

  
174 178
    /* Location of option rom */
175 179
    char *romfile;
176 180
    ram_addr_t rom_offset;

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