Revision e5332e63
| b/dma-helpers.c | ||
|---|---|---|
| 9 | 9 |
|
| 10 | 10 |
#include "dma.h" |
| 11 | 11 |
#include "trace.h" |
| 12 |
#include "range.h" |
|
| 13 |
#include "qemu-thread.h" |
|
| 12 | 14 |
|
| 13 |
int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len) |
|
| 15 |
/* #define DEBUG_IOMMU */ |
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| 16 |
|
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| 17 |
static void do_dma_memory_set(dma_addr_t addr, uint8_t c, dma_addr_t len) |
|
| 14 | 18 |
{
|
| 15 | 19 |
#define FILLBUF_SIZE 512 |
| 16 | 20 |
uint8_t fillbuf[FILLBUF_SIZE]; |
| ... | ... | |
| 23 | 27 |
len -= len; |
| 24 | 28 |
addr += len; |
| 25 | 29 |
} |
| 30 |
} |
|
| 31 |
|
|
| 32 |
int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len) |
|
| 33 |
{
|
|
| 34 |
if (dma_has_iommu(dma)) {
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| 35 |
return iommu_dma_memory_set(dma, addr, c, len); |
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} |
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do_dma_memory_set(addr, c, len); |
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|
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| 26 | 39 |
return 0; |
| 27 | 40 |
} |
| 28 | 41 |
|
| ... | ... | |
| 260 | 273 |
{
|
| 261 | 274 |
bdrv_acct_start(bs, cookie, sg->size, type); |
| 262 | 275 |
} |
| 276 |
|
|
| 277 |
bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len, |
|
| 278 |
DMADirection dir) |
|
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{
|
|
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target_phys_addr_t paddr, plen; |
|
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|
|
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#ifdef DEBUG_IOMMU |
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fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT |
|
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" len=0x" DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir); |
|
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#endif |
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|
|
| 287 |
while (len) {
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| 288 |
if (dma->translate(dma, addr, &paddr, &plen, dir) != 0) {
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return false; |
|
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} |
|
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|
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/* The translation might be valid for larger regions. */ |
|
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if (plen > len) {
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plen = len; |
|
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} |
|
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|
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len -= plen; |
|
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addr += plen; |
|
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} |
|
| 300 |
|
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return true; |
|
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} |
|
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|
|
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int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr, |
|
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void *buf, dma_addr_t len, DMADirection dir) |
|
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{
|
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target_phys_addr_t paddr, plen; |
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int err; |
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|
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#ifdef DEBUG_IOMMU |
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fprintf(stderr, "dma_memory_rw context=%p addr=0x" DMA_ADDR_FMT " len=0x" |
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DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir); |
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#endif |
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|
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while (len) {
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err = dma->translate(dma, addr, &paddr, &plen, dir); |
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if (err) {
|
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/* |
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* In case of failure on reads from the guest, we clean the |
|
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* destination buffer so that a device that doesn't test |
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* for errors will not expose qemu internal memory. |
|
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*/ |
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memset(buf, 0, len); |
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return -1; |
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} |
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/* The translation might be valid for larger regions. */ |
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if (plen > len) {
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plen = len; |
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} |
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|
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cpu_physical_memory_rw(paddr, buf, plen, |
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dir == DMA_DIRECTION_FROM_DEVICE); |
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|
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len -= plen; |
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addr += plen; |
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buf += plen; |
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} |
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|
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return 0; |
|
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} |
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|
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int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, |
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dma_addr_t len) |
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{
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target_phys_addr_t paddr, plen; |
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int err; |
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|
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#ifdef DEBUG_IOMMU |
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fprintf(stderr, "dma_memory_set context=%p addr=0x" DMA_ADDR_FMT |
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" len=0x" DMA_ADDR_FMT "\n", dma, addr, len); |
|
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#endif |
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|
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while (len) {
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err = dma->translate(dma, addr, &paddr, &plen, |
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DMA_DIRECTION_FROM_DEVICE); |
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if (err) {
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return err; |
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} |
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/* The translation might be valid for larger regions. */ |
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if (plen > len) {
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plen = len; |
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} |
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do_dma_memory_set(paddr, c, plen); |
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len -= plen; |
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addr += plen; |
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} |
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return 0; |
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} |
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|
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void dma_context_init(DMAContext *dma, DMATranslateFunc translate, |
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DMAMapFunc map, DMAUnmapFunc unmap) |
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{
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#ifdef DEBUG_IOMMU |
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fprintf(stderr, "dma_context_init(%p, %p, %p, %p)\n", |
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dma, translate, map, unmap); |
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#endif |
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dma->translate = translate; |
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dma->map = map; |
|
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dma->unmap = unmap; |
|
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} |
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|
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void *iommu_dma_memory_map(DMAContext *dma, dma_addr_t addr, dma_addr_t *len, |
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DMADirection dir) |
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{
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| 390 |
int err; |
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target_phys_addr_t paddr, plen; |
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void *buf; |
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if (dma->map) {
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return dma->map(dma, addr, len, dir); |
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} |
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plen = *len; |
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err = dma->translate(dma, addr, &paddr, &plen, dir); |
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if (err) {
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return NULL; |
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} |
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|
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/* |
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* If this is true, the virtual region is contiguous, |
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* but the translated physical region isn't. We just |
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* clamp *len, much like cpu_physical_memory_map() does. |
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*/ |
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if (plen < *len) {
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*len = plen; |
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} |
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buf = cpu_physical_memory_map(paddr, &plen, |
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dir == DMA_DIRECTION_FROM_DEVICE); |
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*len = plen; |
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return buf; |
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} |
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|
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void iommu_dma_memory_unmap(DMAContext *dma, void *buffer, dma_addr_t len, |
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DMADirection dir, dma_addr_t access_len) |
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{
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if (dma->unmap) {
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dma->unmap(dma, buffer, len, dir, access_len); |
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return; |
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} |
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cpu_physical_memory_unmap(buffer, len, |
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dir == DMA_DIRECTION_FROM_DEVICE, |
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access_len); |
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|
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} |
|
| b/dma.h | ||
|---|---|---|
| 31 | 31 |
}; |
| 32 | 32 |
|
| 33 | 33 |
#if defined(TARGET_PHYS_ADDR_BITS) |
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typedef target_phys_addr_t dma_addr_t; |
|
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#define DMA_ADDR_BITS TARGET_PHYS_ADDR_BITS |
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#define DMA_ADDR_FMT TARGET_FMT_plx |
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/* |
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* When an IOMMU is present, bus addresses become distinct from |
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* CPU/memory physical addresses and may be a different size. Because |
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* the IOVA size depends more on the bus than on the platform, we more |
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* or less have to treat these as 64-bit always to cover all (or at |
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* least most) cases. |
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*/ |
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typedef uint64_t dma_addr_t; |
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|
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#define DMA_ADDR_BITS 64 |
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#define DMA_ADDR_FMT "%" PRIx64 |
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|
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typedef int DMATranslateFunc(DMAContext *dma, |
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dma_addr_t addr, |
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target_phys_addr_t *paddr, |
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target_phys_addr_t *len, |
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DMADirection dir); |
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typedef void* DMAMapFunc(DMAContext *dma, |
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dma_addr_t addr, |
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dma_addr_t *len, |
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DMADirection dir); |
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typedef void DMAUnmapFunc(DMAContext *dma, |
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void *buffer, |
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dma_addr_t len, |
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DMADirection dir, |
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dma_addr_t access_len); |
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|
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struct DMAContext {
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DMATranslateFunc *translate; |
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DMAMapFunc *map; |
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DMAUnmapFunc *unmap; |
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}; |
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|
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static inline bool dma_has_iommu(DMAContext *dma) |
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{
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return !!dma; |
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} |
|
| 38 | 72 |
|
| 39 | 73 |
/* Checks that the given range of addresses is valid for DMA. This is |
| 40 | 74 |
* useful for certain cases, but usually you should just use |
| 41 | 75 |
* dma_memory_{read,write}() and check for errors */
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| 42 |
static inline bool dma_memory_valid(DMAContext *dma, dma_addr_t addr, |
|
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dma_addr_t len, DMADirection dir) |
|
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bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len, |
|
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DMADirection dir); |
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static inline bool dma_memory_valid(DMAContext *dma, |
|
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dma_addr_t addr, dma_addr_t len, |
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DMADirection dir) |
|
| 44 | 81 |
{
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/* Stub version, with no iommu we assume all bus addresses are valid */ |
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return true; |
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if (!dma_has_iommu(dma)) {
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return true; |
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} else {
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return iommu_dma_memory_valid(dma, addr, len, dir); |
|
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} |
|
| 47 | 87 |
} |
| 48 | 88 |
|
| 89 |
int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr, |
|
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void *buf, dma_addr_t len, DMADirection dir); |
|
| 49 | 91 |
static inline int dma_memory_rw(DMAContext *dma, dma_addr_t addr, |
| 50 | 92 |
void *buf, dma_addr_t len, DMADirection dir) |
| 51 | 93 |
{
|
| 52 |
/* Stub version when we have no iommu support */ |
|
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cpu_physical_memory_rw(addr, buf, (target_phys_addr_t)len, |
|
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dir == DMA_DIRECTION_FROM_DEVICE); |
|
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return 0; |
|
| 94 |
if (!dma_has_iommu(dma)) {
|
|
| 95 |
/* Fast-path for no IOMMU */ |
|
| 96 |
cpu_physical_memory_rw(addr, buf, len, |
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| 97 |
dir == DMA_DIRECTION_FROM_DEVICE); |
|
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return 0; |
|
| 99 |
} else {
|
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| 100 |
return iommu_dma_memory_rw(dma, addr, buf, len, dir); |
|
| 101 |
} |
|
| 56 | 102 |
} |
| 57 | 103 |
|
| 58 | 104 |
static inline int dma_memory_read(DMAContext *dma, dma_addr_t addr, |
| ... | ... | |
| 68 | 114 |
DMA_DIRECTION_FROM_DEVICE); |
| 69 | 115 |
} |
| 70 | 116 |
|
| 117 |
int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, |
|
| 118 |
dma_addr_t len); |
|
| 119 |
|
|
| 71 | 120 |
int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len); |
| 72 | 121 |
|
| 122 |
void *iommu_dma_memory_map(DMAContext *dma, |
|
| 123 |
dma_addr_t addr, dma_addr_t *len, |
|
| 124 |
DMADirection dir); |
|
| 73 | 125 |
static inline void *dma_memory_map(DMAContext *dma, |
| 74 | 126 |
dma_addr_t addr, dma_addr_t *len, |
| 75 | 127 |
DMADirection dir) |
| 76 | 128 |
{
|
| 77 |
target_phys_addr_t xlen = *len; |
|
| 78 |
void *p; |
|
| 79 |
|
|
| 80 |
p = cpu_physical_memory_map(addr, &xlen, |
|
| 81 |
dir == DMA_DIRECTION_FROM_DEVICE); |
|
| 82 |
*len = xlen; |
|
| 83 |
return p; |
|
| 129 |
if (!dma_has_iommu(dma)) {
|
|
| 130 |
target_phys_addr_t xlen = *len; |
|
| 131 |
void *p; |
|
| 132 |
|
|
| 133 |
p = cpu_physical_memory_map(addr, &xlen, |
|
| 134 |
dir == DMA_DIRECTION_FROM_DEVICE); |
|
| 135 |
*len = xlen; |
|
| 136 |
return p; |
|
| 137 |
} else {
|
|
| 138 |
return iommu_dma_memory_map(dma, addr, len, dir); |
|
| 139 |
} |
|
| 84 | 140 |
} |
| 85 | 141 |
|
| 142 |
void iommu_dma_memory_unmap(DMAContext *dma, |
|
| 143 |
void *buffer, dma_addr_t len, |
|
| 144 |
DMADirection dir, dma_addr_t access_len); |
|
| 86 | 145 |
static inline void dma_memory_unmap(DMAContext *dma, |
| 87 | 146 |
void *buffer, dma_addr_t len, |
| 88 | 147 |
DMADirection dir, dma_addr_t access_len) |
| 89 | 148 |
{
|
| 90 |
return cpu_physical_memory_unmap(buffer, (target_phys_addr_t)len, |
|
| 91 |
dir == DMA_DIRECTION_FROM_DEVICE, |
|
| 92 |
access_len); |
|
| 149 |
if (!dma_has_iommu(dma)) {
|
|
| 150 |
return cpu_physical_memory_unmap(buffer, (target_phys_addr_t)len, |
|
| 151 |
dir == DMA_DIRECTION_FROM_DEVICE, |
|
| 152 |
access_len); |
|
| 153 |
} else {
|
|
| 154 |
iommu_dma_memory_unmap(dma, buffer, len, dir, access_len); |
|
| 155 |
} |
|
| 93 | 156 |
} |
| 94 | 157 |
|
| 95 | 158 |
#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \ |
| ... | ... | |
| 130 | 193 |
|
| 131 | 194 |
#undef DEFINE_LDST_DMA |
| 132 | 195 |
|
| 196 |
void dma_context_init(DMAContext *dma, DMATranslateFunc translate, |
|
| 197 |
DMAMapFunc map, DMAUnmapFunc unmap); |
|
| 198 |
|
|
| 133 | 199 |
struct ScatterGatherEntry {
|
| 134 | 200 |
dma_addr_t base; |
| 135 | 201 |
dma_addr_t len; |
| b/hw/qdev-dma.h | ||
|---|---|---|
| 6 | 6 |
* This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 7 | 7 |
* See the COPYING file in the top-level directory. |
| 8 | 8 |
*/ |
| 9 |
#include "qdev-addr.h" |
|
| 10 |
|
|
| 11 | 9 |
#define DEFINE_PROP_DMAADDR(_n, _s, _f, _d) \ |
| 12 |
DEFINE_PROP_TADDR(_n, _s, _f, _d) |
|
| 10 |
DEFINE_PROP_HEX64(_n, _s, _f, _d) |
|
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