Revision e58c8ba5

b/target-mips/helper.c
403 403 
            env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
404 404 
        }
405 405 
        env->PC += offset;
406 
        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
406 
        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
407 407 
        break;
408 408 
    default:
409 409 
        if (logfile) {
b/target-mips/op.c
1401 1401 
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1402 1402 
        mask |= 1 << CP0Ca_DC;
1403 1403 

  		





  1404
  
  
    
    env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);


  		





  
  1404
  
    
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);


  		





  1405
  1405
  
    

  		





  1406
  1406
  
    
    /* Handle the software interrupt as an hardware one, as they


  		





  1407
  1407
  
    
       are very similar */


  		












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