Revision e58c8ba5 target-mips/op.c
b/target-mips/op.c | ||
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1401 | 1401 |
if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
1402 | 1402 |
mask |= 1 << CP0Ca_DC; |
1403 | 1403 |
|
1404 |
env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask);
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|
1404 |
env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
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|
1405 | 1405 |
|
1406 | 1406 |
/* Handle the software interrupt as an hardware one, as they |
1407 | 1407 |
are very similar */ |
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