Revision e5ad936b hw/apic_common.c
| b/hw/apic_common.c | ||
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#include "apic.h" |
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#include "apic_internal.h" |
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#include "trace.h" |
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#include "kvm.h" |
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static int apic_irq_delivered; |
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bool apic_report_tpr_access; |
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void cpu_set_apic_base(DeviceState *d, uint64_t val) |
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{
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| ... | ... | |
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uint8_t cpu_get_apic_tpr(DeviceState *d) |
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{
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APICCommonState *s; |
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APICCommonClass *info; |
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if (!d) {
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return 0; |
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} |
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s = APIC_COMMON(d); |
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info = APIC_COMMON_GET_CLASS(s); |
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return info->get_tpr(s); |
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} |
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void apic_enable_tpr_access_reporting(DeviceState *d, bool enable) |
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
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apic_report_tpr_access = enable; |
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if (info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, enable); |
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} |
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} |
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void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr) |
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
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return s ? s->tpr >> 4 : 0; |
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s->vapic_paddr = paddr; |
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info->vapic_base_update(s); |
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} |
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void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
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TPRAccess access) |
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
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vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access); |
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} |
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void apic_report_irq_delivered(int delivered) |
| ... | ... | |
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static void apic_reset_common(DeviceState *d) |
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); |
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
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bool bsp; |
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bsp = cpu_is_bsp(s->cpu_env); |
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s->apicbase = 0xfee00000 | |
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(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; |
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s->vapic_paddr = 0; |
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info->vapic_base_update(s); |
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apic_init_reset(d); |
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if (bsp) {
|
| ... | ... | |
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{
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APICCommonState *s = APIC_COMMON(dev); |
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APICCommonClass *info; |
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static DeviceState *vapic; |
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static int apic_no; |
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if (apic_no >= MAX_APICS) {
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| ... | ... | |
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info = APIC_COMMON_GET_CLASS(s); |
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info->init(s); |
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sysbus_init_mmio(&s->busdev, &s->io_memory); |
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sysbus_init_mmio(dev, &s->io_memory); |
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if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK) {
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vapic = sysbus_create_simple("kvmvapic", -1, NULL);
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} |
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s->vapic = vapic; |
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if (apic_report_tpr_access && info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, true); |
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} |
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return 0; |
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} |
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static void apic_dispatch_pre_save(void *opaque) |
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{
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APICCommonState *s = APIC_COMMON(opaque); |
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s); |
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if (info->pre_save) {
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info->pre_save(s); |
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} |
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} |
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static int apic_dispatch_post_load(void *opaque, int version_id) |
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{
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APICCommonState *s = APIC_COMMON(opaque); |
| ... | ... | |
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.minimum_version_id = 3, |
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.minimum_version_id_old = 1, |
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.load_state_old = apic_load_old, |
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.pre_save = apic_dispatch_pre_save, |
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.post_load = apic_dispatch_post_load, |
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(apicbase, APICCommonState), |
| ... | ... | |
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static Property apic_properties_common[] = {
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DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
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DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
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DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
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true), |
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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