Revision e5ad936b hw/apic_internal.h
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#define APIC_SV_DIRECTED_IO (1<<12) |
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#define APIC_SV_ENABLE (1<<8) |
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#define VAPIC_ENABLE_BIT 0 |
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#define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT) |
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#define MAX_APICS 255 |
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#define MSI_SPACE_SIZE 0x100000 |
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void (*init)(APICCommonState *s); |
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void (*set_base)(APICCommonState *s, uint64_t val); |
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void (*set_tpr)(APICCommonState *s, uint8_t val); |
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uint8_t (*get_tpr)(APICCommonState *s); |
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void (*enable_tpr_reporting)(APICCommonState *s, bool enable); |
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void (*vapic_base_update)(APICCommonState *s); |
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void (*external_nmi)(APICCommonState *s); |
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void (*pre_save)(APICCommonState *s); |
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void (*post_load)(APICCommonState *s); |
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} APICCommonClass; |
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int64_t timer_expiry; |
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int sipi_vector; |
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int wait_for_sipi; |
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uint32_t vapic_control; |
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DeviceState *vapic; |
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target_phys_addr_t vapic_paddr; /* note: persistence via kvmvapic */ |
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}; |
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typedef struct VAPICState { |
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uint8_t tpr; |
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uint8_t isr; |
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uint8_t zero; |
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uint8_t irr; |
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uint8_t enabled; |
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} QEMU_PACKED VAPICState; |
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extern bool apic_report_tpr_access; |
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void apic_report_irq_delivered(int delivered); |
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bool apic_next_timer(APICCommonState *s, int64_t current_time); |
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void apic_enable_tpr_access_reporting(DeviceState *d, bool enable); |
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void apic_enable_vapic(DeviceState *d, target_phys_addr_t paddr); |
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void apic_poll_irq(DeviceState *d); |
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void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip, |
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TPRAccess access); |
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#endif /* !QEMU_APIC_INTERNAL_H */ |
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