Revision e5c6b25a hw/omap1.c
b/hw/omap1.c | ||
---|---|---|
2804 | 2804 |
omap_mpuio_kbd_update(s); |
2805 | 2805 |
} |
2806 | 2806 |
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2807 |
/* General-Purpose I/O */ |
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2808 |
struct omap_gpio_s { |
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2809 |
qemu_irq irq; |
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2810 |
qemu_irq *in; |
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2811 |
qemu_irq handler[16]; |
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2812 |
|
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2813 |
uint16_t inputs; |
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2814 |
uint16_t outputs; |
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2815 |
uint16_t dir; |
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2816 |
uint16_t edge; |
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2817 |
uint16_t mask; |
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2818 |
uint16_t ints; |
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2819 |
uint16_t pins; |
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2820 |
}; |
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2821 |
|
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2822 |
static void omap_gpio_set(void *opaque, int line, int level) |
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2823 |
{ |
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2824 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
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2825 |
uint16_t prev = s->inputs; |
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2826 |
|
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2827 |
if (level) |
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2828 |
s->inputs |= 1 << line; |
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2829 |
else |
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2830 |
s->inputs &= ~(1 << line); |
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2831 |
|
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2832 |
if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & |
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2833 |
(1 << line) & s->dir & ~s->mask) { |
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2834 |
s->ints |= 1 << line; |
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2835 |
qemu_irq_raise(s->irq); |
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2836 |
} |
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2837 |
} |
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2838 |
|
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2839 |
static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
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2840 |
{ |
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2841 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
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2842 |
int offset = addr & OMAP_MPUI_REG_MASK; |
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2843 |
|
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2844 |
switch (offset) { |
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2845 |
case 0x00: /* DATA_INPUT */ |
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2846 |
return s->inputs & s->pins; |
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2847 |
|
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2848 |
case 0x04: /* DATA_OUTPUT */ |
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2849 |
return s->outputs; |
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2850 |
|
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2851 |
case 0x08: /* DIRECTION_CONTROL */ |
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2852 |
return s->dir; |
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2853 |
|
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2854 |
case 0x0c: /* INTERRUPT_CONTROL */ |
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2855 |
return s->edge; |
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2856 |
|
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2857 |
case 0x10: /* INTERRUPT_MASK */ |
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2858 |
return s->mask; |
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2859 |
|
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2860 |
case 0x14: /* INTERRUPT_STATUS */ |
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2861 |
return s->ints; |
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2862 |
|
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2863 |
case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
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2864 |
OMAP_BAD_REG(addr); |
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2865 |
return s->pins; |
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2866 |
} |
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2867 |
|
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2868 |
OMAP_BAD_REG(addr); |
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2869 |
return 0; |
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2870 |
} |
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2871 |
|
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2872 |
static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
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2873 |
uint32_t value) |
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2874 |
{ |
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2875 |
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
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2876 |
int offset = addr & OMAP_MPUI_REG_MASK; |
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2877 |
uint16_t diff; |
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2878 |
int ln; |
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2879 |
|
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2880 |
switch (offset) { |
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2881 |
case 0x00: /* DATA_INPUT */ |
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2882 |
OMAP_RO_REG(addr); |
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2883 |
return; |
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2884 |
|
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2885 |
case 0x04: /* DATA_OUTPUT */ |
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2886 |
diff = (s->outputs ^ value) & ~s->dir; |
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2887 |
s->outputs = value; |
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2888 |
while ((ln = ffs(diff))) { |
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2889 |
ln --; |
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2890 |
if (s->handler[ln]) |
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2891 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
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2892 |
diff &= ~(1 << ln); |
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2893 |
} |
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2894 |
break; |
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2895 |
|
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2896 |
case 0x08: /* DIRECTION_CONTROL */ |
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2897 |
diff = s->outputs & (s->dir ^ value); |
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2898 |
s->dir = value; |
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2899 |
|
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2900 |
value = s->outputs & ~s->dir; |
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2901 |
while ((ln = ffs(diff))) { |
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2902 |
ln --; |
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2903 |
if (s->handler[ln]) |
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2904 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
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2905 |
diff &= ~(1 << ln); |
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2906 |
} |
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2907 |
break; |
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2908 |
|
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2909 |
case 0x0c: /* INTERRUPT_CONTROL */ |
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2910 |
s->edge = value; |
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2911 |
break; |
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2912 |
|
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2913 |
case 0x10: /* INTERRUPT_MASK */ |
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2914 |
s->mask = value; |
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2915 |
break; |
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2916 |
|
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2917 |
case 0x14: /* INTERRUPT_STATUS */ |
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2918 |
s->ints &= ~value; |
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2919 |
if (!s->ints) |
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2920 |
qemu_irq_lower(s->irq); |
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2921 |
break; |
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2922 |
|
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2923 |
case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
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2924 |
OMAP_BAD_REG(addr); |
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2925 |
s->pins = value; |
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2926 |
break; |
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2927 |
|
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2928 |
default: |
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2929 |
OMAP_BAD_REG(addr); |
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2930 |
return; |
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2931 |
} |
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2932 |
} |
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2933 |
|
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2934 |
/* *Some* sources say the memory region is 32-bit. */ |
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2935 |
static CPUReadMemoryFunc * const omap_gpio_readfn[] = { |
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2936 |
omap_badwidth_read16, |
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2937 |
omap_gpio_read, |
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2938 |
omap_badwidth_read16, |
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2939 |
}; |
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2940 |
|
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2941 |
static CPUWriteMemoryFunc * const omap_gpio_writefn[] = { |
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2942 |
omap_badwidth_write16, |
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2943 |
omap_gpio_write, |
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2944 |
omap_badwidth_write16, |
|
2945 |
}; |
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2946 |
|
|
2947 |
static void omap_gpio_reset(struct omap_gpio_s *s) |
|
2948 |
{ |
|
2949 |
s->inputs = 0; |
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2950 |
s->outputs = ~0; |
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2951 |
s->dir = ~0; |
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2952 |
s->edge = ~0; |
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2953 |
s->mask = ~0; |
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2954 |
s->ints = 0; |
|
2955 |
s->pins = ~0; |
|
2956 |
} |
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2957 |
|
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2958 |
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, |
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2959 |
qemu_irq irq, omap_clk clk) |
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2960 |
{ |
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2961 |
int iomemtype; |
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2962 |
struct omap_gpio_s *s = (struct omap_gpio_s *) |
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2963 |
qemu_mallocz(sizeof(struct omap_gpio_s)); |
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2964 |
|
|
2965 |
s->irq = irq; |
|
2966 |
s->in = qemu_allocate_irqs(omap_gpio_set, s, 16); |
|
2967 |
omap_gpio_reset(s); |
|
2968 |
|
|
2969 |
iomemtype = cpu_register_io_memory(omap_gpio_readfn, |
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2970 |
omap_gpio_writefn, s); |
|
2971 |
cpu_register_physical_memory(base, 0x1000, iomemtype); |
|
2972 |
|
|
2973 |
return s; |
|
2974 |
} |
|
2975 |
|
|
2976 |
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s) |
|
2977 |
{ |
|
2978 |
return s->in; |
|
2979 |
} |
|
2980 |
|
|
2981 |
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
|
2982 |
{ |
|
2983 |
if (line >= 16 || line < 0) |
|
2984 |
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); |
|
2985 |
s->handler[line] = handler; |
|
2986 |
} |
|
2987 |
|
|
2988 | 2807 |
/* MicroWire Interface */ |
2989 | 2808 |
struct omap_uwire_s { |
2990 | 2809 |
qemu_irq txirq; |
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