Revision e616a7e8
b/hw/grackle_pci.c | ||
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115 | 115 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
116 | 116 |
d->config[0x0e] = 0x00; // header_type |
117 | 117 |
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118 |
d->config[0x18] = 0x00; // primary_bus |
|
119 |
d->config[0x19] = 0x01; // secondary_bus |
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120 |
d->config[0x1a] = 0x00; // subordinate_bus |
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121 |
d->config[0x1c] = 0x00; |
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122 |
d->config[0x1d] = 0x00; |
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123 |
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124 |
d->config[0x20] = 0x00; // memory_base |
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125 |
d->config[0x21] = 0x00; |
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126 |
d->config[0x22] = 0x01; // memory_limit |
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127 |
d->config[0x23] = 0x00; |
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128 |
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129 |
d->config[0x24] = 0x00; // prefetchable_memory_base |
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130 |
d->config[0x25] = 0x00; |
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131 |
d->config[0x26] = 0x00; // prefetchable_memory_limit |
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132 |
d->config[0x27] = 0x00; |
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133 |
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134 | 118 |
#if 0 |
135 | 119 |
/* PCI2PCI bridge same values as PearPC - check this */ |
136 | 120 |
d->config[0x00] = 0x11; // vendor_id |
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