Archipelago » qemu

OBJS+= etraxfs_pic.o

OBJS+= ptimer.o

OBJS+= pflash_cfi01.o

#include "flash.h"

extern qemu_irq *etraxfs_pic_init(CPUState *env, target_ulong base);

/* TODO: Make these blocks relocate:able.  */

    qemu_irq *pic;

    int flash_size = 0x800000;

    int index;

    ram_addr_t phys_flash;

    ram_addr_t phys_ram;

    phys_ram = qemu_ram_alloc(ram_size);

    cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);

    /* Unached mapping.  */

    cpu_register_physical_memory(0xc0000000, ram_size, phys_ram | IO_MEM_RAM);

    phys_flash = qemu_ram_alloc(flash_size);

    cpu_register_physical_memory(0,flash_size, IO_MEM_ROM);

    cpu_register_physical_memory(0x80000000, flash_size, IO_MEM_ROM);

    cpu_register_physical_memory(0x04000000, flash_size, IO_MEM_ROM);

    cpu_register_physical_memory(0x84000000, flash_size, 

				 0x04000000 | IO_MEM_ROM);

    index = drive_get_index(IF_PFLASH, 0, 0);

    pflash_cfi01_register(0x80000000, flash_size,

			  drives_table[index].bdrv, 65536, flash_size >> 16,

			  4, 0x0000, 0x0000, 0x0000, 0x0000);

    index = drive_get_index(IF_PFLASH, 0, 1);

    pflash_cfi01_register(0x84000000, flash_size,

			  drives_table[index].bdrv, 65536, flash_size >> 16,

			  4, 0x0000, 0x0000, 0x0000, 0x0000);

    pic = etraxfs_pic_init(env, 0xb001c000);

    etraxfs_timer_init(env, pic);

    etraxfs_ser_init(env, pic);

/*

 * QEMU ETRAX Interrupt Controller.

 *

 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include <stdio.h>

#include "hw.h"

#define D(x)

struct fs_pic_state_t

{

	CPUState *env;

	target_ulong base;

	uint32_t rw_mask;

	/* Active interrupt lines.  */

	uint32_t r_vect;

	/* Active lines, gated through the mask.  */

	uint32_t r_masked_vect;

	uint32_t r_nmi;

	uint32_t r_guru;

};

static uint32_t pic_readb (void *opaque, target_phys_addr_t addr)

{

	return 0;

}

static uint32_t pic_readw (void *opaque, target_phys_addr_t addr)

{

	return 0;

}

static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)

{

	struct fs_pic_state_t *fs = opaque;

	uint32_t rval;

	/* Transform this to a relative addr.  */

	addr -= fs->base;

	switch (addr)

	{

		case 0x0: 

			rval = fs->rw_mask;

			break;

		case 0x4: 

			rval = fs->r_vect;

			break;

		case 0x8: 

			rval = fs->r_masked_vect;

			break;

		case 0xc: 

			rval = fs->r_nmi;

			break;

		case 0x10: 

			rval = fs->r_guru;

			break;

		default:

			cpu_abort(fs->env, "invalid PIC register.\n");

			break;

	}

	D(printf("%s %x=%x\n", __func__, addr, rval));

	return rval;

}

static void

pic_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)

{

}

static void

pic_writew (void *opaque, target_phys_addr_t addr, uint32_t value)

{

}

static void

pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)

{

	struct fs_pic_state_t *fs = opaque;

	D(printf("%s addr=%x val=%x\n", __func__, addr, value));

	/* Transform this to a relative addr.  */

	addr -= fs->base;

	switch (addr) 

	{

		case 0x0: 

			fs->rw_mask = value;

			break;

		case 0x4: 

			fs->r_vect = value;

			break;

		case 0x8: 

			fs->r_masked_vect = value;

			break;

		case 0xc: 

			fs->r_nmi = value;

			break;

		case 0x10: 

			fs->r_guru = value;

			break;

		default:

			cpu_abort(fs->env, "invalid PIC register.\n");

			break;

	}

}

static CPUReadMemoryFunc *pic_read[] = {

	&pic_readb,

	&pic_readw,

	&pic_readl,

};

static CPUWriteMemoryFunc *pic_write[] = {

	&pic_writeb,

	&pic_writew,

	&pic_writel,

};

void pic_info(void)

{

}

void irq_info(void)

{

}

static void etraxfs_pic_handler(void *opaque, int irq, int level)

{	

	struct fs_pic_state_t *fs = (void *)opaque;

	CPUState *env = fs->env;

	int i;

	uint32_t vector = 0;

	D(printf("%s irq=%d level=%d mask=%x v=%x mv=%x\n", 

		 __func__, irq, level,

		 fs->rw_mask, fs->r_vect, fs->r_masked_vect));

	fs->r_vect &= ~(1 << irq);

	fs->r_vect |= (!!level << irq);

	fs->r_masked_vect = fs->r_vect & fs->rw_mask;

	/* The ETRAX interrupt controller signals interrupts to teh core

	   through an interrupt request wire and an irq vector bus. If 

	   multiple interrupts are simultaneously active it chooses vector 

	   0x30 and lets the sw choose the priorities.  */

	if (fs->r_masked_vect) {

		uint32_t mv = fs->r_masked_vect;

		for (i = 0; i < 31; i++) {

			if (mv & 1) {

				vector = 0x31 + i;

				/* Check for multiple interrupts.  */

				if (mv > 1)

					vector = 0x30;

				break;

			}

			mv >>= 1;

		}

		if (vector) {

			env->interrupt_vector = vector;

			D(printf("%s vector=%x\n", __func__, vector));

			cpu_interrupt(env, CPU_INTERRUPT_HARD);

		}

	} else {

		env->interrupt_vector = 0;

		cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);

		D(printf("%s reset irqs\n", __func__));

	}

}

qemu_irq *etraxfs_pic_init(CPUState *env, target_ulong base)

{

	struct fs_pic_state_t *fs;

	qemu_irq *pic;

	int intr_vect_regs;

	fs = qemu_mallocz(sizeof *fs);

	if (!fs)

		return NULL;

	fs->env = env;

	pic = qemu_allocate_irqs(etraxfs_pic_handler, fs, 30);

	intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);

	cpu_register_physical_memory(base, 0x14, intr_vect_regs);

	fs->base = base;

	return pic;

}

			D(printf ("%s %x p=%x\n", __func__, addr, env->pc));

			fflush(stdout);

			D(printf ("%s %x %x pc=%x\n",

				  __func__, addr, value, env->pc));

 * QEMU ETRAX Timers

#define RW_WD_CTRL 0xb001e040

	uint32_t rw_intr_mask;

	uint32_t rw_ack_intr;

	uint32_t r_intr;

		r = timer[t].rw_intr_mask;

		r = timer[t].r_intr & timer[t].rw_intr_mask;

		D(printf ("%s %x p=%x\n", __func__, addr, env->pc));

		D(printf ("extern or disabled timer clock?\n"));

	D(printf ("freq_hz=%d limit=%d\n", freq_hz, t->limit));

			D(printf ("limit=%d %d\n", 

				  t->limit, t->limit/t->scale));

	if (!(t->r_intr & t->mask & t->rw_intr_mask))

			timer[t].rw_intr_mask = value;

			break;

		case RW_WD_CTRL:

			D(printf ("RW_WD_CTRL=%x\n", value));

			timer[t].r_intr &= ~value;

	t->r_intr |= t->mask;

	if (t->mask & t->rw_intr_mask) {

		D(printf("%s raise\n", __func__));

	timer[0].irq = irqs + 26;

	timer[1].irq = irqs + 26;

#define D(x)

static void cris_shift_ccs(CPUState *env)

{

	uint32_t ccs;

	/* Apply the ccs shift.  */

	ccs = env->pregs[PR_CCS];

	ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2);

	env->pregs[PR_CCS] = ccs;

}

	int r = -1;

	D(printf ("%s addr=%x pc=%x\n", __func__, address, env->pc));

		env->exception_index = EXCP_MMU_FAULT;

		env->fault_vector = res.bf_vec;

		r = 1;

		prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

		r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);

	D(printf("%s returns %d irqreq=%x addr=%x ismmu=%d\n", 

			__func__, r, env->interrupt_request, 

			address, is_softmmu));

	return r;

	int ex_vec = -1;

	D(fprintf (stderr, "exception index=%d interrupt_req=%d\n",

		 env->exception_index,

		 env->interrupt_request));

			/* These exceptions are genereated by the core itself.

			   ERP should point to the insn following the brk.  */

			ex_vec = env->trap_vector;

		case EXCP_MMU_FAULT:

			/* ERP is already setup by translate-all.c through

			   re-translation of the aborted TB combined with 

			   pc searching.  */

			ex_vec = env->fault_vector;

				/* Vectors below 0x30 are internal

				   exceptions, i.e not interrupt requests

				   from the interrupt controller.  */

				if (env->interrupt_vector < 0x30)

				/* Is the core accepting interrupts?  */

				/* The interrupt controller gives us the

				   vector.  */

				ex_vec = env->interrupt_vector;

				/* Normal interrupts are taken between

				   TB's.  env->pc is valid here.  */

	env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);

	/* Apply the CRIS CCS shift.  */

	cris_shift_ccs(env);

	D(printf ("%s ebp=%x isr=%x vec=%x\n", __func__, ebp, isr, ex_vec));

	D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));

#elif defined(TARGET_CRIS)

    env->pregs[PR_ERP] = gen_opc_pc[j];