Revision e62b5b13 target-cris/helper.c
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#include "exec-all.h" |
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#include "host-utils.h" |
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#define D(x) |
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#if defined(CONFIG_USER_ONLY) |
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void do_interrupt (CPUState *env) |
| ... | ... | |
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#else /* !CONFIG_USER_ONLY */ |
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static void cris_shift_ccs(CPUState *env) |
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{
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uint32_t ccs; |
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/* Apply the ccs shift. */ |
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ccs = env->pregs[PR_CCS]; |
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ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2); |
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env->pregs[PR_CCS] = ccs; |
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} |
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int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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struct cris_mmu_result_t res; |
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int prot, miss; |
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int r = -1; |
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target_ulong phy; |
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D(printf ("%s addr=%x pc=%x\n", __func__, address, env->pc));
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address &= TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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miss = cris_mmu_translate(&res, env, address, rw, mmu_idx); |
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if (miss) |
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{
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/* handle the miss. */
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phy = 0;
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env->exception_index = EXCP_MMU_MISS;
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env->exception_index = EXCP_MMU_FAULT;
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env->fault_vector = res.bf_vec;
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r = 1;
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} |
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else |
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{
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phy = res.phy; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); |
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} |
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return tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); |
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} |
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static void cris_shift_ccs(CPUState *env) |
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{
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uint32_t ccs; |
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/* Apply the ccs shift. */ |
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ccs = env->pregs[PR_CCS]; |
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ccs = (ccs & 0xc0000000) | ((ccs << 12) >> 2); |
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env->pregs[PR_CCS] = ccs; |
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D(printf("%s returns %d irqreq=%x addr=%x ismmu=%d\n",
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__func__, r, env->interrupt_request, |
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address, is_softmmu)); |
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return r; |
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} |
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void do_interrupt(CPUState *env) |
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{
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uint32_t ebp, isr; |
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int irqnum; |
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fflush(NULL); |
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int ex_vec = -1; |
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#if 0 |
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printf ("exception index=%d interrupt_req=%d\n",
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env->exception_index, |
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env->interrupt_request); |
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#endif |
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D(fprintf (stderr, "exception index=%d interrupt_req=%d\n", |
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env->exception_index, |
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env->interrupt_request)); |
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switch (env->exception_index) |
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{
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case EXCP_BREAK: |
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irqnum = env->trapnr;
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ebp = env->pregs[PR_EBP];
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isr = ldl_code(ebp + irqnum * 4);
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/* These exceptions are genereated by the core itself.
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ERP should point to the insn following the brk. */
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ex_vec = env->trap_vector;
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env->pregs[PR_ERP] = env->pc + 2; |
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env->pc = isr; |
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cris_shift_ccs(env); |
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break; |
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case EXCP_MMU_MISS: |
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irqnum = 4; |
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ebp = env->pregs[PR_EBP]; |
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isr = ldl_code(ebp + irqnum * 4); |
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env->pregs[PR_ERP] = env->pc; |
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env->pc = isr; |
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cris_shift_ccs(env); |
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case EXCP_MMU_FAULT: |
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/* ERP is already setup by translate-all.c through |
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re-translation of the aborted TB combined with |
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pc searching. */ |
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ex_vec = env->fault_vector; |
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break; |
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default: |
| ... | ... | |
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/* Maybe the irq was acked by sw before we got a |
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change to take it. */ |
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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if (!env->pending_interrupts) |
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/* Vectors below 0x30 are internal |
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exceptions, i.e not interrupt requests |
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from the interrupt controller. */ |
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if (env->interrupt_vector < 0x30) |
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return; |
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/* Is the core accepting interrupts? */ |
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if (!(env->pregs[PR_CCS] & I_FLAG)) {
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return; |
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} |
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irqnum = 31 - clz32(env->pending_interrupts);
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irqnum += 0x30;
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ebp = env->pregs[PR_EBP];
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isr = ldl_code(ebp + irqnum * 4);
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/* The interrupt controller gives us the |
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vector. */
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ex_vec = env->interrupt_vector;
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/* Normal interrupts are taken between
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TB's. env->pc is valid here. */
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env->pregs[PR_ERP] = env->pc; |
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env->pc = isr; |
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cris_shift_ccs(env); |
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#if 0 |
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printf ("%s ebp=%x %x isr=%x %d"
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" ir=%x pending=%x\n", |
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__func__, |
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ebp, ebp + irqnum * 4, |
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isr, env->exception_index, |
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env->interrupt_request, |
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env->pending_interrupts); |
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#endif |
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} |
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} |
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break; |
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} |
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env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4); |
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/* Apply the CRIS CCS shift. */ |
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cris_shift_ccs(env); |
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D(printf ("%s ebp=%x isr=%x vec=%x\n", __func__, ebp, isr, ex_vec));
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} |
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
| ... | ... | |
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miss = cris_mmu_translate(&res, env, addr, 0, 0); |
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if (!miss) |
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phy = res.phy; |
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D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); |
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return phy; |
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} |
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#endif |
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