Revision e64d7d59 hw/cs4231.c
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/* |
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* In addition to Crystal CS4231 there is a DMA controller on Sparc. |
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*/ |
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#define CS_MAXADDR 0x3f |
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#define CS_SIZE (CS_MAXADDR + 1) |
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#define CS_SIZE 0x40 |
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#define CS_REGS 16 |
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#define CS_DREGS 32 |
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#define CS_MAXDREG (CS_DREGS - 1) |
| ... | ... | |
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CSState *s = opaque; |
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uint32_t saddr, ret; |
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saddr = (addr & CS_MAXADDR) >> 2;
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saddr = addr >> 2;
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switch (saddr) {
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case 1: |
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switch (CS_RAP(s)) {
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| ... | ... | |
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CSState *s = opaque; |
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uint32_t saddr; |
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saddr = (addr & CS_MAXADDR) >> 2;
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saddr = addr >> 2;
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DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
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switch (saddr) {
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case 1: |
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