Revision e64d7d59 hw/fdc.c

b/hw/fdc.c
513 513
    fdctrl_t *fdctrl = opaque;
514 514
    uint32_t retval;
515 515

  
516
    switch (reg & 0x07) {
516
    switch (reg) {
517 517
    case FD_REG_SRA:
518 518
        retval = fdctrl_read_statusA(fdctrl);
519 519
        break;
......
550 550

  
551 551
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
552 552

  
553
    switch (reg & 0x07) {
553
    switch (reg) {
554 554
    case FD_REG_DOR:
555 555
        fdctrl_write_dor(fdctrl, value);
556 556
        break;
......
568 568
    }
569 569
}
570 570

  
571
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
572
{
573
    return fdctrl_read(opaque, reg & 7);
574
}
575

  
576
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
577
{
578
    fdctrl_write(opaque, reg & 7, value);
579
}
580

  
571 581
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
572 582
{
573 583
    return fdctrl_read(opaque, (uint32_t)reg);
......
1896 1906
                                        fdctrl);
1897 1907
        cpu_register_physical_memory(io_base, 0x08, io_mem);
1898 1908
    } else {
1899
        register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
1900
                             fdctrl);
1901
        register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
1902
                             fdctrl);
1903
        register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
1904
                              fdctrl);
1905
        register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
1906
                              fdctrl);
1909
        register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
1910
                             &fdctrl_read_port, fdctrl);
1911
        register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
1912
                             &fdctrl_read_port, fdctrl);
1913
        register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
1914
                              &fdctrl_write_port, fdctrl);
1915
        register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
1916
                              &fdctrl_write_port, fdctrl);
1907 1917
    }
1908 1918

  
1909 1919
    return fdctrl;

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