Revision e677137d

b/Makefile.target
211 211
endif
212 212

  
213 213
ifeq ($(TARGET_BASE_ARCH), arm)
214
LIBOBJS+= op_helper.o helper.o neon_helper.o
214
LIBOBJS+= op_helper.o helper.o neon_helper.o iwmmxt_helper.o
215 215
endif
216 216

  
217 217
ifeq ($(TARGET_BASE_ARCH), sh4)
b/target-arm/helpers.h
431 431
DEF_HELPER_1_2(neon_acge_f32, uint32_t, (uint32_t, uint32_t))
432 432
DEF_HELPER_1_2(neon_acgt_f32, uint32_t, (uint32_t, uint32_t))
433 433

  
434
/* iwmmxt_helper.c */
435
DEF_HELPER_1_2(iwmmxt_maddsq, uint64_t, (uint64_t, uint64_t))
436
DEF_HELPER_1_2(iwmmxt_madduq, uint64_t, (uint64_t, uint64_t))
437
DEF_HELPER_1_2(iwmmxt_sadb, uint64_t, (uint64_t, uint64_t))
438
DEF_HELPER_1_2(iwmmxt_sadw, uint64_t, (uint64_t, uint64_t))
439
DEF_HELPER_1_2(iwmmxt_mulslw, uint64_t, (uint64_t, uint64_t))
440
DEF_HELPER_1_2(iwmmxt_mulshw, uint64_t, (uint64_t, uint64_t))
441
DEF_HELPER_1_2(iwmmxt_mululw, uint64_t, (uint64_t, uint64_t))
442
DEF_HELPER_1_2(iwmmxt_muluhw, uint64_t, (uint64_t, uint64_t))
443
DEF_HELPER_1_2(iwmmxt_macsw, uint64_t, (uint64_t, uint64_t))
444
DEF_HELPER_1_2(iwmmxt_macuw, uint64_t, (uint64_t, uint64_t))
445
DEF_HELPER_1_1(iwmmxt_setpsr_nz, uint32_t, (uint64_t))
446

  
447
#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \
448
DEF_HELPER_1_3(iwmmxt_##name##b, uint64_t, (CPUState *, uint64_t, uint64_t)) \
449
DEF_HELPER_1_3(iwmmxt_##name##w, uint64_t, (CPUState *, uint64_t, uint64_t)) \
450
DEF_HELPER_1_3(iwmmxt_##name##l, uint64_t, (CPUState *, uint64_t, uint64_t)) \
451

  
452
DEF_IWMMXT_HELPER_SIZE_ENV(unpackl)
453
DEF_IWMMXT_HELPER_SIZE_ENV(unpackh)
454

  
455
DEF_HELPER_1_2(iwmmxt_unpacklub, uint64_t, (CPUState *, uint64_t))
456
DEF_HELPER_1_2(iwmmxt_unpackluw, uint64_t, (CPUState *, uint64_t))
457
DEF_HELPER_1_2(iwmmxt_unpacklul, uint64_t, (CPUState *, uint64_t))
458
DEF_HELPER_1_2(iwmmxt_unpackhub, uint64_t, (CPUState *, uint64_t))
459
DEF_HELPER_1_2(iwmmxt_unpackhuw, uint64_t, (CPUState *, uint64_t))
460
DEF_HELPER_1_2(iwmmxt_unpackhul, uint64_t, (CPUState *, uint64_t))
461
DEF_HELPER_1_2(iwmmxt_unpacklsb, uint64_t, (CPUState *, uint64_t))
462
DEF_HELPER_1_2(iwmmxt_unpacklsw, uint64_t, (CPUState *, uint64_t))
463
DEF_HELPER_1_2(iwmmxt_unpacklsl, uint64_t, (CPUState *, uint64_t))
464
DEF_HELPER_1_2(iwmmxt_unpackhsb, uint64_t, (CPUState *, uint64_t))
465
DEF_HELPER_1_2(iwmmxt_unpackhsw, uint64_t, (CPUState *, uint64_t))
466
DEF_HELPER_1_2(iwmmxt_unpackhsl, uint64_t, (CPUState *, uint64_t))
467

  
468
DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq)
469
DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu)
470
DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts)
471

  
472
DEF_IWMMXT_HELPER_SIZE_ENV(mins)
473
DEF_IWMMXT_HELPER_SIZE_ENV(minu)
474
DEF_IWMMXT_HELPER_SIZE_ENV(maxs)
475
DEF_IWMMXT_HELPER_SIZE_ENV(maxu)
476

  
477
DEF_IWMMXT_HELPER_SIZE_ENV(subn)
478
DEF_IWMMXT_HELPER_SIZE_ENV(addn)
479
DEF_IWMMXT_HELPER_SIZE_ENV(subu)
480
DEF_IWMMXT_HELPER_SIZE_ENV(addu)
481
DEF_IWMMXT_HELPER_SIZE_ENV(subs)
482
DEF_IWMMXT_HELPER_SIZE_ENV(adds)
483

  
484
DEF_HELPER_1_3(iwmmxt_avgb0, uint64_t, (CPUState *, uint64_t, uint64_t))
485
DEF_HELPER_1_3(iwmmxt_avgb1, uint64_t, (CPUState *, uint64_t, uint64_t))
486
DEF_HELPER_1_3(iwmmxt_avgw0, uint64_t, (CPUState *, uint64_t, uint64_t))
487
DEF_HELPER_1_3(iwmmxt_avgw1, uint64_t, (CPUState *, uint64_t, uint64_t))
488

  
489
DEF_HELPER_1_2(iwmmxt_msadb, uint64_t, (uint64_t, uint64_t))
490

  
491
DEF_HELPER_1_3(iwmmxt_align, uint64_t, (uint64_t, uint64_t, uint32_t))
492
DEF_HELPER_1_4(iwmmxt_insr, uint64_t, (uint64_t, uint32_t, uint32_t, uint32_t))
493

  
494
DEF_HELPER_1_1(iwmmxt_bcstb, uint64_t, (uint32_t))
495
DEF_HELPER_1_1(iwmmxt_bcstw, uint64_t, (uint32_t))
496
DEF_HELPER_1_1(iwmmxt_bcstl, uint64_t, (uint32_t))
497

  
498
DEF_HELPER_1_1(iwmmxt_addcb, uint64_t, (uint64_t))
499
DEF_HELPER_1_1(iwmmxt_addcw, uint64_t, (uint64_t))
500
DEF_HELPER_1_1(iwmmxt_addcl, uint64_t, (uint64_t))
501

  
502
DEF_HELPER_1_1(iwmmxt_msbb, uint32_t, (uint64_t))
503
DEF_HELPER_1_1(iwmmxt_msbw, uint32_t, (uint64_t))
504
DEF_HELPER_1_1(iwmmxt_msbl, uint32_t, (uint64_t))
505

  
506
DEF_HELPER_1_3(iwmmxt_srlw, uint64_t, (CPUState *, uint64_t, uint32_t))
507
DEF_HELPER_1_3(iwmmxt_srll, uint64_t, (CPUState *, uint64_t, uint32_t))
508
DEF_HELPER_1_3(iwmmxt_srlq, uint64_t, (CPUState *, uint64_t, uint32_t))
509
DEF_HELPER_1_3(iwmmxt_sllw, uint64_t, (CPUState *, uint64_t, uint32_t))
510
DEF_HELPER_1_3(iwmmxt_slll, uint64_t, (CPUState *, uint64_t, uint32_t))
511
DEF_HELPER_1_3(iwmmxt_sllq, uint64_t, (CPUState *, uint64_t, uint32_t))
512
DEF_HELPER_1_3(iwmmxt_sraw, uint64_t, (CPUState *, uint64_t, uint32_t))
513
DEF_HELPER_1_3(iwmmxt_sral, uint64_t, (CPUState *, uint64_t, uint32_t))
514
DEF_HELPER_1_3(iwmmxt_sraq, uint64_t, (CPUState *, uint64_t, uint32_t))
515
DEF_HELPER_1_3(iwmmxt_rorw, uint64_t, (CPUState *, uint64_t, uint32_t))
516
DEF_HELPER_1_3(iwmmxt_rorl, uint64_t, (CPUState *, uint64_t, uint32_t))
517
DEF_HELPER_1_3(iwmmxt_rorq, uint64_t, (CPUState *, uint64_t, uint32_t))
518
DEF_HELPER_1_3(iwmmxt_shufh, uint64_t, (CPUState *, uint64_t, uint32_t))
519

  
520
DEF_HELPER_1_3(iwmmxt_packuw, uint64_t, (CPUState *, uint64_t, uint64_t))
521
DEF_HELPER_1_3(iwmmxt_packul, uint64_t, (CPUState *, uint64_t, uint64_t))
522
DEF_HELPER_1_3(iwmmxt_packuq, uint64_t, (CPUState *, uint64_t, uint64_t))
523
DEF_HELPER_1_3(iwmmxt_packsw, uint64_t, (CPUState *, uint64_t, uint64_t))
524
DEF_HELPER_1_3(iwmmxt_packsl, uint64_t, (CPUState *, uint64_t, uint64_t))
525
DEF_HELPER_1_3(iwmmxt_packsq, uint64_t, (CPUState *, uint64_t, uint64_t))
526

  
527
DEF_HELPER_1_3(iwmmxt_muladdsl, uint64_t, (uint64_t, uint32_t, uint32_t))
528
DEF_HELPER_1_3(iwmmxt_muladdsw, uint64_t, (uint64_t, uint32_t, uint32_t))
529
DEF_HELPER_1_3(iwmmxt_muladdswl, uint64_t, (uint64_t, uint32_t, uint32_t))
530

  
434 531
#undef DEF_HELPER
435 532
#undef DEF_HELPER_0_0
436 533
#undef DEF_HELPER_0_1
b/target-arm/iwmmxt_helper.c
1
/*
2
 * iwMMXt micro operations for XScale.
3
 *
4
 * Copyright (c) 2007 OpenedHand, Ltd.
5
 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6
 * Copyright (c) 2008 CodeSourcery
7
 *
8
 * This library is free software; you can redistribute it and/or
9
 * modify it under the terms of the GNU Lesser General Public
10
 * License as published by the Free Software Foundation; either
11
 * version 2 of the License, or (at your option) any later version.
12
 *
13
 * This library is distributed in the hope that it will be useful,
14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16
 * Lesser General Public License for more details.
17
 *
18
 * You should have received a copy of the GNU Lesser General Public
19
 * License along with this library; if not, write to the Free Software
20
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21
 */
22

  
23
#include <stdlib.h>
24
#include <stdio.h>
25

  
26
#include "cpu.h"
27
#include "exec-all.h"
28
#include "helpers.h"
29

  
30
/* iwMMXt macros extracted from GNU gdb.  */
31

  
32
/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations.  */
33
#define SIMD8_SET( v, n, b)	((v != 0) << ((((b) + 1) * 4) + (n)))
34
#define SIMD16_SET(v, n, h)	((v != 0) << ((((h) + 1) * 8) + (n)))
35
#define SIMD32_SET(v, n, w)	((v != 0) << ((((w) + 1) * 16) + (n)))
36
#define SIMD64_SET(v, n)	((v != 0) << (32 + (n)))
37
/* Flags to pass as "n" above.  */
38
#define SIMD_NBIT	-1
39
#define SIMD_ZBIT	-2
40
#define SIMD_CBIT	-3
41
#define SIMD_VBIT	-4
42
/* Various status bit macros.  */
43
#define NBIT8(x)	((x) & 0x80)
44
#define NBIT16(x)	((x) & 0x8000)
45
#define NBIT32(x)	((x) & 0x80000000)
46
#define NBIT64(x)	((x) & 0x8000000000000000ULL)
47
#define ZBIT8(x)	(((x) & 0xff) == 0)
48
#define ZBIT16(x)	(((x) & 0xffff) == 0)
49
#define ZBIT32(x)	(((x) & 0xffffffff) == 0)
50
#define ZBIT64(x)	(x == 0)
51
/* Sign extension macros.  */
52
#define EXTEND8H(a)	((uint16_t) (int8_t) (a))
53
#define EXTEND8(a)	((uint32_t) (int8_t) (a))
54
#define EXTEND16(a)	((uint32_t) (int16_t) (a))
55
#define EXTEND16S(a)	((int32_t) (int16_t) (a))
56
#define EXTEND32(a)	((uint64_t) (int32_t) (a))
57

  
58
uint64_t HELPER(iwmmxt_maddsq)(uint64_t a, uint64_t b)
59
{
60
    a = ((
61
            EXTEND16S((a >> 0) & 0xffff) * EXTEND16S((b >> 0) & 0xffff) +
62
            EXTEND16S((a >> 16) & 0xffff) * EXTEND16S((b >> 16) & 0xffff)
63
        ) & 0xffffffff) | ((uint64_t) (
64
            EXTEND16S((a >> 32) & 0xffff) * EXTEND16S((b >> 32) & 0xffff) +
65
            EXTEND16S((a >> 48) & 0xffff) * EXTEND16S((b >> 48) & 0xffff)
66
        ) << 32);
67
    return a;
68
}
69

  
70
uint64_t HELPER(iwmmxt_madduq)(uint64_t a, uint64_t b)
71
{
72
    a = ((
73
            ((a >> 0) & 0xffff) * ((b >> 0) & 0xffff) +
74
            ((a >> 16) & 0xffff) * ((b >> 16) & 0xffff)
75
        ) & 0xffffffff) | ((
76
            ((a >> 32) & 0xffff) * ((b >> 32) & 0xffff) +
77
            ((a >> 48) & 0xffff) * ((b >> 48) & 0xffff)
78
        ) << 32);
79
    return a;
80
}
81

  
82
uint64_t HELPER(iwmmxt_sadb)(uint64_t a, uint64_t b)
83
{
84
#define abs(x) (((x) >= 0) ? x : -x)
85
#define SADB(SHR) abs((int) ((a >> SHR) & 0xff) - (int) ((b >> SHR) & 0xff))
86
    return
87
        SADB(0) + SADB(8) + SADB(16) + SADB(24) +
88
        SADB(32) + SADB(40) + SADB(48) + SADB(56);
89
#undef SADB
90
}
91

  
92
uint64_t HELPER(iwmmxt_sadw)(uint64_t a, uint64_t b)
93
{
94
#define SADW(SHR) \
95
    abs((int) ((a >> SHR) & 0xffff) - (int) ((b >> SHR) & 0xffff))
96
    return SADW(0) + SADW(16) + SADW(32) + SADW(48);
97
#undef SADW
98
}
99

  
100
uint64_t HELPER(iwmmxt_mulslw)(uint64_t a, uint64_t b)
101
{
102
#define MULS(SHR) ((uint64_t) ((( \
103
        EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \
104
    ) >> 0) & 0xffff) << SHR)
105
    return MULS(0) | MULS(16) | MULS(32) | MULS(48);
106
#undef MULS
107
}
108

  
109
uint64_t HELPER(iwmmxt_mulshw)(uint64_t a, uint64_t b)
110
{
111
#define MULS(SHR) ((uint64_t) ((( \
112
        EXTEND16S((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff) \
113
    ) >> 16) & 0xffff) << SHR)
114
    return MULS(0) | MULS(16) | MULS(32) | MULS(48);
115
#undef MULS
116
}
117

  
118
uint64_t HELPER(iwmmxt_mululw)(uint64_t a, uint64_t b)
119
{
120
#define MULU(SHR) ((uint64_t) ((( \
121
        ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \
122
    ) >> 0) & 0xffff) << SHR)
123
    return MULU(0) | MULU(16) | MULU(32) | MULU(48);
124
#undef MULU
125
}
126

  
127
uint64_t HELPER(iwmmxt_muluhw)(uint64_t a, uint64_t b)
128
{
129
#define MULU(SHR) ((uint64_t) ((( \
130
        ((a >> SHR) & 0xffff) * ((b >> SHR) & 0xffff) \
131
    ) >> 16) & 0xffff) << SHR)
132
    return MULU(0) | MULU(16) | MULU(32) | MULU(48);
133
#undef MULU
134
}
135

  
136
uint64_t HELPER(iwmmxt_macsw)(uint64_t a, uint64_t b)
137
{
138
#define MACS(SHR) ( \
139
        EXTEND16((a >> SHR) & 0xffff) * EXTEND16S((b >> SHR) & 0xffff))
140
    return (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48));
141
#undef MACS
142
}
143

  
144
uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b)
145
{
146
#define MACU(SHR) ( \
147
        (uint32_t) ((a >> SHR) & 0xffff) * \
148
        (uint32_t) ((b >> SHR) & 0xffff))
149
    return MACU(0) + MACU(16) + MACU(32) + MACU(48);
150
#undef MACU
151
}
152

  
153
#define NZBIT8(x, i) \
154
    SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
155
    SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
156
#define NZBIT16(x, i) \
157
    SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
158
    SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
159
#define NZBIT32(x, i) \
160
    SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
161
    SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
162
#define NZBIT64(x) \
163
    SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
164
    SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
165
#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3)			\
166
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
167
                                                 uint64_t a, uint64_t b) \
168
{								\
169
    a =							        \
170
        (((a >> SH0) & 0xff) << 0) | (((b >> SH0) & 0xff) << 8) |	\
171
        (((a >> SH1) & 0xff) << 16) | (((b >> SH1) & 0xff) << 24) |	\
172
        (((a >> SH2) & 0xff) << 32) | (((b >> SH2) & 0xff) << 40) |	\
173
        (((a >> SH3) & 0xff) << 48) | (((b >> SH3) & 0xff) << 56);	\
174
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
175
        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |		        \
176
        NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |		\
177
        NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |		\
178
        NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);		\
179
    return a;                                                   \
180
}								\
181
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
182
                                        uint64_t a, uint64_t b) \
183
{								\
184
    a =							        \
185
        (((a >> SH0) & 0xffff) << 0) |				\
186
        (((b >> SH0) & 0xffff) << 16) |			        \
187
        (((a >> SH2) & 0xffff) << 32) |			        \
188
        (((b >> SH2) & 0xffff) << 48);				\
189
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
190
        NZBIT8(a >> 0, 0) | NZBIT8(a >> 16, 1) |		\
191
        NZBIT8(a >> 32, 2) | NZBIT8(a >> 48, 3);		\
192
    return a;                                                   \
193
}								\
194
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
195
                                        uint64_t a, uint64_t b) \
196
{								\
197
    a =							        \
198
        (((a >> SH0) & 0xffffffff) << 0) |			\
199
        (((b >> SH0) & 0xffffffff) << 32);			\
200
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
201
        NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);		\
202
    return a;                                                   \
203
}								\
204
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
205
                                                  uint64_t x)   \
206
{								\
207
    x =							        \
208
        (((x >> SH0) & 0xff) << 0) |				\
209
        (((x >> SH1) & 0xff) << 16) |				\
210
        (((x >> SH2) & 0xff) << 32) |				\
211
        (((x >> SH3) & 0xff) << 48);				\
212
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
213
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |		\
214
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);		\
215
    return x;                                                   \
216
}								\
217
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
218
                                                  uint64_t x)   \
219
{								\
220
    x =							        \
221
        (((x >> SH0) & 0xffff) << 0) |				\
222
        (((x >> SH2) & 0xffff) << 32);				\
223
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
224
        NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);		\
225
    return x;                                                   \
226
}								\
227
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUState *env, \
228
                                                  uint64_t x)   \
229
{								\
230
    x = (((x >> SH0) & 0xffffffff) << 0);			\
231
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0);	\
232
    return x;                                                   \
233
}								\
234
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
235
                                                  uint64_t x)   \
236
{								\
237
    x =							        \
238
        ((uint64_t) EXTEND8H((x >> SH0) & 0xff) << 0) |	        \
239
        ((uint64_t) EXTEND8H((x >> SH1) & 0xff) << 16) |	\
240
        ((uint64_t) EXTEND8H((x >> SH2) & 0xff) << 32) |	\
241
        ((uint64_t) EXTEND8H((x >> SH3) & 0xff) << 48);	        \
242
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
243
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |		\
244
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);		\
245
    return x;                                                   \
246
}								\
247
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
248
                                                  uint64_t x)   \
249
{								\
250
    x =							        \
251
        ((uint64_t) EXTEND16((x >> SH0) & 0xffff) << 0) |	\
252
        ((uint64_t) EXTEND16((x >> SH2) & 0xffff) << 32);	\
253
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
254
        NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);		\
255
    return x;                                                   \
256
}								\
257
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUState *env, \
258
                                                  uint64_t x)   \
259
{								\
260
    x = EXTEND32((x >> SH0) & 0xffffffff);			\
261
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0);	\
262
    return x;                                                   \
263
}
264
IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
265
IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
266

  
267
#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O)			\
268
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env,    \
269
                                        uint64_t a, uint64_t b) \
270
{								\
271
    a =							        \
272
        CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) |		\
273
        CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) |		\
274
        CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) |		\
275
        CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff);		\
276
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
277
        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |		        \
278
        NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |		\
279
        NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |		\
280
        NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);		\
281
    return a;                                                   \
282
}								\
283
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env,    \
284
                                        uint64_t a, uint64_t b) \
285
{								\
286
    a = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) |	\
287
        CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff);	\
288
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
289
        NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |		\
290
        NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);		\
291
    return a;                                                   \
292
}								\
293
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUState *env,    \
294
                                        uint64_t a, uint64_t b) \
295
{								\
296
    a = CMP(0, Tl, O, 0xffffffff) |				\
297
        CMP(32, Tl, O, 0xffffffff);				\
298
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
299
        NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);		\
300
    return a;                                                   \
301
}
302
#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \
303
            (TYPE) ((b >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
304
IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==)
305
IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >)
306
IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >)
307
#undef CMP
308
#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \
309
            (TYPE) ((b >> SHR) & MASK)) ? a : b) & ((uint64_t) MASK << SHR))
310
IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <)
311
IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <)
312
IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >)
313
IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >)
314
#undef CMP
315
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \
316
            OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
317
IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)
318
IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)
319
#undef CMP
320
/* TODO Signed- and Unsigned-Saturation */
321
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \
322
            OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
323
IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)
324
IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)
325
IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)
326
IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
327
#undef CMP
328
#undef IWMMXT_OP_CMP
329

  
330
#define AVGB(SHR) ((( \
331
        ((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR)
332
#define IWMMXT_OP_AVGB(r)                                                 \
333
uint64_t HELPER(iwmmxt_avgb##r)(CPUState *env, uint64_t a, uint64_t b)    \
334
{                                                                         \
335
    const int round = r;                                                  \
336
    a = AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) |                         \
337
        AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56);                        \
338
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =                                 \
339
        SIMD8_SET(ZBIT8((a >> 0) & 0xff), SIMD_ZBIT, 0) |                 \
340
        SIMD8_SET(ZBIT8((a >> 8) & 0xff), SIMD_ZBIT, 1) |                 \
341
        SIMD8_SET(ZBIT8((a >> 16) & 0xff), SIMD_ZBIT, 2) |                \
342
        SIMD8_SET(ZBIT8((a >> 24) & 0xff), SIMD_ZBIT, 3) |                \
343
        SIMD8_SET(ZBIT8((a >> 32) & 0xff), SIMD_ZBIT, 4) |                \
344
        SIMD8_SET(ZBIT8((a >> 40) & 0xff), SIMD_ZBIT, 5) |                \
345
        SIMD8_SET(ZBIT8((a >> 48) & 0xff), SIMD_ZBIT, 6) |                \
346
        SIMD8_SET(ZBIT8((a >> 56) & 0xff), SIMD_ZBIT, 7);                 \
347
    return a;                                                             \
348
}
349
IWMMXT_OP_AVGB(0)
350
IWMMXT_OP_AVGB(1)
351
#undef IWMMXT_OP_AVGB
352
#undef AVGB
353

  
354
#define AVGW(SHR) ((( \
355
        ((a >> SHR) & 0xffff) + ((b >> SHR) & 0xffff) + round) >> 1) << SHR)
356
#define IWMMXT_OP_AVGW(r)                                               \
357
uint64_t HELPER(iwmmxt_avgw##r)(CPUState *env, uint64_t a, uint64_t b)  \
358
{                                                                       \
359
    const int round = r;                                                \
360
    a = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48);                       \
361
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =                               \
362
        SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) |           \
363
        SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) |          \
364
        SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) |          \
365
        SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3);           \
366
    return a;                                                           \
367
}
368
IWMMXT_OP_AVGW(0)
369
IWMMXT_OP_AVGW(1)
370
#undef IWMMXT_OP_AVGW
371
#undef AVGW
372

  
373
uint64_t HELPER(iwmmxt_msadb)(uint64_t a, uint64_t b)
374
{
375
    a =  ((((a >> 0 ) & 0xffff) * ((b >> 0) & 0xffff) +
376
           ((a >> 16) & 0xffff) * ((b >> 16) & 0xffff)) & 0xffffffff) |
377
         ((((a >> 32) & 0xffff) * ((b >> 32) & 0xffff) +
378
           ((a >> 48) & 0xffff) * ((b >> 48) & 0xffff)) << 32);
379
    return a;
380
}
381

  
382
uint64_t HELPER(iwmmxt_align)(uint64_t a, uint64_t b, uint32_t n)
383
{
384
    a >>= n << 3;
385
    a |= b << (64 - (n << 3));
386
    return a;
387
}
388

  
389
uint64_t HELPER(iwmmxt_insr)(uint64_t x, uint32_t a, uint32_t b, uint32_t n)
390
{
391
    x &= ~((uint64_t) b << n);
392
    x |= (uint64_t) (a & b) << n;
393
    return x;
394
}
395

  
396
uint32_t HELPER(iwmmxt_setpsr_nz)(uint64_t x)
397
{
398
    return SIMD64_SET((x == 0), SIMD_ZBIT) |
399
           SIMD64_SET((x & (1ULL << 63)), SIMD_NBIT);
400
}
401

  
402
uint64_t HELPER(iwmmxt_bcstb)(uint32_t arg)
403
{
404
    arg &= 0xff;
405
    return
406
        ((uint64_t) arg << 0 ) | ((uint64_t) arg << 8 ) |
407
        ((uint64_t) arg << 16) | ((uint64_t) arg << 24) |
408
        ((uint64_t) arg << 32) | ((uint64_t) arg << 40) |
409
        ((uint64_t) arg << 48) | ((uint64_t) arg << 56);
410
}
411

  
412
uint64_t HELPER(iwmmxt_bcstw)(uint32_t arg)
413
{
414
    arg &= 0xffff;
415
    return
416
        ((uint64_t) arg << 0 ) | ((uint64_t) arg << 16) |
417
        ((uint64_t) arg << 32) | ((uint64_t) arg << 48);
418
}
419

  
420
uint64_t HELPER(iwmmxt_bcstl)(uint32_t arg)
421
{
422
    return arg | ((uint64_t) arg << 32);
423
}
424

  
425
uint64_t HELPER(iwmmxt_addcb)(uint64_t x)
426
{
427
    return
428
        ((x >> 0) & 0xff) + ((x >> 8) & 0xff) +
429
        ((x >> 16) & 0xff) + ((x >> 24) & 0xff) +
430
        ((x >> 32) & 0xff) + ((x >> 40) & 0xff) +
431
        ((x >> 48) & 0xff) + ((x >> 56) & 0xff);
432
}
433

  
434
uint64_t HELPER(iwmmxt_addcw)(uint64_t x)
435
{
436
    return
437
        ((x >> 0) & 0xffff) + ((x >> 16) & 0xffff) +
438
        ((x >> 32) & 0xffff) + ((x >> 48) & 0xffff);
439
}
440

  
441
uint64_t HELPER(iwmmxt_addcl)(uint64_t x)
442
{
443
    return (x & 0xffffffff) + (x >> 32);
444
}
445

  
446
uint32_t HELPER(iwmmxt_msbb)(uint64_t x)
447
{
448
    return
449
        ((x >> 7) & 0x01) | ((x >> 14) & 0x02) |
450
        ((x >> 21) & 0x04) | ((x >> 28) & 0x08) |
451
        ((x >> 35) & 0x10) | ((x >> 42) & 0x20) |
452
        ((x >> 49) & 0x40) | ((x >> 56) & 0x80);
453
}
454

  
455
uint32_t HELPER(iwmmxt_msbw)(uint64_t x)
456
{
457
    return
458
        ((x >> 15) & 0x01) | ((x >> 30) & 0x02) |
459
        ((x >> 45) & 0x04) | ((x >> 52) & 0x08);
460
}
461

  
462
uint32_t HELPER(iwmmxt_msbl)(uint64_t x)
463
{
464
    return ((x >> 31) & 0x01) | ((x >> 62) & 0x02);
465
}
466

  
467
/* FIXME: Split wCASF setting into a separate op to avoid env use.  */
468
uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
469
{
470
    x = (((x & (0xffffll << 0)) >> n) & (0xffffll << 0)) |
471
        (((x & (0xffffll << 16)) >> n) & (0xffffll << 16)) |
472
        (((x & (0xffffll << 32)) >> n) & (0xffffll << 32)) |
473
        (((x & (0xffffll << 48)) >> n) & (0xffffll << 48));
474
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
475
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
476
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
477
    return x;
478
}
479

  
480
uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
481
{
482
    x = ((x & (0xffffffffll << 0)) >> n) |
483
        ((x >> n) & (0xffffffffll << 32));
484
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
485
        NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
486
    return x;
487
}
488

  
489
uint64_t HELPER(iwmmxt_srlq)(CPUState *env, uint64_t x, uint32_t n)
490
{
491
    x >>= n;
492
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
493
    return x;
494
}
495

  
496
uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
497
{
498
    x = (((x & (0xffffll << 0)) << n) & (0xffffll << 0)) |
499
        (((x & (0xffffll << 16)) << n) & (0xffffll << 16)) |
500
        (((x & (0xffffll << 32)) << n) & (0xffffll << 32)) |
501
        (((x & (0xffffll << 48)) << n) & (0xffffll << 48));
502
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
503
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
504
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
505
    return x;
506
}
507

  
508
uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
509
{
510
    x = ((x << n) & (0xffffffffll << 0)) |
511
        ((x & (0xffffffffll << 32)) << n);
512
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
513
        NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
514
    return x;
515
}
516

  
517
uint64_t HELPER(iwmmxt_sllq)(CPUState *env, uint64_t x, uint32_t n)
518
{
519
    x <<= n;
520
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
521
    return x;
522
}
523

  
524
uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
525
{
526
    x = ((uint64_t) ((EXTEND16(x >> 0) >> n) & 0xffff) << 0) |
527
        ((uint64_t) ((EXTEND16(x >> 16) >> n) & 0xffff) << 16) |
528
        ((uint64_t) ((EXTEND16(x >> 32) >> n) & 0xffff) << 32) |
529
        ((uint64_t) ((EXTEND16(x >> 48) >> n) & 0xffff) << 48);
530
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
531
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
532
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
533
    return x;
534
}
535

  
536
uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
537
{
538
    x = (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) |
539
        (((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32);
540
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
541
        NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
542
    return x;
543
}
544

  
545
uint64_t HELPER(iwmmxt_sraq)(CPUState *env, uint64_t x, uint32_t n)
546
{
547
    x = (int64_t) x >> n;
548
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
549
    return x;
550
}
551

  
552
uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
553
{
554
    x = ((((x & (0xffffll << 0)) >> n) |
555
          ((x & (0xffffll << 0)) << (16 - n))) & (0xffffll << 0)) |
556
        ((((x & (0xffffll << 16)) >> n) |
557
          ((x & (0xffffll << 16)) << (16 - n))) & (0xffffll << 16)) |
558
        ((((x & (0xffffll << 32)) >> n) |
559
          ((x & (0xffffll << 32)) << (16 - n))) & (0xffffll << 32)) |
560
        ((((x & (0xffffll << 48)) >> n) |
561
          ((x & (0xffffll << 48)) << (16 - n))) & (0xffffll << 48));
562
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
563
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
564
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
565
    return x;
566
}
567

  
568
uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
569
{
570
    x = ((x & (0xffffffffll << 0)) >> n) |
571
        ((x >> n) & (0xffffffffll << 32)) |
572
        ((x << (32 - n)) & (0xffffffffll << 0)) |
573
        ((x & (0xffffffffll << 32)) << (32 - n));
574
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
575
        NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1);
576
    return x;
577
}
578

  
579
uint64_t HELPER(iwmmxt_rorq)(CPUState *env, uint64_t x, uint32_t n)
580
{
581
    x = (x >> n) | (x << (64 - n));
582
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
583
    return x;
584
}
585

  
586
uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
587
{
588
    x = (((x >> ((n << 4) & 0x30)) & 0xffff) << 0) |
589
        (((x >> ((n << 2) & 0x30)) & 0xffff) << 16) |
590
        (((x >> ((n << 0) & 0x30)) & 0xffff) << 32) |
591
        (((x >> ((n >> 2) & 0x30)) & 0xffff) << 48);
592
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
593
        NZBIT16(x >> 0, 0) | NZBIT16(x >> 16, 1) |
594
        NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3);
595
    return x;
596
}
597

  
598
/* TODO: Unsigned-Saturation */
599
uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
600
{
601
    a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
602
        (((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
603
        (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) |
604
        (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56);
605
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
606
        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |
607
        NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |
608
        NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |
609
        NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);
610
    return a;
611
}
612

  
613
uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
614
{
615
    a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
616
        (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
617
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
618
        NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |
619
        NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);
620
    return a;
621
}
622

  
623
uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
624
{
625
    a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
626
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
627
        NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);
628
    return a;
629
}
630

  
631
/* TODO: Signed-Saturation */
632
uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
633
{
634
    a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
635
        (((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
636
        (((b >> 0) & 0xff) << 32) | (((b >> 16) & 0xff) << 40) |
637
        (((b >> 32) & 0xff) << 48) | (((b >> 48) & 0xff) << 56);
638
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
639
        NZBIT8(a >> 0, 0) | NZBIT8(a >> 8, 1) |
640
        NZBIT8(a >> 16, 2) | NZBIT8(a >> 24, 3) |
641
        NZBIT8(a >> 32, 4) | NZBIT8(a >> 40, 5) |
642
        NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7);
643
    return a;
644
}
645

  
646
uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
647
{
648
    a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
649
        (((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
650
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
651
        NZBIT16(a >> 0, 0) | NZBIT16(a >> 16, 1) |
652
        NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3);
653
    return a;
654
}
655

  
656
uint64_t HELPER(iwmmxt_packsq)(CPUState *env, uint64_t a, uint64_t b)
657
{
658
    a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
659
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
660
        NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1);
661
    return a;
662
}
663

  
664
uint64_t HELPER(iwmmxt_muladdsl)(uint64_t c, uint32_t a, uint32_t b)
665
{
666
    return c + ((int32_t) EXTEND32(a) * (int32_t) EXTEND32(b));
667
}
668

  
669
uint64_t HELPER(iwmmxt_muladdsw)(uint64_t c, uint32_t a, uint32_t b)
670
{
671
    c += EXTEND32(EXTEND16S((a >> 0) & 0xffff) *
672
                  EXTEND16S((b >> 0) & 0xffff));
673
    c += EXTEND32(EXTEND16S((a >> 16) & 0xffff) *
674
                  EXTEND16S((b >> 16) & 0xffff));
675
    return c;
676
}
677

  
678
uint64_t HELPER(iwmmxt_muladdswl)(uint64_t c, uint32_t a, uint32_t b)
679
{
680
    return c + (EXTEND32(EXTEND16S(a & 0xffff) *
681
                         EXTEND16S(b & 0xffff)));
682
}
b/target-arm/neon_helper.c
1
/*
2
 * ARM NEON vector operations.
3
 *
4
 * Copyright (c) 2007, 2008 CodeSourcery.
5
 * Written by Paul Brook
6
 *
7
 * This code is licenced under the GNU GPL v2.
8
 */
1 9
#include <stdlib.h>
2 10
#include <stdio.h>
3 11

  
b/target-arm/op.c
20 20
 */
21 21
#include "exec.h"
22 22

  
23
/* memory access */
24

  
25
#define MEMSUFFIX _raw
26
#include "op_mem.h"
27

  
28
#if !defined(CONFIG_USER_ONLY)
29
#define MEMSUFFIX _user
30
#include "op_mem.h"
31
#define MEMSUFFIX _kernel
32
#include "op_mem.h"
33
#endif
34

  
35
/* iwMMXt support */
36
#include "op_iwmmxt.c"
23
void OPPROTO op_dummy(void)
24
{
25
}
/dev/null
1
/*
2
 * iwMMXt micro operations for XScale.
3
 *
4
 * Copyright (c) 2007 OpenedHand, Ltd.
5
 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6
 *
7
 * This library is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU Lesser General Public
9
 * License as published by the Free Software Foundation; either
10
 * version 2 of the License, or (at your option) any later version.
11
 *
12
 * This library is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
 * Lesser General Public License for more details.
16
 *
17
 * You should have received a copy of the GNU Lesser General Public
18
 * License along with this library; if not, write to the Free Software
19
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20
 */
21

  
22
#define M1	env->iwmmxt.regs[PARAM1]
23

  
24
/* iwMMXt macros extracted from GNU gdb.  */
25

  
26
/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations.  */
27
#define SIMD8_SET( v, n, b)	((v != 0) << ((((b) + 1) * 4) + (n)))
28
#define SIMD16_SET(v, n, h)	((v != 0) << ((((h) + 1) * 8) + (n)))
29
#define SIMD32_SET(v, n, w)	((v != 0) << ((((w) + 1) * 16) + (n)))
30
#define SIMD64_SET(v, n)	((v != 0) << (32 + (n)))
31
/* Flags to pass as "n" above.  */
32
#define SIMD_NBIT	-1
33
#define SIMD_ZBIT	-2
34
#define SIMD_CBIT	-3
35
#define SIMD_VBIT	-4
36
/* Various status bit macros.  */
37
#define NBIT8(x)	((x) & 0x80)
38
#define NBIT16(x)	((x) & 0x8000)
39
#define NBIT32(x)	((x) & 0x80000000)
40
#define NBIT64(x)	((x) & 0x8000000000000000ULL)
41
#define ZBIT8(x)	(((x) & 0xff) == 0)
42
#define ZBIT16(x)	(((x) & 0xffff) == 0)
43
#define ZBIT32(x)	(((x) & 0xffffffff) == 0)
44
#define ZBIT64(x)	(x == 0)
45
/* Sign extension macros.  */
46
#define EXTEND8H(a)	((uint16_t) (int8_t) (a))
47
#define EXTEND8(a)	((uint32_t) (int8_t) (a))
48
#define EXTEND16(a)	((uint32_t) (int16_t) (a))
49
#define EXTEND16S(a)	((int32_t) (int16_t) (a))
50
#define EXTEND32(a)	((uint64_t) (int32_t) (a))
51

  
52
void OPPROTO op_iwmmxt_movl_T0_T1_wRn(void)
53
{
54
    T0 = M1 & ~(uint32_t) 0;
55
    T1 = M1 >> 32;
56
}
57

  
58
void OPPROTO op_iwmmxt_movl_wRn_T0_T1(void)
59
{
60
    M1 = ((uint64_t) T1 << 32) | T0;
61
}
62

  
63
void OPPROTO op_iwmmxt_movq_M0_wRn(void)
64
{
65
    M0 = M1;
66
}
67

  
68
void OPPROTO op_iwmmxt_orq_M0_wRn(void)
69
{
70
    M0 |= M1;
71
}
72

  
73
void OPPROTO op_iwmmxt_andq_M0_wRn(void)
74
{
75
    M0 &= M1;
76
}
77

  
78
void OPPROTO op_iwmmxt_xorq_M0_wRn(void)
79
{
80
    M0 ^= M1;
81
}
82

  
83
void OPPROTO op_iwmmxt_maddsq_M0_wRn(void)
84
{
85
    M0 = ((
86
            EXTEND16S((M0 >> 0) & 0xffff) * EXTEND16S((M1 >> 0) & 0xffff) +
87
            EXTEND16S((M0 >> 16) & 0xffff) * EXTEND16S((M1 >> 16) & 0xffff)
88
        ) & 0xffffffff) | ((uint64_t) (
89
            EXTEND16S((M0 >> 32) & 0xffff) * EXTEND16S((M1 >> 32) & 0xffff) +
90
            EXTEND16S((M0 >> 48) & 0xffff) * EXTEND16S((M1 >> 48) & 0xffff)
91
        ) << 32);
92
}
93

  
94
void OPPROTO op_iwmmxt_madduq_M0_wRn(void)
95
{
96
    M0 = ((
97
            ((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +
98
            ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)
99
        ) & 0xffffffff) | ((
100
            ((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +
101
            ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)
102
        ) << 32);
103
}
104

  
105
void OPPROTO op_iwmmxt_sadb_M0_wRn(void)
106
{
107
#define abs(x) (((x) >= 0) ? x : -x)
108
#define SADB(SHR) abs((int) ((M0 >> SHR) & 0xff) - (int) ((M1 >> SHR) & 0xff))
109
    M0 =
110
        SADB(0) + SADB(8) + SADB(16) + SADB(24) +
111
        SADB(32) + SADB(40) + SADB(48) + SADB(56);
112
#undef SADB
113
}
114

  
115
void OPPROTO op_iwmmxt_sadw_M0_wRn(void)
116
{
117
#define SADW(SHR) \
118
    abs((int) ((M0 >> SHR) & 0xffff) - (int) ((M1 >> SHR) & 0xffff))
119
    M0 = SADW(0) + SADW(16) + SADW(32) + SADW(48);
120
#undef SADW
121
}
122

  
123
void OPPROTO op_iwmmxt_addl_M0_wRn(void)
124
{
125
    M0 += env->iwmmxt.regs[PARAM1] & 0xffffffff;
126
}
127

  
128
void OPPROTO op_iwmmxt_mulsw_M0_wRn(void)
129
{
130
#define MULS(SHR) ((uint64_t) ((( \
131
        EXTEND16S((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff) \
132
    ) >> PARAM2) & 0xffff) << SHR)
133
    M0 = MULS(0) | MULS(16) | MULS(32) | MULS(48);
134
#undef MULS
135
}
136

  
137
void OPPROTO op_iwmmxt_muluw_M0_wRn(void)
138
{
139
#define MULU(SHR) ((uint64_t) ((( \
140
        ((M0 >> SHR) & 0xffff) * ((M1 >> SHR) & 0xffff) \
141
    ) >> PARAM2) & 0xffff) << SHR)
142
    M0 = MULU(0) | MULU(16) | MULU(32) | MULU(48);
143
#undef MULU
144
}
145

  
146
void OPPROTO op_iwmmxt_macsw_M0_wRn(void)
147
{
148
#define MACS(SHR) ( \
149
        EXTEND16((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff))
150
    M0 = (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48));
151
#undef MACS
152
}
153

  
154
void OPPROTO op_iwmmxt_macuw_M0_wRn(void)
155
{
156
#define MACU(SHR) ( \
157
        (uint32_t) ((M0 >> SHR) & 0xffff) * \
158
        (uint32_t) ((M1 >> SHR) & 0xffff))
159
    M0 = MACU(0) + MACU(16) + MACU(32) + MACU(48);
160
#undef MACU
161
}
162

  
163
void OPPROTO op_iwmmxt_addsq_M0_wRn(void)
164
{
165
    M0 = (int64_t) M0 + (int64_t) M1;
166
}
167

  
168
void OPPROTO op_iwmmxt_adduq_M0_wRn(void)
169
{
170
    M0 += M1;
171
}
172

  
173
void OPPROTO op_iwmmxt_movq_wRn_M0(void)
174
{
175
    M1 = M0;
176
}
177

  
178
void OPPROTO op_iwmmxt_movl_wCx_T0(void)
179
{
180
    env->iwmmxt.cregs[PARAM1] = T0;
181
}
182

  
183
void OPPROTO op_iwmmxt_movl_T0_wCx(void)
184
{
185
    T0 = env->iwmmxt.cregs[PARAM1];
186
}
187

  
188
void OPPROTO op_iwmmxt_movl_T1_wCx(void)
189
{
190
    T1 = env->iwmmxt.cregs[PARAM1];
191
}
192

  
193
void OPPROTO op_iwmmxt_set_mup(void)
194
{
195
    env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 2;
196
}
197

  
198
void OPPROTO op_iwmmxt_set_cup(void)
199
{
200
    env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 1;
201
}
202

  
203
void OPPROTO op_iwmmxt_setpsr_nz(void)
204
{
205
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
206
        SIMD64_SET((M0 == 0), SIMD_ZBIT) |
207
        SIMD64_SET((M0 & (1ULL << 63)), SIMD_NBIT);
208
}
209

  
210
void OPPROTO op_iwmmxt_negq_M0(void)
211
{
212
    M0 = ~M0;
213
}
214

  
215
#define NZBIT8(x, i) \
216
    SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
217
    SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
218
#define NZBIT16(x, i) \
219
    SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
220
    SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
221
#define NZBIT32(x, i) \
222
    SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
223
    SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
224
#define NZBIT64(x) \
225
    SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
226
    SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
227
#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3)			\
228
void OPPROTO glue(op_iwmmxt_unpack, glue(S, b_M0_wRn))(void)	\
229
{								\
230
    M0 =							\
231
        (((M0 >> SH0) & 0xff) << 0) | (((M1 >> SH0) & 0xff) << 8) |	\
232
        (((M0 >> SH1) & 0xff) << 16) | (((M1 >> SH1) & 0xff) << 24) |	\
233
        (((M0 >> SH2) & 0xff) << 32) | (((M1 >> SH2) & 0xff) << 40) |	\
234
        (((M0 >> SH3) & 0xff) << 48) | (((M1 >> SH3) & 0xff) << 56);	\
235
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
236
        NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |		\
237
        NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |		\
238
        NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |		\
239
        NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);		\
240
}								\
241
void OPPROTO glue(op_iwmmxt_unpack, glue(S, w_M0_wRn))(void)	\
242
{								\
243
    M0 =							\
244
        (((M0 >> SH0) & 0xffff) << 0) |				\
245
        (((M1 >> SH0) & 0xffff) << 16) |			\
246
        (((M0 >> SH2) & 0xffff) << 32) |			\
247
        (((M1 >> SH2) & 0xffff) << 48);				\
248
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
249
        NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 16, 1) |		\
250
        NZBIT8(M0 >> 32, 2) | NZBIT8(M0 >> 48, 3);		\
251
}								\
252
void OPPROTO glue(op_iwmmxt_unpack, glue(S, l_M0_wRn))(void)	\
253
{								\
254
    M0 =							\
255
        (((M0 >> SH0) & 0xffffffff) << 0) |			\
256
        (((M1 >> SH0) & 0xffffffff) << 32);			\
257
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
258
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);		\
259
}								\
260
void OPPROTO glue(op_iwmmxt_unpack, glue(S, ub_M0))(void)	\
261
{								\
262
    M0 =							\
263
        (((M0 >> SH0) & 0xff) << 0) |				\
264
        (((M0 >> SH1) & 0xff) << 16) |				\
265
        (((M0 >> SH2) & 0xff) << 32) |				\
266
        (((M0 >> SH3) & 0xff) << 48);				\
267
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
268
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |		\
269
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);		\
270
}								\
271
void OPPROTO glue(op_iwmmxt_unpack, glue(S, uw_M0))(void)	\
272
{								\
273
    M0 =							\
274
        (((M0 >> SH0) & 0xffff) << 0) |				\
275
        (((M0 >> SH2) & 0xffff) << 32);				\
276
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
277
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);		\
278
}								\
279
void OPPROTO glue(op_iwmmxt_unpack, glue(S, ul_M0))(void)	\
280
{								\
281
    M0 = (((M0 >> SH0) & 0xffffffff) << 0);			\
282
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0);	\
283
}								\
284
void OPPROTO glue(op_iwmmxt_unpack, glue(S, sb_M0))(void)	\
285
{								\
286
    M0 =							\
287
        ((uint64_t) EXTEND8H((M0 >> SH0) & 0xff) << 0) |	\
288
        ((uint64_t) EXTEND8H((M0 >> SH1) & 0xff) << 16) |	\
289
        ((uint64_t) EXTEND8H((M0 >> SH2) & 0xff) << 32) |	\
290
        ((uint64_t) EXTEND8H((M0 >> SH3) & 0xff) << 48);	\
291
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
292
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |		\
293
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);		\
294
}								\
295
void OPPROTO glue(op_iwmmxt_unpack, glue(S, sw_M0))(void)	\
296
{								\
297
    M0 =							\
298
        ((uint64_t) EXTEND16((M0 >> SH0) & 0xffff) << 0) |	\
299
        ((uint64_t) EXTEND16((M0 >> SH2) & 0xffff) << 32);	\
300
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
301
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);		\
302
}								\
303
void OPPROTO glue(op_iwmmxt_unpack, glue(S, sl_M0))(void)	\
304
{								\
305
    M0 = EXTEND32((M0 >> SH0) & 0xffffffff);			\
306
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0);	\
307
}
308
IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
309
IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
310

  
311
#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O)				\
312
void OPPROTO glue(op_iwmmxt_, glue(SUFF, b_M0_wRn))(void)	\
313
{								\
314
    M0 =							\
315
        CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) |		\
316
        CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) |		\
317
        CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) |		\
318
        CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff);		\
319
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
320
        NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |		\
321
        NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |		\
322
        NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |		\
323
        NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);		\
324
}								\
325
void OPPROTO glue(op_iwmmxt_, glue(SUFF, w_M0_wRn))(void)	\
326
{								\
327
    M0 = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) |	\
328
        CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff);	\
329
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
330
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |		\
331
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);		\
332
}								\
333
void OPPROTO glue(op_iwmmxt_, glue(SUFF, l_M0_wRn))(void)	\
334
{								\
335
    M0 = CMP(0, Tl, O, 0xffffffff) |				\
336
        CMP(32, Tl, O, 0xffffffff);				\
337
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =			\
338
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);		\
339
}
340
#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
341
            (TYPE) ((M1 >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
342
IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==)
343
IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >)
344
IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >)
345
#undef CMP
346
#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
347
            (TYPE) ((M1 >> SHR) & MASK)) ? M0 : M1) & ((uint64_t) MASK << SHR))
348
IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <)
349
IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <)
350
IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >)
351
IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >)
352
#undef CMP
353
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
354
            OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)
355
IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)
356
IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)
357
#undef CMP
358
/* TODO Signed- and Unsigned-Saturation */
359
#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
360
            OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)
361
IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)
362
IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)
363
IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)
364
IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
365
#undef CMP
366
#undef IWMMXT_OP_CMP
367

  
368
void OPPROTO op_iwmmxt_avgb_M0_wRn(void)
369
{
370
#define AVGB(SHR) ((( \
371
        ((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR)
372
    M0 =
373
        AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) |
374
        AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56);
375
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
376
        SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) |
377
        SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) |
378
        SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) |
379
        SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) |
380
        SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) |
381
        SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) |
382
        SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) |
383
        SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7);
384
#undef AVGB
385
}
386

  
387
void OPPROTO op_iwmmxt_avgw_M0_wRn(void)
388
{
389
#define AVGW(SHR) ((( \
390
        ((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR)
391
    M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48);
392
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
393
        SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) |
394
        SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) |
395
        SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) |
396
        SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3);
397
#undef AVGW
398
}
399

  
400
void OPPROTO op_iwmmxt_msadb_M0_wRn(void)
401
{
402
    M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +
403
           ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) |
404
         ((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +
405
           ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32);
406
}
407

  
408
void OPPROTO op_iwmmxt_align_M0_T0_wRn(void)
409
{
410
    M0 >>= T0 << 3;
411
    M0 |= M1 << (64 - (T0 << 3));
412
}
413

  
414
void OPPROTO op_iwmmxt_insr_M0_T0_T1(void)
415
{
416
    M0 &= ~((uint64_t) T1 << PARAM1);
417
    M0 |= (uint64_t) (T0 & T1) << PARAM1;
418
}
419

  
420
void OPPROTO op_iwmmxt_extrsb_T0_M0(void)
421
{
422
    T0 = EXTEND8((M0 >> PARAM1) & 0xff);
423
}
424

  
425
void OPPROTO op_iwmmxt_extrsw_T0_M0(void)
426
{
427
    T0 = EXTEND16((M0 >> PARAM1) & 0xffff);
428
}
429

  
430
void OPPROTO op_iwmmxt_extru_T0_M0_T1(void)
431
{
432
    T0 = (M0 >> PARAM1) & T1;
433
}
434

  
435
void OPPROTO op_iwmmxt_bcstb_M0_T0(void)
436
{
437
    T0 &= 0xff;
438
    M0 =
439
        ((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) |
440
        ((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) |
441
        ((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) |
442
        ((uint64_t) T0 << 48) | ((uint64_t) T0 << 56);
443
}
444

  
445
void OPPROTO op_iwmmxt_bcstw_M0_T0(void)
446
{
447
    T0 &= 0xffff;
448
    M0 =
449
        ((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) |
450
        ((uint64_t) T0 << 32) | ((uint64_t) T0 << 48);
451
}
452

  
453
void OPPROTO op_iwmmxt_bcstl_M0_T0(void)
454
{
455
    M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32);
456
}
457

  
458
void OPPROTO op_iwmmxt_addcb_M0(void)
459
{
460
    M0 =
461
        ((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) +
462
        ((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) +
463
        ((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) +
464
        ((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff);
465
}
466

  
467
void OPPROTO op_iwmmxt_addcw_M0(void)
468
{
469
    M0 =
470
        ((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) +
471
        ((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff);
472
}
473

  
474
void OPPROTO op_iwmmxt_addcl_M0(void)
475
{
476
    M0 = (M0 & 0xffffffff) + (M0 >> 32);
477
}
478

  
479
void OPPROTO op_iwmmxt_msbb_T0_M0(void)
480
{
481
    T0 =
482
        ((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) |
483
        ((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) |
484
        ((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) |
485
        ((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80);
486
}
487

  
488
void OPPROTO op_iwmmxt_msbw_T0_M0(void)
489
{
490
    T0 =
491
        ((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) |
492
        ((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08);
493
}
494

  
495
void OPPROTO op_iwmmxt_msbl_T0_M0(void)
496
{
497
    T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02);
498
}
499

  
500
void OPPROTO op_iwmmxt_srlw_M0_T0(void)
501
{
502
    M0 =
503
        (((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) |
504
        (((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) |
505
        (((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) |
506
        (((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48));
507
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
508
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
509
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
510
}
511

  
512
void OPPROTO op_iwmmxt_srll_M0_T0(void)
513
{
514
    M0 =
515
        ((M0 & (0xffffffffll << 0)) >> T0) |
516
        ((M0 >> T0) & (0xffffffffll << 32));
517
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
518
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
519
}
520

  
521
void OPPROTO op_iwmmxt_srlq_M0_T0(void)
522
{
523
    M0 >>= T0;
524
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
525
}
526

  
527
void OPPROTO op_iwmmxt_sllw_M0_T0(void)
528
{
529
    M0 =
530
        (((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) |
531
        (((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) |
532
        (((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) |
533
        (((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48));
534
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
535
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
536
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
537
}
538

  
539
void OPPROTO op_iwmmxt_slll_M0_T0(void)
540
{
541
    M0 =
542
        ((M0 << T0) & (0xffffffffll << 0)) |
543
        ((M0 & (0xffffffffll << 32)) << T0);
544
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
545
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
546
}
547

  
548
void OPPROTO op_iwmmxt_sllq_M0_T0(void)
549
{
550
    M0 <<= T0;
551
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
552
}
553

  
554
void OPPROTO op_iwmmxt_sraw_M0_T0(void)
555
{
556
    M0 =
557
        ((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) |
558
        ((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) |
559
        ((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) |
560
        ((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48);
561
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
562
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
563
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
564
}
565

  
566
void OPPROTO op_iwmmxt_sral_M0_T0(void)
567
{
568
    M0 =
569
        (((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) |
570
        (((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32);
571
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
572
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
573
}
574

  
575
void OPPROTO op_iwmmxt_sraq_M0_T0(void)
576
{
577
    M0 = (int64_t) M0 >> T0;
578
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
579
}
580

  
581
void OPPROTO op_iwmmxt_rorw_M0_T0(void)
582
{
583
    M0 =
584
        ((((M0 & (0xffffll << 0)) >> T0) |
585
          ((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) |
586
        ((((M0 & (0xffffll << 16)) >> T0) |
587
          ((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) |
588
        ((((M0 & (0xffffll << 32)) >> T0) |
589
          ((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) |
590
        ((((M0 & (0xffffll << 48)) >> T0) |
591
          ((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48));
592
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
593
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
594
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
595
}
596

  
597
void OPPROTO op_iwmmxt_rorl_M0_T0(void)
598
{
599
    M0 =
600
        ((M0 & (0xffffffffll << 0)) >> T0) |
601
        ((M0 >> T0) & (0xffffffffll << 32)) |
602
        ((M0 << (32 - T0)) & (0xffffffffll << 0)) |
603
        ((M0 & (0xffffffffll << 32)) << (32 - T0));
604
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
605
        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
606
}
607

  
608
void OPPROTO op_iwmmxt_rorq_M0_T0(void)
609
{
610
    M0 = (M0 >> T0) | (M0 << (64 - T0));
611
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
612
}
613

  
614
void OPPROTO op_iwmmxt_shufh_M0_T0(void)
615
{
616
    M0 =
617
        (((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) |
618
        (((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) |
619
        (((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) |
620
        (((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48);
621
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
622
        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
623
        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
624
}
625

  
626
/* TODO: Unsigned-Saturation */
627
void OPPROTO op_iwmmxt_packuw_M0_wRn(void)
628
{
629
    M0 =
630
        (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |
631
        (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |
632
        (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |
633
        (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);
634
    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
635
        NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |
636
        NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |
637
        NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |
... This diff was truncated because it exceeds the maximum size that can be displayed.

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