Revision e677137d target-arm/translate.c
b/target-arm/translate.c | ||
---|---|---|
78 | 78 |
|
79 | 79 |
static TCGv cpu_env; |
80 | 80 |
/* We reuse the same 64-bit temporaries for efficiency. */ |
81 |
static TCGv cpu_V0, cpu_V1; |
|
81 |
static TCGv cpu_V0, cpu_V1, cpu_M0;
|
|
82 | 82 |
|
83 | 83 |
/* FIXME: These should be removed. */ |
84 | 84 |
static TCGv cpu_T[2]; |
... | ... | |
456 | 456 |
tcg_gen_xori_i32(t0, t1, ~0); |
457 | 457 |
} |
458 | 458 |
|
459 |
/* FIXME: Implement this natively. */ |
|
460 |
static inline void tcg_gen_neg_i64(TCGv dest, TCGv src) |
|
461 |
{ |
|
462 |
tcg_gen_sub_i64(dest, tcg_const_i64(0), src); |
|
463 |
} |
|
464 |
|
|
459 | 465 |
/* T0 &= ~T1. Clobbers T1. */ |
460 | 466 |
/* FIXME: Implement bic natively. */ |
461 | 467 |
static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1) |
... | ... | |
1234 | 1240 |
|
1235 | 1241 |
#define ARM_CP_RW_BIT (1 << 20) |
1236 | 1242 |
|
1243 |
static inline void iwmmxt_load_reg(TCGv var, int reg) |
|
1244 |
{ |
|
1245 |
tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); |
|
1246 |
} |
|
1247 |
|
|
1248 |
static inline void iwmmxt_store_reg(TCGv var, int reg) |
|
1249 |
{ |
|
1250 |
tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); |
|
1251 |
} |
|
1252 |
|
|
1253 |
static inline void gen_op_iwmmxt_movl_wCx_T0(int reg) |
|
1254 |
{ |
|
1255 |
tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
|
1256 |
} |
|
1257 |
|
|
1258 |
static inline void gen_op_iwmmxt_movl_T0_wCx(int reg) |
|
1259 |
{ |
|
1260 |
tcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
|
1261 |
} |
|
1262 |
|
|
1263 |
static inline void gen_op_iwmmxt_movl_T1_wCx(int reg) |
|
1264 |
{ |
|
1265 |
tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
|
1266 |
} |
|
1267 |
|
|
1268 |
static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) |
|
1269 |
{ |
|
1270 |
iwmmxt_store_reg(cpu_M0, rn); |
|
1271 |
} |
|
1272 |
|
|
1273 |
static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) |
|
1274 |
{ |
|
1275 |
iwmmxt_load_reg(cpu_M0, rn); |
|
1276 |
} |
|
1277 |
|
|
1278 |
static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) |
|
1279 |
{ |
|
1280 |
iwmmxt_load_reg(cpu_V1, rn); |
|
1281 |
tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); |
|
1282 |
} |
|
1283 |
|
|
1284 |
static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) |
|
1285 |
{ |
|
1286 |
iwmmxt_load_reg(cpu_V1, rn); |
|
1287 |
tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); |
|
1288 |
} |
|
1289 |
|
|
1290 |
static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) |
|
1291 |
{ |
|
1292 |
iwmmxt_load_reg(cpu_V1, rn); |
|
1293 |
tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); |
|
1294 |
} |
|
1295 |
|
|
1296 |
#define IWMMXT_OP(name) \ |
|
1297 |
static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ |
|
1298 |
{ \ |
|
1299 |
iwmmxt_load_reg(cpu_V1, rn); \ |
|
1300 |
gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ |
|
1301 |
} |
|
1302 |
|
|
1303 |
#define IWMMXT_OP_ENV(name) \ |
|
1304 |
static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ |
|
1305 |
{ \ |
|
1306 |
iwmmxt_load_reg(cpu_V1, rn); \ |
|
1307 |
gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ |
|
1308 |
} |
|
1309 |
|
|
1310 |
#define IWMMXT_OP_ENV_SIZE(name) \ |
|
1311 |
IWMMXT_OP_ENV(name##b) \ |
|
1312 |
IWMMXT_OP_ENV(name##w) \ |
|
1313 |
IWMMXT_OP_ENV(name##l) |
|
1314 |
|
|
1315 |
#define IWMMXT_OP_ENV1(name) \ |
|
1316 |
static inline void gen_op_iwmmxt_##name##_M0(void) \ |
|
1317 |
{ \ |
|
1318 |
gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ |
|
1319 |
} |
|
1320 |
|
|
1321 |
IWMMXT_OP(maddsq) |
|
1322 |
IWMMXT_OP(madduq) |
|
1323 |
IWMMXT_OP(sadb) |
|
1324 |
IWMMXT_OP(sadw) |
|
1325 |
IWMMXT_OP(mulslw) |
|
1326 |
IWMMXT_OP(mulshw) |
|
1327 |
IWMMXT_OP(mululw) |
|
1328 |
IWMMXT_OP(muluhw) |
|
1329 |
IWMMXT_OP(macsw) |
|
1330 |
IWMMXT_OP(macuw) |
|
1331 |
|
|
1332 |
IWMMXT_OP_ENV_SIZE(unpackl) |
|
1333 |
IWMMXT_OP_ENV_SIZE(unpackh) |
|
1334 |
|
|
1335 |
IWMMXT_OP_ENV1(unpacklub) |
|
1336 |
IWMMXT_OP_ENV1(unpackluw) |
|
1337 |
IWMMXT_OP_ENV1(unpacklul) |
|
1338 |
IWMMXT_OP_ENV1(unpackhub) |
|
1339 |
IWMMXT_OP_ENV1(unpackhuw) |
|
1340 |
IWMMXT_OP_ENV1(unpackhul) |
|
1341 |
IWMMXT_OP_ENV1(unpacklsb) |
|
1342 |
IWMMXT_OP_ENV1(unpacklsw) |
|
1343 |
IWMMXT_OP_ENV1(unpacklsl) |
|
1344 |
IWMMXT_OP_ENV1(unpackhsb) |
|
1345 |
IWMMXT_OP_ENV1(unpackhsw) |
|
1346 |
IWMMXT_OP_ENV1(unpackhsl) |
|
1347 |
|
|
1348 |
IWMMXT_OP_ENV_SIZE(cmpeq) |
|
1349 |
IWMMXT_OP_ENV_SIZE(cmpgtu) |
|
1350 |
IWMMXT_OP_ENV_SIZE(cmpgts) |
|
1351 |
|
|
1352 |
IWMMXT_OP_ENV_SIZE(mins) |
|
1353 |
IWMMXT_OP_ENV_SIZE(minu) |
|
1354 |
IWMMXT_OP_ENV_SIZE(maxs) |
|
1355 |
IWMMXT_OP_ENV_SIZE(maxu) |
|
1356 |
|
|
1357 |
IWMMXT_OP_ENV_SIZE(subn) |
|
1358 |
IWMMXT_OP_ENV_SIZE(addn) |
|
1359 |
IWMMXT_OP_ENV_SIZE(subu) |
|
1360 |
IWMMXT_OP_ENV_SIZE(addu) |
|
1361 |
IWMMXT_OP_ENV_SIZE(subs) |
|
1362 |
IWMMXT_OP_ENV_SIZE(adds) |
|
1363 |
|
|
1364 |
IWMMXT_OP_ENV(avgb0) |
|
1365 |
IWMMXT_OP_ENV(avgb1) |
|
1366 |
IWMMXT_OP_ENV(avgw0) |
|
1367 |
IWMMXT_OP_ENV(avgw1) |
|
1368 |
|
|
1369 |
IWMMXT_OP(msadb) |
|
1370 |
|
|
1371 |
IWMMXT_OP_ENV(packuw) |
|
1372 |
IWMMXT_OP_ENV(packul) |
|
1373 |
IWMMXT_OP_ENV(packuq) |
|
1374 |
IWMMXT_OP_ENV(packsw) |
|
1375 |
IWMMXT_OP_ENV(packsl) |
|
1376 |
IWMMXT_OP_ENV(packsq) |
|
1377 |
|
|
1378 |
static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void) |
|
1379 |
{ |
|
1380 |
gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]); |
|
1381 |
} |
|
1382 |
|
|
1383 |
static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void) |
|
1384 |
{ |
|
1385 |
gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]); |
|
1386 |
} |
|
1387 |
|
|
1388 |
static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void) |
|
1389 |
{ |
|
1390 |
gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]); |
|
1391 |
} |
|
1392 |
|
|
1393 |
static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn) |
|
1394 |
{ |
|
1395 |
iwmmxt_load_reg(cpu_V1, rn); |
|
1396 |
gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, cpu_T[0]); |
|
1397 |
} |
|
1398 |
|
|
1399 |
static inline void gen_op_iwmmxt_insr_M0_T0_T1(int shift) |
|
1400 |
{ |
|
1401 |
TCGv tmp = tcg_const_i32(shift); |
|
1402 |
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1], tmp); |
|
1403 |
} |
|
1404 |
|
|
1405 |
static inline void gen_op_iwmmxt_extrsb_T0_M0(int shift) |
|
1406 |
{ |
|
1407 |
tcg_gen_shri_i64(cpu_M0, cpu_M0, shift); |
|
1408 |
tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0); |
|
1409 |
tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]); |
|
1410 |
} |
|
1411 |
|
|
1412 |
static inline void gen_op_iwmmxt_extrsw_T0_M0(int shift) |
|
1413 |
{ |
|
1414 |
tcg_gen_shri_i64(cpu_M0, cpu_M0, shift); |
|
1415 |
tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0); |
|
1416 |
tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]); |
|
1417 |
} |
|
1418 |
|
|
1419 |
static inline void gen_op_iwmmxt_extru_T0_M0(int shift, uint32_t mask) |
|
1420 |
{ |
|
1421 |
tcg_gen_shri_i64(cpu_M0, cpu_M0, shift); |
|
1422 |
tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0); |
|
1423 |
if (mask != ~0u) |
|
1424 |
tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask); |
|
1425 |
} |
|
1426 |
|
|
1427 |
static void gen_op_iwmmxt_set_mup(void) |
|
1428 |
{ |
|
1429 |
TCGv tmp; |
|
1430 |
tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); |
|
1431 |
tcg_gen_ori_i32(tmp, tmp, 2); |
|
1432 |
store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); |
|
1433 |
} |
|
1434 |
|
|
1435 |
static void gen_op_iwmmxt_set_cup(void) |
|
1436 |
{ |
|
1437 |
TCGv tmp; |
|
1438 |
tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); |
|
1439 |
tcg_gen_ori_i32(tmp, tmp, 1); |
|
1440 |
store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); |
|
1441 |
} |
|
1442 |
|
|
1443 |
static void gen_op_iwmmxt_setpsr_nz(void) |
|
1444 |
{ |
|
1445 |
TCGv tmp = new_tmp(); |
|
1446 |
gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); |
|
1447 |
store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); |
|
1448 |
} |
|
1449 |
|
|
1450 |
static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) |
|
1451 |
{ |
|
1452 |
iwmmxt_load_reg(cpu_V1, rn); |
|
1453 |
tcg_gen_andi_i64(cpu_V1, cpu_V1, 0xffffffffu); |
|
1454 |
tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); |
|
1455 |
} |
|
1456 |
|
|
1457 |
|
|
1458 |
static void gen_iwmmxt_movl_T0_T1_wRn(int rn) |
|
1459 |
{ |
|
1460 |
iwmmxt_load_reg(cpu_V0, rn); |
|
1461 |
tcg_gen_trunc_i64_i32(cpu_T[0], cpu_V0); |
|
1462 |
tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); |
|
1463 |
tcg_gen_trunc_i64_i32(cpu_T[1], cpu_V0); |
|
1464 |
} |
|
1465 |
|
|
1466 |
static void gen_iwmmxt_movl_wRn_T0_T1(int rn) |
|
1467 |
{ |
|
1468 |
tcg_gen_extu_i32_i64(cpu_V0, cpu_T[0]); |
|
1469 |
tcg_gen_extu_i32_i64(cpu_V1, cpu_T[0]); |
|
1470 |
tcg_gen_shli_i64(cpu_V1, cpu_V1, 32); |
|
1471 |
tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
|
1472 |
iwmmxt_store_reg(cpu_V0, rn); |
|
1473 |
} |
|
1474 |
|
|
1237 | 1475 |
static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn) |
1238 | 1476 |
{ |
1239 | 1477 |
int rd; |
... | ... | |
1275 | 1513 |
else |
1276 | 1514 |
gen_op_iwmmxt_movl_T0_wCx(rd); |
1277 | 1515 |
else |
1278 |
gen_op_iwmmxt_movl_T0_T1_wRn(rd);
|
|
1516 |
gen_iwmmxt_movl_T0_T1_wRn(rd); |
|
1279 | 1517 |
|
1280 | 1518 |
gen_op_movl_T1_im(mask); |
1281 | 1519 |
gen_op_andl_T0_T1(); |
... | ... | |
1296 | 1534 |
rdlo = (insn >> 12) & 0xf; |
1297 | 1535 |
rdhi = (insn >> 16) & 0xf; |
1298 | 1536 |
if (insn & ARM_CP_RW_BIT) { /* TMRRC */ |
1299 |
gen_op_iwmmxt_movl_T0_T1_wRn(wrd);
|
|
1537 |
gen_iwmmxt_movl_T0_T1_wRn(wrd); |
|
1300 | 1538 |
gen_movl_reg_T0(s, rdlo); |
1301 | 1539 |
gen_movl_reg_T1(s, rdhi); |
1302 | 1540 |
} else { /* TMCRR */ |
1303 | 1541 |
gen_movl_T0_reg(s, rdlo); |
1304 | 1542 |
gen_movl_T1_reg(s, rdhi); |
1305 |
gen_op_iwmmxt_movl_wRn_T0_T1(wrd);
|
|
1543 |
gen_iwmmxt_movl_wRn_T0_T1(wrd); |
|
1306 | 1544 |
gen_op_iwmmxt_set_mup(); |
1307 | 1545 |
} |
1308 | 1546 |
return 0; |
... | ... | |
1318 | 1556 |
dead_tmp(tmp); |
1319 | 1557 |
gen_op_iwmmxt_movl_wCx_T0(wrd); |
1320 | 1558 |
} else { |
1321 |
if (insn & (1 << 8)) |
|
1322 |
if (insn & (1 << 22)) /* WLDRD */ |
|
1323 |
gen_ldst(iwmmxt_ldq, s); |
|
1324 |
else /* WLDRW wRd */ |
|
1325 |
gen_ldst(iwmmxt_ldl, s); |
|
1326 |
else |
|
1327 |
if (insn & (1 << 22)) /* WLDRH */ |
|
1328 |
gen_ldst(iwmmxt_ldw, s); |
|
1329 |
else /* WLDRB */ |
|
1330 |
gen_ldst(iwmmxt_ldb, s); |
|
1559 |
i = 1; |
|
1560 |
if (insn & (1 << 8)) { |
|
1561 |
if (insn & (1 << 22)) { /* WLDRD */ |
|
1562 |
tcg_gen_qemu_ld64(cpu_M0, cpu_T[1], IS_USER(s)); |
|
1563 |
i = 0; |
|
1564 |
} else { /* WLDRW wRd */ |
|
1565 |
tmp = gen_ld32(cpu_T[1], IS_USER(s)); |
|
1566 |
} |
|
1567 |
} else { |
|
1568 |
if (insn & (1 << 22)) { /* WLDRH */ |
|
1569 |
tmp = gen_ld16u(cpu_T[1], IS_USER(s)); |
|
1570 |
} else { /* WLDRB */ |
|
1571 |
tmp = gen_ld8u(cpu_T[1], IS_USER(s)); |
|
1572 |
} |
|
1573 |
} |
|
1574 |
if (i) { |
|
1575 |
tcg_gen_extu_i32_i64(cpu_M0, tmp); |
|
1576 |
dead_tmp(tmp); |
|
1577 |
} |
|
1331 | 1578 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
1332 | 1579 |
} |
1333 | 1580 |
} else { |
... | ... | |
1338 | 1585 |
gen_st32(tmp, cpu_T[1], IS_USER(s)); |
1339 | 1586 |
} else { |
1340 | 1587 |
gen_op_iwmmxt_movq_M0_wRn(wrd); |
1341 |
if (insn & (1 << 8)) |
|
1342 |
if (insn & (1 << 22)) /* WSTRD */ |
|
1343 |
gen_ldst(iwmmxt_stq, s); |
|
1344 |
else /* WSTRW wRd */ |
|
1345 |
gen_ldst(iwmmxt_stl, s); |
|
1346 |
else |
|
1347 |
if (insn & (1 << 22)) /* WSTRH */ |
|
1348 |
gen_ldst(iwmmxt_ldw, s); |
|
1349 |
else /* WSTRB */ |
|
1350 |
gen_ldst(iwmmxt_stb, s); |
|
1588 |
tmp = new_tmp(); |
|
1589 |
if (insn & (1 << 8)) { |
|
1590 |
if (insn & (1 << 22)) { /* WSTRD */ |
|
1591 |
dead_tmp(tmp); |
|
1592 |
tcg_gen_qemu_st64(cpu_M0, cpu_T[1], IS_USER(s)); |
|
1593 |
} else { /* WSTRW wRd */ |
|
1594 |
tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
|
1595 |
gen_st32(tmp, cpu_T[1], IS_USER(s)); |
|
1596 |
} |
|
1597 |
} else { |
|
1598 |
if (insn & (1 << 22)) { /* WSTRH */ |
|
1599 |
tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
|
1600 |
gen_st16(tmp, cpu_T[1], IS_USER(s)); |
|
1601 |
} else { /* WSTRB */ |
|
1602 |
tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
|
1603 |
gen_st8(tmp, cpu_T[1], IS_USER(s)); |
|
1604 |
} |
|
1605 |
} |
|
1351 | 1606 |
} |
1352 | 1607 |
} |
1353 | 1608 |
return 0; |
... | ... | |
1422 | 1677 |
rd0 = (insn >> 0) & 0xf; |
1423 | 1678 |
rd1 = (insn >> 16) & 0xf; |
1424 | 1679 |
gen_op_iwmmxt_movq_M0_wRn(rd0); |
1425 |
gen_op_iwmmxt_negq_M0();
|
|
1680 |
tcg_gen_neg_i64(cpu_M0, cpu_M0);
|
|
1426 | 1681 |
gen_op_iwmmxt_andq_M0_wRn(rd1); |
1427 | 1682 |
gen_op_iwmmxt_setpsr_nz(); |
1428 | 1683 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
... | ... | |
1515 | 1770 |
rd0 = (insn >> 16) & 0xf; |
1516 | 1771 |
rd1 = (insn >> 0) & 0xf; |
1517 | 1772 |
gen_op_iwmmxt_movq_M0_wRn(rd0); |
1518 |
if (insn & (1 << 21)) |
|
1519 |
gen_op_iwmmxt_mulsw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0); |
|
1520 |
else |
|
1521 |
gen_op_iwmmxt_muluw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0); |
|
1773 |
if (insn & (1 << 21)) { |
|
1774 |
if (insn & (1 << 20)) |
|
1775 |
gen_op_iwmmxt_mulshw_M0_wRn(rd1); |
|
1776 |
else |
|
1777 |
gen_op_iwmmxt_mulslw_M0_wRn(rd1); |
|
1778 |
} else { |
|
1779 |
if (insn & (1 << 20)) |
|
1780 |
gen_op_iwmmxt_muluhw_M0_wRn(rd1); |
|
1781 |
else |
|
1782 |
gen_op_iwmmxt_mululw_M0_wRn(rd1); |
|
1783 |
} |
|
1522 | 1784 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
1523 | 1785 |
gen_op_iwmmxt_set_mup(); |
1524 | 1786 |
break; |
... | ... | |
1532 | 1794 |
else |
1533 | 1795 |
gen_op_iwmmxt_macuw_M0_wRn(rd1); |
1534 | 1796 |
if (!(insn & (1 << 20))) { |
1535 |
if (insn & (1 << 21)) |
|
1536 |
gen_op_iwmmxt_addsq_M0_wRn(wrd); |
|
1537 |
else |
|
1538 |
gen_op_iwmmxt_adduq_M0_wRn(wrd); |
|
1797 |
iwmmxt_load_reg(cpu_V1, wrd); |
|
1798 |
tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); |
|
1539 | 1799 |
} |
1540 | 1800 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
1541 | 1801 |
gen_op_iwmmxt_set_mup(); |
... | ... | |
1567 | 1827 |
rd0 = (insn >> 16) & 0xf; |
1568 | 1828 |
rd1 = (insn >> 0) & 0xf; |
1569 | 1829 |
gen_op_iwmmxt_movq_M0_wRn(rd0); |
1570 |
if (insn & (1 << 22)) |
|
1571 |
gen_op_iwmmxt_avgw_M0_wRn(rd1, (insn >> 20) & 1); |
|
1572 |
else |
|
1573 |
gen_op_iwmmxt_avgb_M0_wRn(rd1, (insn >> 20) & 1); |
|
1830 |
if (insn & (1 << 22)) { |
|
1831 |
if (insn & (1 << 20)) |
|
1832 |
gen_op_iwmmxt_avgw1_M0_wRn(rd1); |
|
1833 |
else |
|
1834 |
gen_op_iwmmxt_avgw0_M0_wRn(rd1); |
|
1835 |
} else { |
|
1836 |
if (insn & (1 << 20)) |
|
1837 |
gen_op_iwmmxt_avgb1_M0_wRn(rd1); |
|
1838 |
else |
|
1839 |
gen_op_iwmmxt_avgb0_M0_wRn(rd1); |
|
1840 |
} |
|
1574 | 1841 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
1575 | 1842 |
gen_op_iwmmxt_set_mup(); |
1576 | 1843 |
gen_op_iwmmxt_set_cup(); |
... | ... | |
1622 | 1889 |
if (insn & 8) |
1623 | 1890 |
gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3); |
1624 | 1891 |
else { |
1625 |
gen_op_movl_T1_im(0xff); |
|
1626 |
gen_op_iwmmxt_extru_T0_M0_T1((insn & 7) << 3); |
|
1892 |
gen_op_iwmmxt_extru_T0_M0((insn & 7) << 3, 0xff); |
|
1627 | 1893 |
} |
1628 | 1894 |
break; |
1629 | 1895 |
case 1: |
1630 | 1896 |
if (insn & 8) |
1631 | 1897 |
gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4); |
1632 | 1898 |
else { |
1633 |
gen_op_movl_T1_im(0xffff); |
|
1634 |
gen_op_iwmmxt_extru_T0_M0_T1((insn & 3) << 4); |
|
1899 |
gen_op_iwmmxt_extru_T0_M0((insn & 3) << 4, 0xffff); |
|
1635 | 1900 |
} |
1636 | 1901 |
break; |
1637 | 1902 |
case 2: |
1638 |
gen_op_movl_T1_im(0xffffffff); |
|
1639 |
gen_op_iwmmxt_extru_T0_M0_T1((insn & 1) << 5); |
|
1903 |
gen_op_iwmmxt_extru_T0_M0((insn & 1) << 5, ~0u); |
|
1640 | 1904 |
break; |
1641 | 1905 |
case 3: |
1642 | 1906 |
return 1; |
... | ... | |
1669 | 1933 |
gen_movl_T0_reg(s, rd); |
1670 | 1934 |
switch ((insn >> 6) & 3) { |
1671 | 1935 |
case 0: |
1672 |
gen_op_iwmmxt_bcstb_M0_T0();
|
|
1936 |
gen_helper_iwmmxt_bcstb(cpu_M0, cpu_T[0]);
|
|
1673 | 1937 |
break; |
1674 | 1938 |
case 1: |
1675 |
gen_op_iwmmxt_bcstw_M0_T0();
|
|
1939 |
gen_helper_iwmmxt_bcstw(cpu_M0, cpu_T[0]);
|
|
1676 | 1940 |
break; |
1677 | 1941 |
case 2: |
1678 |
gen_op_iwmmxt_bcstl_M0_T0();
|
|
1942 |
gen_helper_iwmmxt_bcstl(cpu_M0, cpu_T[0]);
|
|
1679 | 1943 |
break; |
1680 | 1944 |
case 3: |
1681 | 1945 |
return 1; |
... | ... | |
1715 | 1979 |
gen_op_iwmmxt_movq_M0_wRn(rd0); |
1716 | 1980 |
switch ((insn >> 22) & 3) { |
1717 | 1981 |
case 0: |
1718 |
gen_op_iwmmxt_addcb_M0();
|
|
1982 |
gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
|
|
1719 | 1983 |
break; |
1720 | 1984 |
case 1: |
1721 |
gen_op_iwmmxt_addcw_M0();
|
|
1985 |
gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
|
|
1722 | 1986 |
break; |
1723 | 1987 |
case 2: |
1724 |
gen_op_iwmmxt_addcl_M0();
|
|
1988 |
gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
|
|
1725 | 1989 |
break; |
1726 | 1990 |
case 3: |
1727 | 1991 |
return 1; |
... | ... | |
1763 | 2027 |
gen_op_iwmmxt_movq_M0_wRn(rd0); |
1764 | 2028 |
switch ((insn >> 22) & 3) { |
1765 | 2029 |
case 0: |
1766 |
gen_op_iwmmxt_msbb_T0_M0();
|
|
2030 |
gen_helper_iwmmxt_msbb(cpu_T[0], cpu_M0);
|
|
1767 | 2031 |
break; |
1768 | 2032 |
case 1: |
1769 |
gen_op_iwmmxt_msbw_T0_M0();
|
|
2033 |
gen_helper_iwmmxt_msbw(cpu_T[0], cpu_M0);
|
|
1770 | 2034 |
break; |
1771 | 2035 |
case 2: |
1772 |
gen_op_iwmmxt_msbl_T0_M0();
|
|
2036 |
gen_helper_iwmmxt_msbl(cpu_T[0], cpu_M0);
|
|
1773 | 2037 |
break; |
1774 | 2038 |
case 3: |
1775 | 2039 |
return 1; |
... | ... | |
1881 | 2145 |
case 0: |
1882 | 2146 |
return 1; |
1883 | 2147 |
case 1: |
1884 |
gen_op_iwmmxt_srlw_M0_T0();
|
|
2148 |
gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1885 | 2149 |
break; |
1886 | 2150 |
case 2: |
1887 |
gen_op_iwmmxt_srll_M0_T0();
|
|
2151 |
gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1888 | 2152 |
break; |
1889 | 2153 |
case 3: |
1890 |
gen_op_iwmmxt_srlq_M0_T0();
|
|
2154 |
gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1891 | 2155 |
break; |
1892 | 2156 |
} |
1893 | 2157 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
... | ... | |
1905 | 2169 |
case 0: |
1906 | 2170 |
return 1; |
1907 | 2171 |
case 1: |
1908 |
gen_op_iwmmxt_sraw_M0_T0();
|
|
2172 |
gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1909 | 2173 |
break; |
1910 | 2174 |
case 2: |
1911 |
gen_op_iwmmxt_sral_M0_T0();
|
|
2175 |
gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1912 | 2176 |
break; |
1913 | 2177 |
case 3: |
1914 |
gen_op_iwmmxt_sraq_M0_T0();
|
|
2178 |
gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1915 | 2179 |
break; |
1916 | 2180 |
} |
1917 | 2181 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
... | ... | |
1929 | 2193 |
case 0: |
1930 | 2194 |
return 1; |
1931 | 2195 |
case 1: |
1932 |
gen_op_iwmmxt_sllw_M0_T0();
|
|
2196 |
gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1933 | 2197 |
break; |
1934 | 2198 |
case 2: |
1935 |
gen_op_iwmmxt_slll_M0_T0();
|
|
2199 |
gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1936 | 2200 |
break; |
1937 | 2201 |
case 3: |
1938 |
gen_op_iwmmxt_sllq_M0_T0();
|
|
2202 |
gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1939 | 2203 |
break; |
1940 | 2204 |
} |
1941 | 2205 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
... | ... | |
1953 | 2217 |
case 1: |
1954 | 2218 |
if (gen_iwmmxt_shift(insn, 0xf)) |
1955 | 2219 |
return 1; |
1956 |
gen_op_iwmmxt_rorw_M0_T0();
|
|
2220 |
gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1957 | 2221 |
break; |
1958 | 2222 |
case 2: |
1959 | 2223 |
if (gen_iwmmxt_shift(insn, 0x1f)) |
1960 | 2224 |
return 1; |
1961 |
gen_op_iwmmxt_rorl_M0_T0();
|
|
2225 |
gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1962 | 2226 |
break; |
1963 | 2227 |
case 3: |
1964 | 2228 |
if (gen_iwmmxt_shift(insn, 0x3f)) |
1965 | 2229 |
return 1; |
1966 |
gen_op_iwmmxt_rorq_M0_T0();
|
|
2230 |
gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
1967 | 2231 |
break; |
1968 | 2232 |
} |
1969 | 2233 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
... | ... | |
2094 | 2358 |
rd0 = (insn >> 16) & 0xf; |
2095 | 2359 |
gen_op_iwmmxt_movq_M0_wRn(rd0); |
2096 | 2360 |
gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f)); |
2097 |
gen_op_iwmmxt_shufh_M0_T0();
|
|
2361 |
gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, cpu_T[0]);
|
|
2098 | 2362 |
gen_op_iwmmxt_movq_wRn_M0(wrd); |
2099 | 2363 |
gen_op_iwmmxt_set_mup(); |
2100 | 2364 |
gen_op_iwmmxt_set_cup(); |
... | ... | |
2279 | 2543 |
return 1; |
2280 | 2544 |
|
2281 | 2545 |
if (insn & ARM_CP_RW_BIT) { /* MRA */ |
2282 |
gen_op_iwmmxt_movl_T0_T1_wRn(acc);
|
|
2546 |
gen_iwmmxt_movl_T0_T1_wRn(acc); |
|
2283 | 2547 |
gen_movl_reg_T0(s, rdlo); |
2284 | 2548 |
gen_op_movl_T0_im((1 << (40 - 32)) - 1); |
2285 | 2549 |
gen_op_andl_T0_T1(); |
... | ... | |
2287 | 2551 |
} else { /* MAR */ |
2288 | 2552 |
gen_movl_T0_reg(s, rdlo); |
2289 | 2553 |
gen_movl_T1_reg(s, rdhi); |
2290 |
gen_op_iwmmxt_movl_wRn_T0_T1(acc);
|
|
2554 |
gen_iwmmxt_movl_wRn_T0_T1(acc); |
|
2291 | 2555 |
} |
2292 | 2556 |
return 0; |
2293 | 2557 |
} |
... | ... | |
8322 | 8586 |
cpu_F1d = tcg_temp_new(TCG_TYPE_I64); |
8323 | 8587 |
cpu_V0 = cpu_F0d; |
8324 | 8588 |
cpu_V1 = cpu_F1d; |
8589 |
/* FIXME: cpu_M0 can probably be the same as cpu_V0. */ |
|
8590 |
cpu_M0 = tcg_temp_new(TCG_TYPE_I64); |
|
8325 | 8591 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
8326 | 8592 |
lj = -1; |
8327 | 8593 |
/* Reset the conditional execution bits immediately. This avoids |
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