Revision e6afc2f4 target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 248 | 248 |
} else {
|
| 249 | 249 |
tcg_gen_movi_i32(cpu_pc, dest); |
| 250 | 250 |
if (ctx->singlestep_enabled) |
| 251 |
gen_op_debug();
|
|
| 251 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 252 | 252 |
tcg_gen_exit_tb(0); |
| 253 | 253 |
} |
| 254 | 254 |
} |
| ... | ... | |
| 260 | 260 |
delayed jump as immediate jump are conditinal jumps */ |
| 261 | 261 |
tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
| 262 | 262 |
if (ctx->singlestep_enabled) |
| 263 |
gen_op_debug();
|
|
| 263 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 264 | 264 |
tcg_gen_exit_tb(0); |
| 265 | 265 |
} else {
|
| 266 | 266 |
gen_goto_tb(ctx, 0, ctx->delayed_pc); |
| ... | ... | |
| 368 | 368 |
|
| 369 | 369 |
#define CHECK_NOT_DELAY_SLOT \ |
| 370 | 370 |
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ |
| 371 |
{gen_op_raise_slot_illegal_instruction (); ctx->bstate = BS_EXCP; \
|
|
| 371 |
{tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \
|
|
| 372 | 372 |
return;} |
| 373 | 373 |
|
| 374 | 374 |
void _decode_opc(DisasContext * ctx) |
| ... | ... | |
| 400 | 400 |
#if defined(CONFIG_USER_ONLY) |
| 401 | 401 |
assert(0); /* XXXXX */ |
| 402 | 402 |
#else |
| 403 |
gen_op_ldtlb();
|
|
| 403 |
tcg_gen_helper_0_0(helper_ldtlb);
|
|
| 404 | 404 |
#endif |
| 405 | 405 |
return; |
| 406 | 406 |
case 0x002b: /* rte */ |
| ... | ... | |
| 428 | 428 |
return; |
| 429 | 429 |
case 0x001b: /* sleep */ |
| 430 | 430 |
if (ctx->memidx) {
|
| 431 |
gen_op_sleep();
|
|
| 431 |
tcg_gen_helper_0_0(helper_sleep);
|
|
| 432 | 432 |
} else {
|
| 433 |
gen_op_raise_illegal_instruction();
|
|
| 433 |
tcg_gen_helper_0_0(helper_raise_illegal_instruction);
|
|
| 434 | 434 |
ctx->bstate = BS_EXCP; |
| 435 | 435 |
} |
| 436 | 436 |
return; |
| ... | ... | |
| 1060 | 1060 |
gen_op_stb_T0_T1(ctx); |
| 1061 | 1061 |
return; |
| 1062 | 1062 |
case 0xc300: /* trapa #imm */ |
| 1063 |
CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pc, ctx->pc); |
|
| 1064 |
gen_op_trapa(B7_0); |
|
| 1063 |
CHECK_NOT_DELAY_SLOT |
|
| 1064 |
tcg_gen_movi_i32(cpu_pc, ctx->pc); |
|
| 1065 |
tcg_gen_movi_i32(cpu_T[0], B7_0); |
|
| 1066 |
tcg_gen_helper_0_1(helper_trapa, cpu_T[0]); |
|
| 1065 | 1067 |
ctx->bstate = BS_BRANCH; |
| 1066 | 1068 |
return; |
| 1067 | 1069 |
case 0xc800: /* tst #imm,R0 */ |
| ... | ... | |
| 1355 | 1357 |
|
| 1356 | 1358 |
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", |
| 1357 | 1359 |
ctx->opcode, ctx->pc); |
| 1358 |
gen_op_raise_illegal_instruction();
|
|
| 1360 |
tcg_gen_helper_0_0(helper_raise_illegal_instruction);
|
|
| 1359 | 1361 |
ctx->bstate = BS_EXCP; |
| 1360 | 1362 |
} |
| 1361 | 1363 |
|
| ... | ... | |
| 1434 | 1436 |
if (ctx.pc == env->breakpoints[i]) {
|
| 1435 | 1437 |
/* We have hit a breakpoint - make sure PC is up-to-date */ |
| 1436 | 1438 |
tcg_gen_movi_i32(cpu_pc, ctx.pc); |
| 1437 |
gen_op_debug();
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|
| 1439 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 1438 | 1440 |
ctx.bstate = BS_EXCP; |
| 1439 | 1441 |
break; |
| 1440 | 1442 |
} |
| ... | ... | |
| 1475 | 1477 |
if (tb->cflags & CF_LAST_IO) |
| 1476 | 1478 |
gen_io_end(); |
| 1477 | 1479 |
if (env->singlestep_enabled) {
|
| 1478 |
gen_op_debug();
|
|
| 1480 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 1479 | 1481 |
} else {
|
| 1480 | 1482 |
switch (ctx.bstate) {
|
| 1481 | 1483 |
case BS_STOP: |
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