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Revision e6bba2ef

IDe6bba2ef49670167694b227df13fc8461debbcd5

Added by Nathan Froyd over 11 years ago

target-ppc: fix SPE evcmp* instructions

The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position. Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.

Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.

Signed-off-by: Nathan Froyd <>
Signed-off-by: Aurelien Jarno <>

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