root / hw / cirrus_vga.c @ e6e5ad80
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1 | e6e5ad80 | bellard | /*
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2 | e6e5ad80 | bellard | * QEMU Cirrus VGA Emulator.
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3 | e6e5ad80 | bellard | *
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4 | e6e5ad80 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | e6e5ad80 | bellard | * Copyright (c) 2004 Suzu
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6 | e6e5ad80 | bellard | *
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7 | e6e5ad80 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | e6e5ad80 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | e6e5ad80 | bellard | * in the Software without restriction, including without limitation the rights
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10 | e6e5ad80 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | e6e5ad80 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | e6e5ad80 | bellard | * furnished to do so, subject to the following conditions:
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13 | e6e5ad80 | bellard | *
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14 | e6e5ad80 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | e6e5ad80 | bellard | * all copies or substantial portions of the Software.
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16 | e6e5ad80 | bellard | *
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17 | e6e5ad80 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | e6e5ad80 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | e6e5ad80 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | e6e5ad80 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | e6e5ad80 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | e6e5ad80 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | e6e5ad80 | bellard | * THE SOFTWARE.
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24 | e6e5ad80 | bellard | */
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25 | e6e5ad80 | bellard | #include "vl.h" |
26 | e6e5ad80 | bellard | #include "vga_int.h" |
27 | e6e5ad80 | bellard | |
28 | e6e5ad80 | bellard | /***************************************
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29 | e6e5ad80 | bellard | *
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30 | e6e5ad80 | bellard | * definitions
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31 | e6e5ad80 | bellard | *
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32 | e6e5ad80 | bellard | ***************************************/
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33 | e6e5ad80 | bellard | |
34 | e6e5ad80 | bellard | #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
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35 | e6e5ad80 | bellard | |
36 | e6e5ad80 | bellard | // ID
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37 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5422 (0x23<<2) |
38 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5426 (0x24<<2) |
39 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5424 (0x25<<2) |
40 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5428 (0x26<<2) |
41 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5430 (0x28<<2) |
42 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5434 (0x2A<<2) |
43 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5446 (0x2E<<2) |
44 | e6e5ad80 | bellard | |
45 | e6e5ad80 | bellard | // sequencer 0x07
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46 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_VGA 0x00 |
47 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_SVGA 0x01 |
48 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_MASK 0x0e |
49 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_8 0x00 |
50 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
51 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_24 0x04 |
52 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16 0x06 |
53 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_32 0x08 |
54 | e6e5ad80 | bellard | #define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
55 | e6e5ad80 | bellard | |
56 | e6e5ad80 | bellard | // sequencer 0x0f
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57 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_512k 0x08 |
58 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_1M 0x10 |
59 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_2M 0x18 |
60 | e6e5ad80 | bellard | #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
61 | e6e5ad80 | bellard | |
62 | e6e5ad80 | bellard | // sequencer 0x12
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63 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_SHOW 0x01 |
64 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_HIDDENPEL 0x02 |
65 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
66 | e6e5ad80 | bellard | |
67 | e6e5ad80 | bellard | // sequencer 0x17
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68 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBFAST 0x10 |
69 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_PCI 0x20 |
70 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
71 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_ISA 0x38 |
72 | e6e5ad80 | bellard | #define CIRRUS_MMIO_ENABLE 0x04 |
73 | e6e5ad80 | bellard | #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
74 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
75 | e6e5ad80 | bellard | |
76 | e6e5ad80 | bellard | // control 0x0b
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77 | e6e5ad80 | bellard | #define CIRRUS_BANKING_DUAL 0x01 |
78 | e6e5ad80 | bellard | #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
79 | e6e5ad80 | bellard | |
80 | e6e5ad80 | bellard | // control 0x30
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81 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_BACKWARDS 0x01 |
82 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
83 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
84 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
85 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
86 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
87 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
88 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
89 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
90 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
91 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
92 | e6e5ad80 | bellard | |
93 | e6e5ad80 | bellard | // control 0x31
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94 | e6e5ad80 | bellard | #define CIRRUS_BLT_BUSY 0x01 |
95 | e6e5ad80 | bellard | #define CIRRUS_BLT_START 0x02 |
96 | e6e5ad80 | bellard | #define CIRRUS_BLT_RESET 0x04 |
97 | e6e5ad80 | bellard | #define CIRRUS_BLT_FIFOUSED 0x10 |
98 | e6e5ad80 | bellard | |
99 | e6e5ad80 | bellard | // control 0x32
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100 | e6e5ad80 | bellard | #define CIRRUS_ROP_0 0x00 |
101 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_DST 0x05 |
102 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOP 0x06 |
103 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
104 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTDST 0x0b |
105 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC 0x0d |
106 | e6e5ad80 | bellard | #define CIRRUS_ROP_1 0x0e |
107 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
108 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_XOR_DST 0x59 |
109 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_DST 0x6d |
110 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
111 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
112 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
113 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC 0xd0 |
114 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
115 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
116 | e6e5ad80 | bellard | |
117 | e6e5ad80 | bellard | // memory-mapped IO
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118 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
119 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
120 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
121 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
122 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
123 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
124 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
125 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
126 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
127 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODE 0x18 // byte |
128 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTROP 0x1a // byte |
129 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
130 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
131 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
132 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
133 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
134 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
135 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
136 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
137 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
138 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
139 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
140 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
141 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
142 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
143 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
144 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
145 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
146 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
147 | e6e5ad80 | bellard | |
148 | e6e5ad80 | bellard | // PCI 0x00: vendor, 0x02: device
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149 | e6e5ad80 | bellard | #define PCI_VENDOR_CIRRUS 0x1013 |
150 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5430 0x00a0 // CLGD5430 or CLGD5440 |
151 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5434 0x00a8 |
152 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5436 0x00ac |
153 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5446 0x00b8 |
154 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5462 0x00d0 |
155 | e6e5ad80 | bellard | #define PCI_DEVICE_CLGD5465 0x00d6 |
156 | e6e5ad80 | bellard | // PCI 0x04: command(word), 0x06(word): status
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157 | e6e5ad80 | bellard | #define PCI_COMMAND_IOACCESS 0x0001 |
158 | e6e5ad80 | bellard | #define PCI_COMMAND_MEMACCESS 0x0002 |
159 | e6e5ad80 | bellard | #define PCI_COMMAND_BUSMASTER 0x0004 |
160 | e6e5ad80 | bellard | #define PCI_COMMAND_SPECIALCYCLE 0x0008 |
161 | e6e5ad80 | bellard | #define PCI_COMMAND_MEMWRITEINVALID 0x0010 |
162 | e6e5ad80 | bellard | #define PCI_COMMAND_PALETTESNOOPING 0x0020 |
163 | e6e5ad80 | bellard | #define PCI_COMMAND_PARITYDETECTION 0x0040 |
164 | e6e5ad80 | bellard | #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080 |
165 | e6e5ad80 | bellard | #define PCI_COMMAND_SERR 0x0100 |
166 | e6e5ad80 | bellard | #define PCI_COMMAND_BACKTOBACKTRANS 0x0200 |
167 | e6e5ad80 | bellard | // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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168 | e6e5ad80 | bellard | #define PCI_CLASS_BASE_DISPLAY 0x03 |
169 | e6e5ad80 | bellard | // PCI 0x08, 0x00ff0000
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170 | e6e5ad80 | bellard | #define PCI_CLASS_SUB_VGA 0x00 |
171 | e6e5ad80 | bellard | // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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172 | e6e5ad80 | bellard | #define PCI_CLASS_HEADERTYPE_00h 0x00 |
173 | e6e5ad80 | bellard | // 0x10-0x3f (headertype 00h)
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174 | e6e5ad80 | bellard | // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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175 | e6e5ad80 | bellard | // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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176 | e6e5ad80 | bellard | #define PCI_MAP_MEM 0x0 |
177 | e6e5ad80 | bellard | #define PCI_MAP_IO 0x1 |
178 | e6e5ad80 | bellard | #define PCI_MAP_MEM_ADDR_MASK (~0xf) |
179 | e6e5ad80 | bellard | #define PCI_MAP_IO_ADDR_MASK (~0x3) |
180 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_32BIT 0x0 |
181 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1 |
182 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_64BIT 0x4 |
183 | e6e5ad80 | bellard | #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8 |
184 | e6e5ad80 | bellard | // PCI 0x28: cardbus CIS pointer
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185 | e6e5ad80 | bellard | // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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186 | e6e5ad80 | bellard | // PCI 0x30: expansion ROM base address
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187 | e6e5ad80 | bellard | #define PCI_ROMBIOS_ENABLED 0x1 |
188 | e6e5ad80 | bellard | // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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189 | e6e5ad80 | bellard | // PCI 0x38: reserved
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190 | e6e5ad80 | bellard | // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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191 | e6e5ad80 | bellard | |
192 | e6e5ad80 | bellard | #define CIRRUS_PNPMMIO_SIZE 0x800 |
193 | e6e5ad80 | bellard | |
194 | e6e5ad80 | bellard | |
195 | e6e5ad80 | bellard | /* I/O and memory hook */
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196 | e6e5ad80 | bellard | #define CIRRUS_HOOK_NOT_HANDLED 0 |
197 | e6e5ad80 | bellard | #define CIRRUS_HOOK_HANDLED 1 |
198 | e6e5ad80 | bellard | |
199 | e6e5ad80 | bellard | typedef void (*cirrus_bitblt_rop_t) (uint8_t * dst, const uint8_t * src, |
200 | e6e5ad80 | bellard | int dstpitch, int srcpitch, |
201 | e6e5ad80 | bellard | int bltwidth, int bltheight); |
202 | e6e5ad80 | bellard | |
203 | e6e5ad80 | bellard | typedef void (*cirrus_bitblt_handler_t) (void *opaque); |
204 | e6e5ad80 | bellard | |
205 | e6e5ad80 | bellard | typedef struct CirrusVGAState { |
206 | e6e5ad80 | bellard | /* XXX: we use the anonymous struct/union gcc 3.x extension */
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207 | e6e5ad80 | bellard | struct VGAState;
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208 | e6e5ad80 | bellard | |
209 | e6e5ad80 | bellard | int cirrus_linear_io_addr;
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210 | e6e5ad80 | bellard | int cirrus_mmio_io_addr;
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211 | e6e5ad80 | bellard | uint32_t cirrus_addr_mask; |
212 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr0; |
213 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr1; |
214 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_lockindex; |
215 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_data; |
216 | e6e5ad80 | bellard | uint32_t cirrus_bank_base[2];
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217 | e6e5ad80 | bellard | uint32_t cirrus_bank_limit[2];
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218 | e6e5ad80 | bellard | uint8_t cirrus_hidden_palette[48];
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219 | e6e5ad80 | bellard | uint32_t cirrus_hw_cursor_x; |
220 | e6e5ad80 | bellard | uint32_t cirrus_hw_cursor_y; |
221 | e6e5ad80 | bellard | int cirrus_blt_pixelwidth;
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222 | e6e5ad80 | bellard | int cirrus_blt_width;
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223 | e6e5ad80 | bellard | int cirrus_blt_height;
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224 | e6e5ad80 | bellard | int cirrus_blt_dstpitch;
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225 | e6e5ad80 | bellard | int cirrus_blt_srcpitch;
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226 | e6e5ad80 | bellard | uint32_t cirrus_blt_dstaddr; |
227 | e6e5ad80 | bellard | uint32_t cirrus_blt_srcaddr; |
228 | e6e5ad80 | bellard | uint8_t cirrus_blt_mode; |
229 | e6e5ad80 | bellard | cirrus_bitblt_rop_t cirrus_rop; |
230 | e6e5ad80 | bellard | #define CIRRUS_BLTBUFSIZE 256 |
231 | e6e5ad80 | bellard | uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
232 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr; |
233 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr_end; |
234 | e6e5ad80 | bellard | uint32_t cirrus_srccounter; |
235 | e6e5ad80 | bellard | uint8_t *cirrus_dstptr; |
236 | e6e5ad80 | bellard | uint8_t *cirrus_dstptr_end; |
237 | e6e5ad80 | bellard | uint32_t cirrus_dstcounter; |
238 | e6e5ad80 | bellard | cirrus_bitblt_handler_t cirrus_blt_handler; |
239 | e6e5ad80 | bellard | int cirrus_blt_horz_counter;
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240 | e6e5ad80 | bellard | } CirrusVGAState; |
241 | e6e5ad80 | bellard | |
242 | e6e5ad80 | bellard | typedef struct PCICirrusVGAState { |
243 | e6e5ad80 | bellard | PCIDevice dev; |
244 | e6e5ad80 | bellard | CirrusVGAState cirrus_vga; |
245 | e6e5ad80 | bellard | } PCICirrusVGAState; |
246 | e6e5ad80 | bellard | |
247 | e6e5ad80 | bellard | /***************************************
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248 | e6e5ad80 | bellard | *
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249 | e6e5ad80 | bellard | * prototypes.
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250 | e6e5ad80 | bellard | *
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251 | e6e5ad80 | bellard | ***************************************/
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252 | e6e5ad80 | bellard | |
253 | e6e5ad80 | bellard | |
254 | e6e5ad80 | bellard | static void cirrus_bitblt_reset(CirrusVGAState * s); |
255 | e6e5ad80 | bellard | |
256 | e6e5ad80 | bellard | /***************************************
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257 | e6e5ad80 | bellard | *
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258 | e6e5ad80 | bellard | * raster operations
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259 | e6e5ad80 | bellard | *
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260 | e6e5ad80 | bellard | ***************************************/
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261 | e6e5ad80 | bellard | |
262 | e6e5ad80 | bellard | #define IMPLEMENT_FORWARD_BITBLT(name,opline) \
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263 | e6e5ad80 | bellard | static void \ |
264 | e6e5ad80 | bellard | cirrus_bitblt_rop_fwd_##name( \ |
265 | e6e5ad80 | bellard | uint8_t *dst,const uint8_t *src, \
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266 | e6e5ad80 | bellard | int dstpitch,int srcpitch, \ |
267 | e6e5ad80 | bellard | int bltwidth,int bltheight) \ |
268 | e6e5ad80 | bellard | { \ |
269 | e6e5ad80 | bellard | int x,y; \
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270 | e6e5ad80 | bellard | dstpitch -= bltwidth; \ |
271 | e6e5ad80 | bellard | srcpitch -= bltwidth; \ |
272 | e6e5ad80 | bellard | for (y = 0; y < bltheight; y++) { \ |
273 | e6e5ad80 | bellard | for (x = 0; x < bltwidth; x++) { \ |
274 | e6e5ad80 | bellard | opline; \ |
275 | e6e5ad80 | bellard | dst++; \ |
276 | e6e5ad80 | bellard | src++; \ |
277 | e6e5ad80 | bellard | } \ |
278 | e6e5ad80 | bellard | dst += dstpitch; \ |
279 | e6e5ad80 | bellard | src += srcpitch; \ |
280 | e6e5ad80 | bellard | } \ |
281 | e6e5ad80 | bellard | } |
282 | e6e5ad80 | bellard | |
283 | e6e5ad80 | bellard | #define IMPLEMENT_BACKWARD_BITBLT(name,opline) \
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284 | e6e5ad80 | bellard | static void \ |
285 | e6e5ad80 | bellard | cirrus_bitblt_rop_bkwd_##name( \ |
286 | e6e5ad80 | bellard | uint8_t *dst,const uint8_t *src, \
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287 | e6e5ad80 | bellard | int dstpitch,int srcpitch, \ |
288 | e6e5ad80 | bellard | int bltwidth,int bltheight) \ |
289 | e6e5ad80 | bellard | { \ |
290 | e6e5ad80 | bellard | int x,y; \
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291 | e6e5ad80 | bellard | dstpitch += bltwidth; \ |
292 | e6e5ad80 | bellard | srcpitch += bltwidth; \ |
293 | e6e5ad80 | bellard | for (y = 0; y < bltheight; y++) { \ |
294 | e6e5ad80 | bellard | for (x = 0; x < bltwidth; x++) { \ |
295 | e6e5ad80 | bellard | opline; \ |
296 | e6e5ad80 | bellard | dst--; \ |
297 | e6e5ad80 | bellard | src--; \ |
298 | e6e5ad80 | bellard | } \ |
299 | e6e5ad80 | bellard | dst += dstpitch; \ |
300 | e6e5ad80 | bellard | src += srcpitch; \ |
301 | e6e5ad80 | bellard | } \ |
302 | e6e5ad80 | bellard | } |
303 | e6e5ad80 | bellard | |
304 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(0, *dst = 0) |
305 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst)) |
306 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(nop, (void) 0) |
307 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst))) |
308 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(notdst, *dst = ~(*dst)) |
309 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src, *dst = *src) |
310 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(1, *dst = 0xff) |
311 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst)) |
312 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst)) |
313 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst)) |
314 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst))) |
315 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst))) |
316 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst))) |
317 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(notsrc, *dst = (~(*src))) |
318 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst)) |
319 | e6e5ad80 | bellard | IMPLEMENT_FORWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst))) |
320 | e6e5ad80 | bellard | |
321 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(0, *dst = 0) |
322 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst)) |
323 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(nop, (void) 0) |
324 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst))) |
325 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(notdst, *dst = ~(*dst)) |
326 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src, *dst = *src) |
327 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(1, *dst = 0xff) |
328 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst)) |
329 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst)) |
330 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst)) |
331 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst))) |
332 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst))) |
333 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst))) |
334 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(notsrc, *dst = (~(*src))) |
335 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst)) |
336 | e6e5ad80 | bellard | IMPLEMENT_BACKWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst))) |
337 | e6e5ad80 | bellard | |
338 | e6e5ad80 | bellard | static cirrus_bitblt_rop_t cirrus_get_fwd_rop_handler(uint8_t rop)
|
339 | e6e5ad80 | bellard | { |
340 | e6e5ad80 | bellard | cirrus_bitblt_rop_t rop_handler = cirrus_bitblt_rop_fwd_nop; |
341 | e6e5ad80 | bellard | |
342 | e6e5ad80 | bellard | switch (rop) {
|
343 | e6e5ad80 | bellard | case CIRRUS_ROP_0:
|
344 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_0; |
345 | e6e5ad80 | bellard | break;
|
346 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_AND_DST:
|
347 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src_and_dst; |
348 | e6e5ad80 | bellard | break;
|
349 | e6e5ad80 | bellard | case CIRRUS_ROP_NOP:
|
350 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_nop; |
351 | e6e5ad80 | bellard | break;
|
352 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_AND_NOTDST:
|
353 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src_and_notdst; |
354 | e6e5ad80 | bellard | break;
|
355 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTDST:
|
356 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_notdst; |
357 | e6e5ad80 | bellard | break;
|
358 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC:
|
359 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src; |
360 | e6e5ad80 | bellard | break;
|
361 | e6e5ad80 | bellard | case CIRRUS_ROP_1:
|
362 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_1; |
363 | e6e5ad80 | bellard | break;
|
364 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_AND_DST:
|
365 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_notsrc_and_dst; |
366 | e6e5ad80 | bellard | break;
|
367 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_XOR_DST:
|
368 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src_xor_dst; |
369 | e6e5ad80 | bellard | break;
|
370 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_OR_DST:
|
371 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src_or_dst; |
372 | e6e5ad80 | bellard | break;
|
373 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_OR_NOTDST:
|
374 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_notsrc_or_notdst; |
375 | e6e5ad80 | bellard | break;
|
376 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_NOTXOR_DST:
|
377 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src_notxor_dst; |
378 | e6e5ad80 | bellard | break;
|
379 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_OR_NOTDST:
|
380 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_src_or_notdst; |
381 | e6e5ad80 | bellard | break;
|
382 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC:
|
383 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_notsrc; |
384 | e6e5ad80 | bellard | break;
|
385 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_OR_DST:
|
386 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_notsrc_or_dst; |
387 | e6e5ad80 | bellard | break;
|
388 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_AND_NOTDST:
|
389 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_fwd_notsrc_and_notdst; |
390 | e6e5ad80 | bellard | break;
|
391 | e6e5ad80 | bellard | default:
|
392 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
393 | e6e5ad80 | bellard | printf("unknown ROP %02x\n", rop);
|
394 | e6e5ad80 | bellard | #endif
|
395 | e6e5ad80 | bellard | break;
|
396 | e6e5ad80 | bellard | } |
397 | e6e5ad80 | bellard | |
398 | e6e5ad80 | bellard | return rop_handler;
|
399 | e6e5ad80 | bellard | } |
400 | e6e5ad80 | bellard | |
401 | e6e5ad80 | bellard | static cirrus_bitblt_rop_t cirrus_get_bkwd_rop_handler(uint8_t rop)
|
402 | e6e5ad80 | bellard | { |
403 | e6e5ad80 | bellard | cirrus_bitblt_rop_t rop_handler = cirrus_bitblt_rop_bkwd_nop; |
404 | e6e5ad80 | bellard | |
405 | e6e5ad80 | bellard | switch (rop) {
|
406 | e6e5ad80 | bellard | case CIRRUS_ROP_0:
|
407 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_0; |
408 | e6e5ad80 | bellard | break;
|
409 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_AND_DST:
|
410 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src_and_dst; |
411 | e6e5ad80 | bellard | break;
|
412 | e6e5ad80 | bellard | case CIRRUS_ROP_NOP:
|
413 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_nop; |
414 | e6e5ad80 | bellard | break;
|
415 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_AND_NOTDST:
|
416 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src_and_notdst; |
417 | e6e5ad80 | bellard | break;
|
418 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTDST:
|
419 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_notdst; |
420 | e6e5ad80 | bellard | break;
|
421 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC:
|
422 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src; |
423 | e6e5ad80 | bellard | break;
|
424 | e6e5ad80 | bellard | case CIRRUS_ROP_1:
|
425 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_1; |
426 | e6e5ad80 | bellard | break;
|
427 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_AND_DST:
|
428 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_notsrc_and_dst; |
429 | e6e5ad80 | bellard | break;
|
430 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_XOR_DST:
|
431 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src_xor_dst; |
432 | e6e5ad80 | bellard | break;
|
433 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_OR_DST:
|
434 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src_or_dst; |
435 | e6e5ad80 | bellard | break;
|
436 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_OR_NOTDST:
|
437 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_notsrc_or_notdst; |
438 | e6e5ad80 | bellard | break;
|
439 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_NOTXOR_DST:
|
440 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src_notxor_dst; |
441 | e6e5ad80 | bellard | break;
|
442 | e6e5ad80 | bellard | case CIRRUS_ROP_SRC_OR_NOTDST:
|
443 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_src_or_notdst; |
444 | e6e5ad80 | bellard | break;
|
445 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC:
|
446 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_notsrc; |
447 | e6e5ad80 | bellard | break;
|
448 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_OR_DST:
|
449 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_notsrc_or_dst; |
450 | e6e5ad80 | bellard | break;
|
451 | e6e5ad80 | bellard | case CIRRUS_ROP_NOTSRC_AND_NOTDST:
|
452 | e6e5ad80 | bellard | rop_handler = cirrus_bitblt_rop_bkwd_notsrc_and_notdst; |
453 | e6e5ad80 | bellard | break;
|
454 | e6e5ad80 | bellard | default:
|
455 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
456 | e6e5ad80 | bellard | printf("unknown ROP %02x\n", rop);
|
457 | e6e5ad80 | bellard | #endif
|
458 | e6e5ad80 | bellard | break;
|
459 | e6e5ad80 | bellard | } |
460 | e6e5ad80 | bellard | |
461 | e6e5ad80 | bellard | return rop_handler;
|
462 | e6e5ad80 | bellard | } |
463 | e6e5ad80 | bellard | |
464 | e6e5ad80 | bellard | /***************************************
|
465 | e6e5ad80 | bellard | *
|
466 | e6e5ad80 | bellard | * color expansion
|
467 | e6e5ad80 | bellard | *
|
468 | e6e5ad80 | bellard | ***************************************/
|
469 | e6e5ad80 | bellard | |
470 | e6e5ad80 | bellard | static void |
471 | e6e5ad80 | bellard | cirrus_colorexpand_8(CirrusVGAState * s, uint8_t * dst, |
472 | e6e5ad80 | bellard | const uint8_t * src, int count) |
473 | e6e5ad80 | bellard | { |
474 | e6e5ad80 | bellard | int x;
|
475 | e6e5ad80 | bellard | uint8_t colors[2];
|
476 | e6e5ad80 | bellard | unsigned bits;
|
477 | e6e5ad80 | bellard | unsigned bitmask;
|
478 | e6e5ad80 | bellard | int srcskipleft = 0; |
479 | e6e5ad80 | bellard | |
480 | e6e5ad80 | bellard | colors[0] = s->gr[0x00]; |
481 | e6e5ad80 | bellard | colors[1] = s->gr[0x01]; |
482 | e6e5ad80 | bellard | |
483 | e6e5ad80 | bellard | bitmask = 0x80 >> srcskipleft;
|
484 | e6e5ad80 | bellard | bits = *src++; |
485 | e6e5ad80 | bellard | for (x = 0; x < count; x++) { |
486 | e6e5ad80 | bellard | if ((bitmask & 0xff) == 0) { |
487 | e6e5ad80 | bellard | bitmask = 0x80;
|
488 | e6e5ad80 | bellard | bits = *src++; |
489 | e6e5ad80 | bellard | } |
490 | e6e5ad80 | bellard | *dst++ = colors[!!(bits & bitmask)]; |
491 | e6e5ad80 | bellard | bitmask >>= 1;
|
492 | e6e5ad80 | bellard | } |
493 | e6e5ad80 | bellard | } |
494 | e6e5ad80 | bellard | |
495 | e6e5ad80 | bellard | static void |
496 | e6e5ad80 | bellard | cirrus_colorexpand_16(CirrusVGAState * s, uint8_t * dst, |
497 | e6e5ad80 | bellard | const uint8_t * src, int count) |
498 | e6e5ad80 | bellard | { |
499 | e6e5ad80 | bellard | int x;
|
500 | e6e5ad80 | bellard | uint8_t colors[2][2]; |
501 | e6e5ad80 | bellard | unsigned bits;
|
502 | e6e5ad80 | bellard | unsigned bitmask;
|
503 | e6e5ad80 | bellard | unsigned index;
|
504 | e6e5ad80 | bellard | int srcskipleft = 0; |
505 | e6e5ad80 | bellard | |
506 | e6e5ad80 | bellard | colors[0][0] = s->gr[0x00]; |
507 | e6e5ad80 | bellard | colors[0][1] = s->gr[0x10]; |
508 | e6e5ad80 | bellard | colors[1][0] = s->gr[0x01]; |
509 | e6e5ad80 | bellard | colors[1][1] = s->gr[0x11]; |
510 | e6e5ad80 | bellard | |
511 | e6e5ad80 | bellard | bitmask = 0x80 >> srcskipleft;
|
512 | e6e5ad80 | bellard | bits = *src++; |
513 | e6e5ad80 | bellard | for (x = 0; x < count; x++) { |
514 | e6e5ad80 | bellard | if ((bitmask & 0xff) == 0) { |
515 | e6e5ad80 | bellard | bitmask = 0x80;
|
516 | e6e5ad80 | bellard | bits = *src++; |
517 | e6e5ad80 | bellard | } |
518 | e6e5ad80 | bellard | index = !!(bits & bitmask); |
519 | e6e5ad80 | bellard | *dst++ = colors[index][0];
|
520 | e6e5ad80 | bellard | *dst++ = colors[index][1];
|
521 | e6e5ad80 | bellard | bitmask >>= 1;
|
522 | e6e5ad80 | bellard | } |
523 | e6e5ad80 | bellard | } |
524 | e6e5ad80 | bellard | |
525 | e6e5ad80 | bellard | static void |
526 | e6e5ad80 | bellard | cirrus_colorexpand_24(CirrusVGAState * s, uint8_t * dst, |
527 | e6e5ad80 | bellard | const uint8_t * src, int count) |
528 | e6e5ad80 | bellard | { |
529 | e6e5ad80 | bellard | int x;
|
530 | e6e5ad80 | bellard | uint8_t colors[2][3]; |
531 | e6e5ad80 | bellard | unsigned bits;
|
532 | e6e5ad80 | bellard | unsigned bitmask;
|
533 | e6e5ad80 | bellard | unsigned index;
|
534 | e6e5ad80 | bellard | int srcskipleft = 0; |
535 | e6e5ad80 | bellard | |
536 | e6e5ad80 | bellard | colors[0][0] = s->gr[0x00]; |
537 | e6e5ad80 | bellard | colors[0][1] = s->gr[0x10]; |
538 | e6e5ad80 | bellard | colors[0][2] = s->gr[0x12]; |
539 | e6e5ad80 | bellard | colors[1][0] = s->gr[0x01]; |
540 | e6e5ad80 | bellard | colors[1][1] = s->gr[0x11]; |
541 | e6e5ad80 | bellard | colors[1][2] = s->gr[0x13]; |
542 | e6e5ad80 | bellard | |
543 | e6e5ad80 | bellard | bitmask = 0x80 << srcskipleft;
|
544 | e6e5ad80 | bellard | bits = *src++; |
545 | e6e5ad80 | bellard | for (x = 0; x < count; x++) { |
546 | e6e5ad80 | bellard | if ((bitmask & 0xff) == 0) { |
547 | e6e5ad80 | bellard | bitmask = 0x80;
|
548 | e6e5ad80 | bellard | bits = *src++; |
549 | e6e5ad80 | bellard | } |
550 | e6e5ad80 | bellard | index = !!(bits & bitmask); |
551 | e6e5ad80 | bellard | *dst++ = colors[index][0];
|
552 | e6e5ad80 | bellard | *dst++ = colors[index][1];
|
553 | e6e5ad80 | bellard | *dst++ = colors[index][2];
|
554 | e6e5ad80 | bellard | bitmask >>= 1;
|
555 | e6e5ad80 | bellard | } |
556 | e6e5ad80 | bellard | } |
557 | e6e5ad80 | bellard | |
558 | e6e5ad80 | bellard | static void |
559 | e6e5ad80 | bellard | cirrus_colorexpand_32(CirrusVGAState * s, uint8_t * dst, |
560 | e6e5ad80 | bellard | const uint8_t * src, int count) |
561 | e6e5ad80 | bellard | { |
562 | e6e5ad80 | bellard | int x;
|
563 | e6e5ad80 | bellard | uint8_t colors[2][4]; |
564 | e6e5ad80 | bellard | unsigned bits;
|
565 | e6e5ad80 | bellard | unsigned bitmask;
|
566 | e6e5ad80 | bellard | unsigned index;
|
567 | e6e5ad80 | bellard | int srcskipleft = 0; |
568 | e6e5ad80 | bellard | |
569 | e6e5ad80 | bellard | colors[0][0] = s->gr[0x00]; |
570 | e6e5ad80 | bellard | colors[0][1] = s->gr[0x10]; |
571 | e6e5ad80 | bellard | colors[0][2] = s->gr[0x12]; |
572 | e6e5ad80 | bellard | colors[0][3] = s->gr[0x14]; |
573 | e6e5ad80 | bellard | colors[1][0] = s->gr[0x01]; |
574 | e6e5ad80 | bellard | colors[1][1] = s->gr[0x11]; |
575 | e6e5ad80 | bellard | colors[1][2] = s->gr[0x13]; |
576 | e6e5ad80 | bellard | colors[1][3] = s->gr[0x15]; |
577 | e6e5ad80 | bellard | |
578 | e6e5ad80 | bellard | bitmask = 0x80 << srcskipleft;
|
579 | e6e5ad80 | bellard | bits = *src++; |
580 | e6e5ad80 | bellard | for (x = 0; x < count; x++) { |
581 | e6e5ad80 | bellard | if ((bitmask & 0xff) == 0) { |
582 | e6e5ad80 | bellard | bitmask = 0x80;
|
583 | e6e5ad80 | bellard | bits = *src++; |
584 | e6e5ad80 | bellard | } |
585 | e6e5ad80 | bellard | index = !!(bits & bitmask); |
586 | e6e5ad80 | bellard | *dst++ = colors[index][0];
|
587 | e6e5ad80 | bellard | *dst++ = colors[index][1];
|
588 | e6e5ad80 | bellard | *dst++ = colors[index][2];
|
589 | e6e5ad80 | bellard | *dst++ = colors[index][3];
|
590 | e6e5ad80 | bellard | bitmask >>= 1;
|
591 | e6e5ad80 | bellard | } |
592 | e6e5ad80 | bellard | } |
593 | e6e5ad80 | bellard | |
594 | e6e5ad80 | bellard | static void |
595 | e6e5ad80 | bellard | cirrus_colorexpand(CirrusVGAState * s, uint8_t * dst, const uint8_t * src,
|
596 | e6e5ad80 | bellard | int count)
|
597 | e6e5ad80 | bellard | { |
598 | e6e5ad80 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
599 | e6e5ad80 | bellard | case 1: |
600 | e6e5ad80 | bellard | cirrus_colorexpand_8(s, dst, src, count); |
601 | e6e5ad80 | bellard | break;
|
602 | e6e5ad80 | bellard | case 2: |
603 | e6e5ad80 | bellard | cirrus_colorexpand_16(s, dst, src, count); |
604 | e6e5ad80 | bellard | break;
|
605 | e6e5ad80 | bellard | case 3: |
606 | e6e5ad80 | bellard | cirrus_colorexpand_24(s, dst, src, count); |
607 | e6e5ad80 | bellard | break;
|
608 | e6e5ad80 | bellard | case 4: |
609 | e6e5ad80 | bellard | cirrus_colorexpand_32(s, dst, src, count); |
610 | e6e5ad80 | bellard | break;
|
611 | e6e5ad80 | bellard | default:
|
612 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
613 | e6e5ad80 | bellard | printf("cirrus: COLOREXPAND pixelwidth %d - unimplemented\n",
|
614 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth); |
615 | e6e5ad80 | bellard | #endif
|
616 | e6e5ad80 | bellard | break;
|
617 | e6e5ad80 | bellard | } |
618 | e6e5ad80 | bellard | } |
619 | e6e5ad80 | bellard | |
620 | e6e5ad80 | bellard | static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
621 | e6e5ad80 | bellard | int off_pitch, int bytesperline, |
622 | e6e5ad80 | bellard | int lines)
|
623 | e6e5ad80 | bellard | { |
624 | e6e5ad80 | bellard | int y;
|
625 | e6e5ad80 | bellard | int off_cur;
|
626 | e6e5ad80 | bellard | int off_cur_end;
|
627 | e6e5ad80 | bellard | |
628 | e6e5ad80 | bellard | for (y = 0; y < lines; y++) { |
629 | e6e5ad80 | bellard | off_cur = off_begin; |
630 | e6e5ad80 | bellard | off_cur_end = off_cur + bytesperline; |
631 | e6e5ad80 | bellard | off_cur &= TARGET_PAGE_MASK; |
632 | e6e5ad80 | bellard | while (off_cur < off_cur_end) {
|
633 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + off_cur); |
634 | e6e5ad80 | bellard | off_cur += TARGET_PAGE_SIZE; |
635 | e6e5ad80 | bellard | } |
636 | e6e5ad80 | bellard | off_begin += off_pitch; |
637 | e6e5ad80 | bellard | } |
638 | e6e5ad80 | bellard | } |
639 | e6e5ad80 | bellard | |
640 | e6e5ad80 | bellard | |
641 | e6e5ad80 | bellard | |
642 | e6e5ad80 | bellard | static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
643 | e6e5ad80 | bellard | const uint8_t * src)
|
644 | e6e5ad80 | bellard | { |
645 | e6e5ad80 | bellard | uint8_t work_colorexp[256];
|
646 | e6e5ad80 | bellard | uint8_t *dst; |
647 | e6e5ad80 | bellard | uint8_t *dstc; |
648 | e6e5ad80 | bellard | int x, y;
|
649 | e6e5ad80 | bellard | int tilewidth, tileheight;
|
650 | e6e5ad80 | bellard | int patternbytes = s->cirrus_blt_pixelwidth * 8; |
651 | e6e5ad80 | bellard | |
652 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
653 | e6e5ad80 | bellard | cirrus_colorexpand(s, work_colorexp, src, 8 * 8); |
654 | e6e5ad80 | bellard | src = work_colorexp; |
655 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_COLOREXPAND; |
656 | e6e5ad80 | bellard | } |
657 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_PATTERNCOPY) {
|
658 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
659 | e6e5ad80 | bellard | printf("cirrus: blt mode %02x (pattercopy) - unimplemented\n",
|
660 | e6e5ad80 | bellard | s->cirrus_blt_mode); |
661 | e6e5ad80 | bellard | #endif
|
662 | e6e5ad80 | bellard | return 0; |
663 | e6e5ad80 | bellard | } |
664 | e6e5ad80 | bellard | |
665 | e6e5ad80 | bellard | dst = s->vram_ptr + s->cirrus_blt_dstaddr; |
666 | e6e5ad80 | bellard | for (y = 0; y < s->cirrus_blt_height; y += 8) { |
667 | e6e5ad80 | bellard | dstc = dst; |
668 | e6e5ad80 | bellard | tileheight = qemu_MIN(8, s->cirrus_blt_height - y);
|
669 | e6e5ad80 | bellard | for (x = 0; x < s->cirrus_blt_width; x += patternbytes) { |
670 | e6e5ad80 | bellard | tilewidth = qemu_MIN(patternbytes, s->cirrus_blt_width - x); |
671 | e6e5ad80 | bellard | (*s->cirrus_rop) (dstc, src, |
672 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, patternbytes, |
673 | e6e5ad80 | bellard | tilewidth, tileheight); |
674 | e6e5ad80 | bellard | dstc += patternbytes; |
675 | e6e5ad80 | bellard | } |
676 | e6e5ad80 | bellard | dst += s->cirrus_blt_dstpitch * 8;
|
677 | e6e5ad80 | bellard | } |
678 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
679 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
680 | e6e5ad80 | bellard | s->cirrus_blt_height); |
681 | e6e5ad80 | bellard | return 1; |
682 | e6e5ad80 | bellard | } |
683 | e6e5ad80 | bellard | |
684 | e6e5ad80 | bellard | /***************************************
|
685 | e6e5ad80 | bellard | *
|
686 | e6e5ad80 | bellard | * bitblt (video-to-video)
|
687 | e6e5ad80 | bellard | *
|
688 | e6e5ad80 | bellard | ***************************************/
|
689 | e6e5ad80 | bellard | |
690 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
691 | e6e5ad80 | bellard | { |
692 | e6e5ad80 | bellard | return cirrus_bitblt_common_patterncopy(s,
|
693 | e6e5ad80 | bellard | s->vram_ptr + |
694 | e6e5ad80 | bellard | s->cirrus_blt_srcaddr); |
695 | e6e5ad80 | bellard | } |
696 | e6e5ad80 | bellard | |
697 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
698 | e6e5ad80 | bellard | { |
699 | e6e5ad80 | bellard | if ((s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) != 0) { |
700 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
701 | e6e5ad80 | bellard | printf("cirrus: CIRRUS_BLTMODE_COLOREXPAND - unimplemented\n");
|
702 | e6e5ad80 | bellard | #endif
|
703 | e6e5ad80 | bellard | return 0; |
704 | e6e5ad80 | bellard | } |
705 | e6e5ad80 | bellard | if ((s->cirrus_blt_mode & (~CIRRUS_BLTMODE_BACKWARDS)) != 0) { |
706 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
707 | e6e5ad80 | bellard | printf("cirrus: blt mode %02x - unimplemented\n",
|
708 | e6e5ad80 | bellard | s->cirrus_blt_mode); |
709 | e6e5ad80 | bellard | #endif
|
710 | e6e5ad80 | bellard | return 0; |
711 | e6e5ad80 | bellard | } |
712 | e6e5ad80 | bellard | |
713 | e6e5ad80 | bellard | (*s->cirrus_rop) (s->vram_ptr + s->cirrus_blt_dstaddr, |
714 | e6e5ad80 | bellard | s->vram_ptr + s->cirrus_blt_srcaddr, |
715 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
716 | e6e5ad80 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
717 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
718 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
719 | e6e5ad80 | bellard | s->cirrus_blt_height); |
720 | e6e5ad80 | bellard | return 1; |
721 | e6e5ad80 | bellard | } |
722 | e6e5ad80 | bellard | |
723 | e6e5ad80 | bellard | /***************************************
|
724 | e6e5ad80 | bellard | *
|
725 | e6e5ad80 | bellard | * bitblt (cpu-to-video)
|
726 | e6e5ad80 | bellard | *
|
727 | e6e5ad80 | bellard | ***************************************/
|
728 | e6e5ad80 | bellard | |
729 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_patterncopy(void *opaque) |
730 | e6e5ad80 | bellard | { |
731 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
732 | e6e5ad80 | bellard | int data_count;
|
733 | e6e5ad80 | bellard | |
734 | e6e5ad80 | bellard | data_count = s->cirrus_srcptr - &s->cirrus_bltbuf[0];
|
735 | e6e5ad80 | bellard | |
736 | e6e5ad80 | bellard | if (data_count > 0) { |
737 | e6e5ad80 | bellard | if (data_count != s->cirrus_srccounter) {
|
738 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
739 | e6e5ad80 | bellard | printf("cirrus: internal error\n");
|
740 | e6e5ad80 | bellard | #endif
|
741 | e6e5ad80 | bellard | } else {
|
742 | e6e5ad80 | bellard | cirrus_bitblt_common_patterncopy(s, &s->cirrus_bltbuf[0]);
|
743 | e6e5ad80 | bellard | } |
744 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
745 | e6e5ad80 | bellard | } |
746 | e6e5ad80 | bellard | } |
747 | e6e5ad80 | bellard | |
748 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_copy(void *opaque) |
749 | e6e5ad80 | bellard | { |
750 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
751 | e6e5ad80 | bellard | int data_count;
|
752 | e6e5ad80 | bellard | int data_avail;
|
753 | e6e5ad80 | bellard | uint8_t work_colorexp[256];
|
754 | e6e5ad80 | bellard | uint8_t *src_ptr = NULL;
|
755 | e6e5ad80 | bellard | int src_avail = 0; |
756 | e6e5ad80 | bellard | int src_processing;
|
757 | e6e5ad80 | bellard | int src_linepad = 0; |
758 | e6e5ad80 | bellard | |
759 | e6e5ad80 | bellard | if (s->cirrus_blt_height <= 0) { |
760 | e6e5ad80 | bellard | s->cirrus_srcptr = s->cirrus_srcptr_end; |
761 | e6e5ad80 | bellard | return;
|
762 | e6e5ad80 | bellard | } |
763 | e6e5ad80 | bellard | |
764 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
765 | e6e5ad80 | bellard | while (1) { |
766 | e6e5ad80 | bellard | /* get BLT source. */
|
767 | e6e5ad80 | bellard | if (src_avail <= 0) { |
768 | e6e5ad80 | bellard | data_count = s->cirrus_srcptr_end - s->cirrus_srcptr; |
769 | e6e5ad80 | bellard | if (data_count <= 0) |
770 | e6e5ad80 | bellard | break;
|
771 | e6e5ad80 | bellard | |
772 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
773 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_COLOREXPAND) {
|
774 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
775 | e6e5ad80 | bellard | printf("cirrus: unsupported\n");
|
776 | e6e5ad80 | bellard | #endif
|
777 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
778 | e6e5ad80 | bellard | return;
|
779 | e6e5ad80 | bellard | } |
780 | e6e5ad80 | bellard | data_avail = qemu_MIN(data_count, 256 / 32); |
781 | e6e5ad80 | bellard | cirrus_colorexpand(s, work_colorexp, s->cirrus_srcptr, |
782 | e6e5ad80 | bellard | data_avail * 8);
|
783 | e6e5ad80 | bellard | src_ptr = &work_colorexp[0];
|
784 | e6e5ad80 | bellard | src_avail = data_avail * 8 * s->cirrus_blt_pixelwidth;
|
785 | e6e5ad80 | bellard | s->cirrus_srcptr += data_avail; |
786 | e6e5ad80 | bellard | src_linepad = |
787 | e6e5ad80 | bellard | ((s->cirrus_blt_width + 7) / 8) * 8 - |
788 | e6e5ad80 | bellard | s->cirrus_blt_width; |
789 | e6e5ad80 | bellard | src_linepad *= s->cirrus_blt_pixelwidth; |
790 | e6e5ad80 | bellard | } else {
|
791 | e6e5ad80 | bellard | if (s->cirrus_blt_mode != 0) { |
792 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
793 | e6e5ad80 | bellard | printf("cirrus: unsupported\n");
|
794 | e6e5ad80 | bellard | #endif
|
795 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
796 | e6e5ad80 | bellard | return;
|
797 | e6e5ad80 | bellard | } |
798 | e6e5ad80 | bellard | src_ptr = s->cirrus_srcptr; |
799 | e6e5ad80 | bellard | src_avail = |
800 | e6e5ad80 | bellard | data_count / s->cirrus_blt_pixelwidth * |
801 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth; |
802 | e6e5ad80 | bellard | s->cirrus_srcptr += src_avail; |
803 | e6e5ad80 | bellard | } |
804 | e6e5ad80 | bellard | if (src_avail <= 0) |
805 | e6e5ad80 | bellard | break;
|
806 | e6e5ad80 | bellard | } |
807 | e6e5ad80 | bellard | |
808 | e6e5ad80 | bellard | /* 1-line BLT */
|
809 | e6e5ad80 | bellard | src_processing = |
810 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch - s->cirrus_blt_horz_counter; |
811 | e6e5ad80 | bellard | src_processing = qemu_MIN(src_avail, src_processing); |
812 | e6e5ad80 | bellard | (*s->cirrus_rop) (s->vram_ptr + s->cirrus_blt_dstaddr, |
813 | e6e5ad80 | bellard | src_ptr, 0, 0, src_processing, 1); |
814 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
815 | e6e5ad80 | bellard | src_processing, 1);
|
816 | e6e5ad80 | bellard | |
817 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr += src_processing; |
818 | e6e5ad80 | bellard | src_ptr += src_processing; |
819 | e6e5ad80 | bellard | src_avail -= src_processing; |
820 | e6e5ad80 | bellard | s->cirrus_blt_horz_counter += src_processing; |
821 | e6e5ad80 | bellard | if (s->cirrus_blt_horz_counter >= s->cirrus_blt_srcpitch) {
|
822 | e6e5ad80 | bellard | src_ptr += src_linepad; |
823 | e6e5ad80 | bellard | src_avail -= src_linepad; |
824 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr += |
825 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch - s->cirrus_blt_srcpitch; |
826 | e6e5ad80 | bellard | s->cirrus_blt_horz_counter = 0;
|
827 | e6e5ad80 | bellard | s->cirrus_blt_height--; |
828 | e6e5ad80 | bellard | if (s->cirrus_blt_height <= 0) { |
829 | e6e5ad80 | bellard | s->cirrus_srcptr = s->cirrus_srcptr_end; |
830 | e6e5ad80 | bellard | return;
|
831 | e6e5ad80 | bellard | } |
832 | e6e5ad80 | bellard | } |
833 | e6e5ad80 | bellard | } |
834 | e6e5ad80 | bellard | } |
835 | e6e5ad80 | bellard | |
836 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
837 | e6e5ad80 | bellard | { |
838 | e6e5ad80 | bellard | int copy_count;
|
839 | e6e5ad80 | bellard | int avail_count;
|
840 | e6e5ad80 | bellard | |
841 | e6e5ad80 | bellard | s->cirrus_blt_handler(s); |
842 | e6e5ad80 | bellard | |
843 | e6e5ad80 | bellard | if (s->cirrus_srccounter > 0) { |
844 | e6e5ad80 | bellard | s->cirrus_srccounter -= s->cirrus_srcptr - &s->cirrus_bltbuf[0];
|
845 | e6e5ad80 | bellard | copy_count = s->cirrus_srcptr_end - s->cirrus_srcptr; |
846 | e6e5ad80 | bellard | memmove(&s->cirrus_bltbuf[0], s->cirrus_srcptr, copy_count);
|
847 | e6e5ad80 | bellard | avail_count = qemu_MIN(CIRRUS_BLTBUFSIZE, s->cirrus_srccounter); |
848 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
849 | e6e5ad80 | bellard | s->cirrus_srcptr_end = s->cirrus_srcptr + avail_count; |
850 | e6e5ad80 | bellard | if (s->cirrus_srccounter <= 0) { |
851 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
852 | e6e5ad80 | bellard | } |
853 | e6e5ad80 | bellard | } |
854 | e6e5ad80 | bellard | } |
855 | e6e5ad80 | bellard | |
856 | e6e5ad80 | bellard | /***************************************
|
857 | e6e5ad80 | bellard | *
|
858 | e6e5ad80 | bellard | * bitblt wrapper
|
859 | e6e5ad80 | bellard | *
|
860 | e6e5ad80 | bellard | ***************************************/
|
861 | e6e5ad80 | bellard | |
862 | e6e5ad80 | bellard | static void cirrus_bitblt_reset(CirrusVGAState * s) |
863 | e6e5ad80 | bellard | { |
864 | e6e5ad80 | bellard | s->gr[0x31] &=
|
865 | e6e5ad80 | bellard | ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
866 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
867 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
868 | e6e5ad80 | bellard | s->cirrus_srccounter = 0;
|
869 | e6e5ad80 | bellard | s->cirrus_dstptr = &s->cirrus_bltbuf[0];
|
870 | e6e5ad80 | bellard | s->cirrus_dstptr_end = &s->cirrus_bltbuf[0];
|
871 | e6e5ad80 | bellard | s->cirrus_dstcounter = 0;
|
872 | e6e5ad80 | bellard | s->cirrus_blt_handler = NULL;
|
873 | e6e5ad80 | bellard | } |
874 | e6e5ad80 | bellard | |
875 | e6e5ad80 | bellard | static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
876 | e6e5ad80 | bellard | { |
877 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
878 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
879 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
880 | e6e5ad80 | bellard | |
881 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
882 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
883 | e6e5ad80 | bellard | s->cirrus_srccounter = 8;
|
884 | e6e5ad80 | bellard | } else {
|
885 | e6e5ad80 | bellard | s->cirrus_srccounter = 8 * 8 * s->cirrus_blt_pixelwidth; |
886 | e6e5ad80 | bellard | } |
887 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch = 0;
|
888 | e6e5ad80 | bellard | s->cirrus_blt_handler = cirrus_bitblt_cputovideo_patterncopy; |
889 | e6e5ad80 | bellard | } else {
|
890 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
891 | e6e5ad80 | bellard | s->cirrus_srccounter = |
892 | e6e5ad80 | bellard | ((s->cirrus_blt_width + 7) / 8) * s->cirrus_blt_height; |
893 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch = |
894 | e6e5ad80 | bellard | s->cirrus_blt_width * s->cirrus_blt_pixelwidth; |
895 | e6e5ad80 | bellard | } else {
|
896 | e6e5ad80 | bellard | s->cirrus_srccounter = |
897 | e6e5ad80 | bellard | s->cirrus_blt_width * s->cirrus_blt_height; |
898 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch = s->cirrus_blt_width; |
899 | e6e5ad80 | bellard | } |
900 | e6e5ad80 | bellard | /* 4-byte alignment */
|
901 | e6e5ad80 | bellard | s->cirrus_srccounter = (s->cirrus_srccounter + 3) & (~3); |
902 | e6e5ad80 | bellard | |
903 | e6e5ad80 | bellard | s->cirrus_blt_handler = cirrus_bitblt_cputovideo_copy; |
904 | e6e5ad80 | bellard | s->cirrus_blt_horz_counter = 0;
|
905 | e6e5ad80 | bellard | } |
906 | e6e5ad80 | bellard | |
907 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
908 | e6e5ad80 | bellard | return 1; |
909 | e6e5ad80 | bellard | } |
910 | e6e5ad80 | bellard | |
911 | e6e5ad80 | bellard | static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
912 | e6e5ad80 | bellard | { |
913 | e6e5ad80 | bellard | /* XXX */
|
914 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
915 | e6e5ad80 | bellard | printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
916 | e6e5ad80 | bellard | #endif
|
917 | e6e5ad80 | bellard | return 0; |
918 | e6e5ad80 | bellard | } |
919 | e6e5ad80 | bellard | |
920 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
921 | e6e5ad80 | bellard | { |
922 | e6e5ad80 | bellard | int ret;
|
923 | e6e5ad80 | bellard | |
924 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
925 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_patterncopy(s); |
926 | e6e5ad80 | bellard | } else {
|
927 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_copy(s); |
928 | e6e5ad80 | bellard | } |
929 | e6e5ad80 | bellard | |
930 | e6e5ad80 | bellard | if (ret)
|
931 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
932 | e6e5ad80 | bellard | return ret;
|
933 | e6e5ad80 | bellard | } |
934 | e6e5ad80 | bellard | |
935 | e6e5ad80 | bellard | static void cirrus_bitblt_start(CirrusVGAState * s) |
936 | e6e5ad80 | bellard | { |
937 | e6e5ad80 | bellard | uint8_t blt_rop; |
938 | e6e5ad80 | bellard | |
939 | e6e5ad80 | bellard | s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1; |
940 | e6e5ad80 | bellard | s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1; |
941 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8)); |
942 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8)); |
943 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr = |
944 | e6e5ad80 | bellard | (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16)); |
945 | e6e5ad80 | bellard | s->cirrus_blt_srcaddr = |
946 | e6e5ad80 | bellard | (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16)); |
947 | e6e5ad80 | bellard | s->cirrus_blt_mode = s->gr[0x30];
|
948 | e6e5ad80 | bellard | blt_rop = s->gr[0x32];
|
949 | e6e5ad80 | bellard | |
950 | e6e5ad80 | bellard | switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
951 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH8:
|
952 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 1;
|
953 | e6e5ad80 | bellard | break;
|
954 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH16:
|
955 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 2;
|
956 | e6e5ad80 | bellard | break;
|
957 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH24:
|
958 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 3;
|
959 | e6e5ad80 | bellard | break;
|
960 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH32:
|
961 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 4;
|
962 | e6e5ad80 | bellard | break;
|
963 | e6e5ad80 | bellard | default:
|
964 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
965 | e6e5ad80 | bellard | printf("cirrus: bitblt - pixel width is unknown\n");
|
966 | e6e5ad80 | bellard | #endif
|
967 | e6e5ad80 | bellard | goto bitblt_ignore;
|
968 | e6e5ad80 | bellard | } |
969 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
970 | e6e5ad80 | bellard | |
971 | e6e5ad80 | bellard | if ((s->
|
972 | e6e5ad80 | bellard | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
973 | e6e5ad80 | bellard | CIRRUS_BLTMODE_MEMSYSDEST)) |
974 | e6e5ad80 | bellard | == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { |
975 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
976 | e6e5ad80 | bellard | printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
977 | e6e5ad80 | bellard | #endif
|
978 | e6e5ad80 | bellard | goto bitblt_ignore;
|
979 | e6e5ad80 | bellard | } |
980 | e6e5ad80 | bellard | |
981 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
982 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
983 | e6e5ad80 | bellard | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
984 | e6e5ad80 | bellard | s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop); |
985 | e6e5ad80 | bellard | } else {
|
986 | e6e5ad80 | bellard | s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop); |
987 | e6e5ad80 | bellard | } |
988 | e6e5ad80 | bellard | |
989 | e6e5ad80 | bellard | // setup bitblt engine.
|
990 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
991 | e6e5ad80 | bellard | if (!cirrus_bitblt_cputovideo(s))
|
992 | e6e5ad80 | bellard | goto bitblt_ignore;
|
993 | e6e5ad80 | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
994 | e6e5ad80 | bellard | if (!cirrus_bitblt_videotocpu(s))
|
995 | e6e5ad80 | bellard | goto bitblt_ignore;
|
996 | e6e5ad80 | bellard | } else {
|
997 | e6e5ad80 | bellard | if (!cirrus_bitblt_videotovideo(s))
|
998 | e6e5ad80 | bellard | goto bitblt_ignore;
|
999 | e6e5ad80 | bellard | } |
1000 | e6e5ad80 | bellard | |
1001 | e6e5ad80 | bellard | return;
|
1002 | e6e5ad80 | bellard | bitblt_ignore:;
|
1003 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1004 | e6e5ad80 | bellard | } |
1005 | e6e5ad80 | bellard | |
1006 | e6e5ad80 | bellard | static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
1007 | e6e5ad80 | bellard | { |
1008 | e6e5ad80 | bellard | unsigned old_value;
|
1009 | e6e5ad80 | bellard | |
1010 | e6e5ad80 | bellard | old_value = s->gr[0x31];
|
1011 | e6e5ad80 | bellard | s->gr[0x31] = reg_value;
|
1012 | e6e5ad80 | bellard | |
1013 | e6e5ad80 | bellard | if (((old_value & CIRRUS_BLT_RESET) != 0) && |
1014 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
1015 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1016 | e6e5ad80 | bellard | } else if (((old_value & CIRRUS_BLT_START) == 0) && |
1017 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_START) != 0)) {
|
1018 | e6e5ad80 | bellard | s->gr[0x31] |= CIRRUS_BLT_BUSY;
|
1019 | e6e5ad80 | bellard | cirrus_bitblt_start(s); |
1020 | e6e5ad80 | bellard | } |
1021 | e6e5ad80 | bellard | } |
1022 | e6e5ad80 | bellard | |
1023 | e6e5ad80 | bellard | |
1024 | e6e5ad80 | bellard | /***************************************
|
1025 | e6e5ad80 | bellard | *
|
1026 | e6e5ad80 | bellard | * basic parameters
|
1027 | e6e5ad80 | bellard | *
|
1028 | e6e5ad80 | bellard | ***************************************/
|
1029 | e6e5ad80 | bellard | |
1030 | e6e5ad80 | bellard | static void cirrus_get_offsets(VGAState *s1, |
1031 | e6e5ad80 | bellard | uint32_t *pline_offset, |
1032 | e6e5ad80 | bellard | uint32_t *pstart_addr) |
1033 | e6e5ad80 | bellard | { |
1034 | e6e5ad80 | bellard | CirrusVGAState * s = (CirrusVGAState *)s1; |
1035 | e6e5ad80 | bellard | uint32_t start_addr; |
1036 | e6e5ad80 | bellard | uint32_t line_offset; |
1037 | e6e5ad80 | bellard | |
1038 | e6e5ad80 | bellard | line_offset = s->cr[0x13]
|
1039 | e6e5ad80 | bellard | | ((s->cr[0x1b] & 0x10) << 8); |
1040 | e6e5ad80 | bellard | line_offset <<= 3;
|
1041 | e6e5ad80 | bellard | *pline_offset = line_offset; |
1042 | e6e5ad80 | bellard | |
1043 | e6e5ad80 | bellard | start_addr = (s->cr[0x0c] << 8) |
1044 | e6e5ad80 | bellard | | s->cr[0x0d]
|
1045 | e6e5ad80 | bellard | | ((s->cr[0x1b] & 0x01) << 16) |
1046 | e6e5ad80 | bellard | | ((s->cr[0x1b] & 0x0c) << 15) |
1047 | e6e5ad80 | bellard | | ((s->cr[0x1d] & 0x80) << 12); |
1048 | e6e5ad80 | bellard | *pstart_addr = start_addr; |
1049 | e6e5ad80 | bellard | } |
1050 | e6e5ad80 | bellard | |
1051 | e6e5ad80 | bellard | static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
1052 | e6e5ad80 | bellard | { |
1053 | e6e5ad80 | bellard | uint32_t ret = 16;
|
1054 | e6e5ad80 | bellard | |
1055 | e6e5ad80 | bellard | switch (s->cirrus_hidden_dac_data & 0xf) { |
1056 | e6e5ad80 | bellard | case 0: |
1057 | e6e5ad80 | bellard | ret = 15;
|
1058 | e6e5ad80 | bellard | break; /* Sierra HiColor */ |
1059 | e6e5ad80 | bellard | case 1: |
1060 | e6e5ad80 | bellard | ret = 16;
|
1061 | e6e5ad80 | bellard | break; /* XGA HiColor */ |
1062 | e6e5ad80 | bellard | default:
|
1063 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1064 | e6e5ad80 | bellard | printf("cirrus: invalid DAC value %x in 16bpp\n",
|
1065 | e6e5ad80 | bellard | (s->cirrus_hidden_dac_data & 0xf));
|
1066 | e6e5ad80 | bellard | #endif
|
1067 | e6e5ad80 | bellard | ret = 15; /* XXX */ |
1068 | e6e5ad80 | bellard | break;
|
1069 | e6e5ad80 | bellard | } |
1070 | e6e5ad80 | bellard | return ret;
|
1071 | e6e5ad80 | bellard | } |
1072 | e6e5ad80 | bellard | |
1073 | e6e5ad80 | bellard | static int cirrus_get_bpp(VGAState *s1) |
1074 | e6e5ad80 | bellard | { |
1075 | e6e5ad80 | bellard | CirrusVGAState * s = (CirrusVGAState *)s1; |
1076 | e6e5ad80 | bellard | uint32_t ret = 8;
|
1077 | e6e5ad80 | bellard | |
1078 | e6e5ad80 | bellard | if ((s->sr[0x07] & 0x01) != 0) { |
1079 | e6e5ad80 | bellard | /* Cirrus SVGA */
|
1080 | e6e5ad80 | bellard | switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
1081 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_8:
|
1082 | e6e5ad80 | bellard | ret = 8;
|
1083 | e6e5ad80 | bellard | break;
|
1084 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
1085 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1086 | e6e5ad80 | bellard | break;
|
1087 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_24:
|
1088 | e6e5ad80 | bellard | ret = 24;
|
1089 | e6e5ad80 | bellard | break;
|
1090 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16:
|
1091 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1092 | e6e5ad80 | bellard | break;
|
1093 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_32:
|
1094 | e6e5ad80 | bellard | ret = 32;
|
1095 | e6e5ad80 | bellard | break;
|
1096 | e6e5ad80 | bellard | default:
|
1097 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1098 | e6e5ad80 | bellard | printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]); |
1099 | e6e5ad80 | bellard | #endif
|
1100 | e6e5ad80 | bellard | ret = 8;
|
1101 | e6e5ad80 | bellard | break;
|
1102 | e6e5ad80 | bellard | } |
1103 | e6e5ad80 | bellard | } else {
|
1104 | e6e5ad80 | bellard | /* VGA */
|
1105 | e6e5ad80 | bellard | ret = 8;
|
1106 | e6e5ad80 | bellard | } |
1107 | e6e5ad80 | bellard | |
1108 | e6e5ad80 | bellard | return ret;
|
1109 | e6e5ad80 | bellard | } |
1110 | e6e5ad80 | bellard | |
1111 | e6e5ad80 | bellard | /***************************************
|
1112 | e6e5ad80 | bellard | *
|
1113 | e6e5ad80 | bellard | * bank memory
|
1114 | e6e5ad80 | bellard | *
|
1115 | e6e5ad80 | bellard | ***************************************/
|
1116 | e6e5ad80 | bellard | |
1117 | e6e5ad80 | bellard | static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
1118 | e6e5ad80 | bellard | { |
1119 | e6e5ad80 | bellard | unsigned offset;
|
1120 | e6e5ad80 | bellard | unsigned limit;
|
1121 | e6e5ad80 | bellard | |
1122 | e6e5ad80 | bellard | if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */ |
1123 | e6e5ad80 | bellard | offset = s->gr[0x09 + bank_index];
|
1124 | e6e5ad80 | bellard | else /* single bank */ |
1125 | e6e5ad80 | bellard | offset = s->gr[0x09];
|
1126 | e6e5ad80 | bellard | |
1127 | e6e5ad80 | bellard | if ((s->gr[0x0b] & 0x20) != 0) |
1128 | e6e5ad80 | bellard | offset <<= 14;
|
1129 | e6e5ad80 | bellard | else
|
1130 | e6e5ad80 | bellard | offset <<= 12;
|
1131 | e6e5ad80 | bellard | |
1132 | e6e5ad80 | bellard | if (s->vram_size <= offset)
|
1133 | e6e5ad80 | bellard | limit = 0;
|
1134 | e6e5ad80 | bellard | else
|
1135 | e6e5ad80 | bellard | limit = s->vram_size - offset; |
1136 | e6e5ad80 | bellard | |
1137 | e6e5ad80 | bellard | if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1138 | e6e5ad80 | bellard | if (limit > 0x8000) { |
1139 | e6e5ad80 | bellard | offset += 0x8000;
|
1140 | e6e5ad80 | bellard | limit -= 0x8000;
|
1141 | e6e5ad80 | bellard | } else {
|
1142 | e6e5ad80 | bellard | limit = 0;
|
1143 | e6e5ad80 | bellard | } |
1144 | e6e5ad80 | bellard | } |
1145 | e6e5ad80 | bellard | |
1146 | e6e5ad80 | bellard | if (limit > 0) { |
1147 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = offset; |
1148 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = limit; |
1149 | e6e5ad80 | bellard | } else {
|
1150 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = 0;
|
1151 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = 0;
|
1152 | e6e5ad80 | bellard | } |
1153 | e6e5ad80 | bellard | } |
1154 | e6e5ad80 | bellard | |
1155 | e6e5ad80 | bellard | /***************************************
|
1156 | e6e5ad80 | bellard | *
|
1157 | e6e5ad80 | bellard | * I/O access between 0x3c4-0x3c5
|
1158 | e6e5ad80 | bellard | *
|
1159 | e6e5ad80 | bellard | ***************************************/
|
1160 | e6e5ad80 | bellard | |
1161 | e6e5ad80 | bellard | static int |
1162 | e6e5ad80 | bellard | cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1163 | e6e5ad80 | bellard | { |
1164 | e6e5ad80 | bellard | switch (reg_index) {
|
1165 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1166 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1167 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1168 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1169 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1170 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1171 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1172 | e6e5ad80 | bellard | *reg_value = s->sr[reg_index]; |
1173 | e6e5ad80 | bellard | break;
|
1174 | e6e5ad80 | bellard | case 0x05: // ??? |
1175 | e6e5ad80 | bellard | case 0x07: // Extended Sequencer Mode |
1176 | e6e5ad80 | bellard | case 0x08: // EEPROM Control |
1177 | e6e5ad80 | bellard | case 0x09: // Scratch Register 0 |
1178 | e6e5ad80 | bellard | case 0x0a: // Scratch Register 1 |
1179 | e6e5ad80 | bellard | case 0x0b: // VCLK 0 |
1180 | e6e5ad80 | bellard | case 0x0c: // VCLK 1 |
1181 | e6e5ad80 | bellard | case 0x0d: // VCLK 2 |
1182 | e6e5ad80 | bellard | case 0x0e: // VCLK 3 |
1183 | e6e5ad80 | bellard | case 0x0f: // DRAM Control |
1184 | e6e5ad80 | bellard | case 0x10: |
1185 | e6e5ad80 | bellard | case 0x30: |
1186 | e6e5ad80 | bellard | case 0x50: |
1187 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1188 | e6e5ad80 | bellard | case 0x90: |
1189 | e6e5ad80 | bellard | case 0xb0: |
1190 | e6e5ad80 | bellard | case 0xd0: |
1191 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1192 | e6e5ad80 | bellard | case 0x11: |
1193 | e6e5ad80 | bellard | case 0x31: |
1194 | e6e5ad80 | bellard | case 0x51: |
1195 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1196 | e6e5ad80 | bellard | case 0x91: |
1197 | e6e5ad80 | bellard | case 0xb1: |
1198 | e6e5ad80 | bellard | case 0xd1: |
1199 | e6e5ad80 | bellard | case 0xf1: // Graphics Cursor Y |
1200 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1201 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1202 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1203 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1204 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1205 | e6e5ad80 | bellard | case 0x17: // Configuration Readback and Extended Control |
1206 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1207 | e6e5ad80 | bellard | case 0x19: // Signal Generator Result |
1208 | e6e5ad80 | bellard | case 0x1a: // Signal Generator Result |
1209 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1210 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1211 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1212 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1213 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1214 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1215 | e6e5ad80 | bellard | printf("cirrus: handled inport sr_index %02x\n", reg_index);
|
1216 | e6e5ad80 | bellard | #endif
|
1217 | e6e5ad80 | bellard | *reg_value = s->sr[reg_index]; |
1218 | e6e5ad80 | bellard | break;
|
1219 | e6e5ad80 | bellard | default:
|
1220 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1221 | e6e5ad80 | bellard | printf("cirrus: inport sr_index %02x\n", reg_index);
|
1222 | e6e5ad80 | bellard | #endif
|
1223 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1224 | e6e5ad80 | bellard | break;
|
1225 | e6e5ad80 | bellard | } |
1226 | e6e5ad80 | bellard | |
1227 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1228 | e6e5ad80 | bellard | } |
1229 | e6e5ad80 | bellard | |
1230 | e6e5ad80 | bellard | static int |
1231 | e6e5ad80 | bellard | cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1232 | e6e5ad80 | bellard | { |
1233 | e6e5ad80 | bellard | switch (reg_index) {
|
1234 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1235 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1236 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1237 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1238 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1239 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1240 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1241 | e6e5ad80 | bellard | reg_value &= 0x17;
|
1242 | e6e5ad80 | bellard | if (reg_value == 0x12) { |
1243 | e6e5ad80 | bellard | s->sr[reg_index] = 0x12;
|
1244 | e6e5ad80 | bellard | } else {
|
1245 | e6e5ad80 | bellard | s->sr[reg_index] = 0x0f;
|
1246 | e6e5ad80 | bellard | } |
1247 | e6e5ad80 | bellard | break;
|
1248 | e6e5ad80 | bellard | case 0x10: |
1249 | e6e5ad80 | bellard | case 0x30: |
1250 | e6e5ad80 | bellard | case 0x50: |
1251 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1252 | e6e5ad80 | bellard | case 0x90: |
1253 | e6e5ad80 | bellard | case 0xb0: |
1254 | e6e5ad80 | bellard | case 0xd0: |
1255 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1256 | e6e5ad80 | bellard | s->sr[0x10] = reg_value;
|
1257 | e6e5ad80 | bellard | s->cirrus_hw_cursor_x = ((reg_index << 3) & 0x700) | reg_value; |
1258 | e6e5ad80 | bellard | break;
|
1259 | e6e5ad80 | bellard | case 0x11: |
1260 | e6e5ad80 | bellard | case 0x31: |
1261 | e6e5ad80 | bellard | case 0x51: |
1262 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1263 | e6e5ad80 | bellard | case 0x91: |
1264 | e6e5ad80 | bellard | case 0xb1: |
1265 | e6e5ad80 | bellard | case 0xd1: |
1266 | e6e5ad80 | bellard | case 0xf1: // Graphics Cursor Y |
1267 | e6e5ad80 | bellard | s->sr[0x11] = reg_value;
|
1268 | e6e5ad80 | bellard | s->cirrus_hw_cursor_y = ((reg_index << 3) & 0x700) | reg_value; |
1269 | e6e5ad80 | bellard | break;
|
1270 | e6e5ad80 | bellard | case 0x07: // Extended Sequencer Mode |
1271 | e6e5ad80 | bellard | case 0x08: // EEPROM Control |
1272 | e6e5ad80 | bellard | case 0x09: // Scratch Register 0 |
1273 | e6e5ad80 | bellard | case 0x0a: // Scratch Register 1 |
1274 | e6e5ad80 | bellard | case 0x0b: // VCLK 0 |
1275 | e6e5ad80 | bellard | case 0x0c: // VCLK 1 |
1276 | e6e5ad80 | bellard | case 0x0d: // VCLK 2 |
1277 | e6e5ad80 | bellard | case 0x0e: // VCLK 3 |
1278 | e6e5ad80 | bellard | case 0x0f: // DRAM Control |
1279 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1280 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1281 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1282 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1283 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1284 | e6e5ad80 | bellard | case 0x17: // Configuration Readback and Extended Control |
1285 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1286 | e6e5ad80 | bellard | case 0x19: // Signature Generator Result |
1287 | e6e5ad80 | bellard | case 0x1a: // Signature Generator Result |
1288 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1289 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1290 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1291 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1292 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1293 | e6e5ad80 | bellard | s->sr[reg_index] = reg_value; |
1294 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1295 | e6e5ad80 | bellard | printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
1296 | e6e5ad80 | bellard | reg_index, reg_value); |
1297 | e6e5ad80 | bellard | #endif
|
1298 | e6e5ad80 | bellard | break;
|
1299 | e6e5ad80 | bellard | default:
|
1300 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1301 | e6e5ad80 | bellard | printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
|
1302 | e6e5ad80 | bellard | reg_value); |
1303 | e6e5ad80 | bellard | #endif
|
1304 | e6e5ad80 | bellard | break;
|
1305 | e6e5ad80 | bellard | } |
1306 | e6e5ad80 | bellard | |
1307 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1308 | e6e5ad80 | bellard | } |
1309 | e6e5ad80 | bellard | |
1310 | e6e5ad80 | bellard | /***************************************
|
1311 | e6e5ad80 | bellard | *
|
1312 | e6e5ad80 | bellard | * I/O access at 0x3c6
|
1313 | e6e5ad80 | bellard | *
|
1314 | e6e5ad80 | bellard | ***************************************/
|
1315 | e6e5ad80 | bellard | |
1316 | e6e5ad80 | bellard | static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value) |
1317 | e6e5ad80 | bellard | { |
1318 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1319 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex < 5) { |
1320 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex == 4) { |
1321 | e6e5ad80 | bellard | *reg_value = s->cirrus_hidden_dac_data; |
1322 | e6e5ad80 | bellard | } |
1323 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex++; |
1324 | e6e5ad80 | bellard | } |
1325 | e6e5ad80 | bellard | } |
1326 | e6e5ad80 | bellard | |
1327 | e6e5ad80 | bellard | static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
1328 | e6e5ad80 | bellard | { |
1329 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex == 4) { |
1330 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = reg_value; |
1331 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1332 | e6e5ad80 | bellard | printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
1333 | e6e5ad80 | bellard | #endif
|
1334 | e6e5ad80 | bellard | } |
1335 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
1336 | e6e5ad80 | bellard | } |
1337 | e6e5ad80 | bellard | |
1338 | e6e5ad80 | bellard | /***************************************
|
1339 | e6e5ad80 | bellard | *
|
1340 | e6e5ad80 | bellard | * I/O access at 0x3c9
|
1341 | e6e5ad80 | bellard | *
|
1342 | e6e5ad80 | bellard | ***************************************/
|
1343 | e6e5ad80 | bellard | |
1344 | e6e5ad80 | bellard | static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value) |
1345 | e6e5ad80 | bellard | { |
1346 | e6e5ad80 | bellard | if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
1347 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1348 | e6e5ad80 | bellard | if (s->dac_read_index < 0x10) { |
1349 | e6e5ad80 | bellard | *reg_value = |
1350 | e6e5ad80 | bellard | s->cirrus_hidden_palette[s->dac_read_index * 3 +
|
1351 | e6e5ad80 | bellard | s->dac_sub_index]; |
1352 | e6e5ad80 | bellard | } else {
|
1353 | e6e5ad80 | bellard | *reg_value = 0xff; /* XXX */ |
1354 | e6e5ad80 | bellard | } |
1355 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
1356 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
1357 | e6e5ad80 | bellard | s->dac_read_index++; |
1358 | e6e5ad80 | bellard | } |
1359 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1360 | e6e5ad80 | bellard | } |
1361 | e6e5ad80 | bellard | |
1362 | e6e5ad80 | bellard | static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value) |
1363 | e6e5ad80 | bellard | { |
1364 | e6e5ad80 | bellard | if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) |
1365 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1366 | e6e5ad80 | bellard | s->dac_cache[s->dac_sub_index] = reg_value; |
1367 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
1368 | e6e5ad80 | bellard | if (s->dac_read_index < 0x10) { |
1369 | e6e5ad80 | bellard | memcpy(&s->cirrus_hidden_palette[s->dac_write_index * 3],
|
1370 | e6e5ad80 | bellard | s->dac_cache, 3);
|
1371 | e6e5ad80 | bellard | /* XXX update cursor */
|
1372 | e6e5ad80 | bellard | } |
1373 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
1374 | e6e5ad80 | bellard | s->dac_write_index++; |
1375 | e6e5ad80 | bellard | } |
1376 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1377 | e6e5ad80 | bellard | } |
1378 | e6e5ad80 | bellard | |
1379 | e6e5ad80 | bellard | /***************************************
|
1380 | e6e5ad80 | bellard | *
|
1381 | e6e5ad80 | bellard | * I/O access between 0x3ce-0x3cf
|
1382 | e6e5ad80 | bellard | *
|
1383 | e6e5ad80 | bellard | ***************************************/
|
1384 | e6e5ad80 | bellard | |
1385 | e6e5ad80 | bellard | static int |
1386 | e6e5ad80 | bellard | cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1387 | e6e5ad80 | bellard | { |
1388 | e6e5ad80 | bellard | switch (reg_index) {
|
1389 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1390 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1391 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1392 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1393 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1394 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1395 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1396 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1397 | e6e5ad80 | bellard | default:
|
1398 | e6e5ad80 | bellard | break;
|
1399 | e6e5ad80 | bellard | } |
1400 | e6e5ad80 | bellard | |
1401 | e6e5ad80 | bellard | if (reg_index < 0x3a) { |
1402 | e6e5ad80 | bellard | *reg_value = s->gr[reg_index]; |
1403 | e6e5ad80 | bellard | } else {
|
1404 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1405 | e6e5ad80 | bellard | printf("cirrus: inport gr_index %02x\n", reg_index);
|
1406 | e6e5ad80 | bellard | #endif
|
1407 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1408 | e6e5ad80 | bellard | } |
1409 | e6e5ad80 | bellard | |
1410 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1411 | e6e5ad80 | bellard | } |
1412 | e6e5ad80 | bellard | |
1413 | e6e5ad80 | bellard | static int |
1414 | e6e5ad80 | bellard | cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1415 | e6e5ad80 | bellard | { |
1416 | e6e5ad80 | bellard | switch (reg_index) {
|
1417 | e6e5ad80 | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1418 | e6e5ad80 | bellard | s->gr[0x00] = reg_value;
|
1419 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1420 | e6e5ad80 | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1421 | e6e5ad80 | bellard | s->gr[0x01] = reg_value;
|
1422 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1423 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1424 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1425 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1426 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1427 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1428 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1429 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1430 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1431 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value & 0x7f;
|
1432 | e6e5ad80 | bellard | break;
|
1433 | e6e5ad80 | bellard | case 0x09: // bank offset #0 |
1434 | e6e5ad80 | bellard | case 0x0A: // bank offset #1 |
1435 | e6e5ad80 | bellard | case 0x0B: |
1436 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value; |
1437 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 0);
|
1438 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 1);
|
1439 | e6e5ad80 | bellard | break;
|
1440 | e6e5ad80 | bellard | case 0x10: // BGCOLOR 0x0000ff00 |
1441 | e6e5ad80 | bellard | case 0x11: // FGCOLOR 0x0000ff00 |
1442 | e6e5ad80 | bellard | case 0x12: // BGCOLOR 0x00ff0000 |
1443 | e6e5ad80 | bellard | case 0x13: // FGCOLOR 0x00ff0000 |
1444 | e6e5ad80 | bellard | case 0x14: // BGCOLOR 0xff000000 |
1445 | e6e5ad80 | bellard | case 0x15: // FGCOLOR 0xff000000 |
1446 | e6e5ad80 | bellard | case 0x20: // BLT WIDTH 0x0000ff |
1447 | e6e5ad80 | bellard | case 0x22: // BLT HEIGHT 0x0000ff |
1448 | e6e5ad80 | bellard | case 0x24: // BLT DEST PITCH 0x0000ff |
1449 | e6e5ad80 | bellard | case 0x26: // BLT SRC PITCH 0x0000ff |
1450 | e6e5ad80 | bellard | case 0x28: // BLT DEST ADDR 0x0000ff |
1451 | e6e5ad80 | bellard | case 0x29: // BLT DEST ADDR 0x00ff00 |
1452 | e6e5ad80 | bellard | case 0x2c: // BLT SRC ADDR 0x0000ff |
1453 | e6e5ad80 | bellard | case 0x2d: // BLT SRC ADDR 0x00ff00 |
1454 | e6e5ad80 | bellard | case 0x30: // BLT MODE |
1455 | e6e5ad80 | bellard | case 0x32: // RASTER OP |
1456 | e6e5ad80 | bellard | case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1457 | e6e5ad80 | bellard | case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
1458 | e6e5ad80 | bellard | case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
1459 | e6e5ad80 | bellard | case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
1460 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value; |
1461 | e6e5ad80 | bellard | break;
|
1462 | e6e5ad80 | bellard | case 0x21: // BLT WIDTH 0x001f00 |
1463 | e6e5ad80 | bellard | case 0x23: // BLT HEIGHT 0x001f00 |
1464 | e6e5ad80 | bellard | case 0x25: // BLT DEST PITCH 0x001f00 |
1465 | e6e5ad80 | bellard | case 0x27: // BLT SRC PITCH 0x001f00 |
1466 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value & 0x1f;
|
1467 | e6e5ad80 | bellard | break;
|
1468 | e6e5ad80 | bellard | case 0x2a: // BLT DEST ADDR 0x3f0000 |
1469 | e6e5ad80 | bellard | case 0x2e: // BLT SRC ADDR 0x3f0000 |
1470 | e6e5ad80 | bellard | s->gr[reg_index] = reg_value & 0x3f;
|
1471 | e6e5ad80 | bellard | break;
|
1472 | e6e5ad80 | bellard | case 0x31: // BLT STATUS/START |
1473 | e6e5ad80 | bellard | cirrus_write_bitblt(s, reg_value); |
1474 | e6e5ad80 | bellard | break;
|
1475 | e6e5ad80 | bellard | default:
|
1476 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1477 | e6e5ad80 | bellard | printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
1478 | e6e5ad80 | bellard | reg_value); |
1479 | e6e5ad80 | bellard | #endif
|
1480 | e6e5ad80 | bellard | break;
|
1481 | e6e5ad80 | bellard | } |
1482 | e6e5ad80 | bellard | |
1483 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1484 | e6e5ad80 | bellard | } |
1485 | e6e5ad80 | bellard | |
1486 | e6e5ad80 | bellard | /***************************************
|
1487 | e6e5ad80 | bellard | *
|
1488 | e6e5ad80 | bellard | * I/O access between 0x3d4-0x3d5
|
1489 | e6e5ad80 | bellard | *
|
1490 | e6e5ad80 | bellard | ***************************************/
|
1491 | e6e5ad80 | bellard | |
1492 | e6e5ad80 | bellard | static int |
1493 | e6e5ad80 | bellard | cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value) |
1494 | e6e5ad80 | bellard | { |
1495 | e6e5ad80 | bellard | switch (reg_index) {
|
1496 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1497 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1498 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1499 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1500 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1501 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1502 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1503 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1504 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1505 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1506 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1507 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1508 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1509 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1510 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1511 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1512 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1513 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1514 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1515 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1516 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1517 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1518 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1519 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1520 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1521 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1522 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1523 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1524 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1525 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1526 | e6e5ad80 | bellard | case 0x1d: // Overlay Extended Control |
1527 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1528 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1529 | e6e5ad80 | bellard | case 0x25: // Part Status |
1530 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1531 | e6e5ad80 | bellard | *reg_value = s->cr[reg_index]; |
1532 | e6e5ad80 | bellard | break;
|
1533 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1534 | e6e5ad80 | bellard | *reg_value = s->ar_index & 0x3f;
|
1535 | e6e5ad80 | bellard | break;
|
1536 | e6e5ad80 | bellard | default:
|
1537 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1538 | e6e5ad80 | bellard | printf("cirrus: inport cr_index %02x\n", reg_index);
|
1539 | e6e5ad80 | bellard | *reg_value = 0xff;
|
1540 | e6e5ad80 | bellard | #endif
|
1541 | e6e5ad80 | bellard | break;
|
1542 | e6e5ad80 | bellard | } |
1543 | e6e5ad80 | bellard | |
1544 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1545 | e6e5ad80 | bellard | } |
1546 | e6e5ad80 | bellard | |
1547 | e6e5ad80 | bellard | static int |
1548 | e6e5ad80 | bellard | cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1549 | e6e5ad80 | bellard | { |
1550 | e6e5ad80 | bellard | switch (reg_index) {
|
1551 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1552 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1553 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1554 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1555 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1556 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1557 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1558 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1559 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1560 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1561 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1562 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1563 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1564 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1565 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1566 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1567 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1568 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1569 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1570 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1571 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1572 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1573 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1574 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1575 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1576 | e6e5ad80 | bellard | return CIRRUS_HOOK_NOT_HANDLED;
|
1577 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1578 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1579 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1580 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1581 | e6e5ad80 | bellard | s->cr[reg_index] = reg_value; |
1582 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1583 | e6e5ad80 | bellard | printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
1584 | e6e5ad80 | bellard | reg_index, reg_value); |
1585 | e6e5ad80 | bellard | #endif
|
1586 | e6e5ad80 | bellard | break;
|
1587 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1588 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1589 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1590 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1591 | e6e5ad80 | bellard | break;
|
1592 | e6e5ad80 | bellard | case 0x1d: // Overlay Extended Control |
1593 | e6e5ad80 | bellard | case 0x25: // Part Status |
1594 | e6e5ad80 | bellard | default:
|
1595 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1596 | e6e5ad80 | bellard | printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
|
1597 | e6e5ad80 | bellard | reg_value); |
1598 | e6e5ad80 | bellard | #endif
|
1599 | e6e5ad80 | bellard | break;
|
1600 | e6e5ad80 | bellard | } |
1601 | e6e5ad80 | bellard | |
1602 | e6e5ad80 | bellard | return CIRRUS_HOOK_HANDLED;
|
1603 | e6e5ad80 | bellard | } |
1604 | e6e5ad80 | bellard | |
1605 | e6e5ad80 | bellard | /***************************************
|
1606 | e6e5ad80 | bellard | *
|
1607 | e6e5ad80 | bellard | * memory-mapped I/O (bitblt)
|
1608 | e6e5ad80 | bellard | *
|
1609 | e6e5ad80 | bellard | ***************************************/
|
1610 | e6e5ad80 | bellard | |
1611 | e6e5ad80 | bellard | static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
1612 | e6e5ad80 | bellard | { |
1613 | e6e5ad80 | bellard | int value = 0xff; |
1614 | e6e5ad80 | bellard | |
1615 | e6e5ad80 | bellard | switch (address) {
|
1616 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1617 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x00, &value);
|
1618 | e6e5ad80 | bellard | break;
|
1619 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1620 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x10, &value);
|
1621 | e6e5ad80 | bellard | break;
|
1622 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1623 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x12, &value);
|
1624 | e6e5ad80 | bellard | break;
|
1625 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1626 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x14, &value);
|
1627 | e6e5ad80 | bellard | break;
|
1628 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1629 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x01, &value);
|
1630 | e6e5ad80 | bellard | break;
|
1631 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1632 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x11, &value);
|
1633 | e6e5ad80 | bellard | break;
|
1634 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1635 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x13, &value);
|
1636 | e6e5ad80 | bellard | break;
|
1637 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1638 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x15, &value);
|
1639 | e6e5ad80 | bellard | break;
|
1640 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1641 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x20, &value);
|
1642 | e6e5ad80 | bellard | break;
|
1643 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1644 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x21, &value);
|
1645 | e6e5ad80 | bellard | break;
|
1646 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1647 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x22, &value);
|
1648 | e6e5ad80 | bellard | break;
|
1649 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1650 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x23, &value);
|
1651 | e6e5ad80 | bellard | break;
|
1652 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1653 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x24, &value);
|
1654 | e6e5ad80 | bellard | break;
|
1655 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1656 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x25, &value);
|
1657 | e6e5ad80 | bellard | break;
|
1658 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1659 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x26, &value);
|
1660 | e6e5ad80 | bellard | break;
|
1661 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1662 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x27, &value);
|
1663 | e6e5ad80 | bellard | break;
|
1664 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1665 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x28, &value);
|
1666 | e6e5ad80 | bellard | break;
|
1667 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1668 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x29, &value);
|
1669 | e6e5ad80 | bellard | break;
|
1670 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1671 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2a, &value);
|
1672 | e6e5ad80 | bellard | break;
|
1673 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1674 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2c, &value);
|
1675 | e6e5ad80 | bellard | break;
|
1676 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1677 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2d, &value);
|
1678 | e6e5ad80 | bellard | break;
|
1679 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1680 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2e, &value);
|
1681 | e6e5ad80 | bellard | break;
|
1682 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1683 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x2f, &value);
|
1684 | e6e5ad80 | bellard | break;
|
1685 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1686 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x30, &value);
|
1687 | e6e5ad80 | bellard | break;
|
1688 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1689 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x32, &value);
|
1690 | e6e5ad80 | bellard | break;
|
1691 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1692 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x34, &value);
|
1693 | e6e5ad80 | bellard | break;
|
1694 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1695 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x35, &value);
|
1696 | e6e5ad80 | bellard | break;
|
1697 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1698 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x38, &value);
|
1699 | e6e5ad80 | bellard | break;
|
1700 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1701 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x39, &value);
|
1702 | e6e5ad80 | bellard | break;
|
1703 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1704 | e6e5ad80 | bellard | cirrus_hook_read_gr(s, 0x31, &value);
|
1705 | e6e5ad80 | bellard | break;
|
1706 | e6e5ad80 | bellard | default:
|
1707 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1708 | e6e5ad80 | bellard | printf("cirrus: mmio read - address 0x%04x\n", address);
|
1709 | e6e5ad80 | bellard | #endif
|
1710 | e6e5ad80 | bellard | break;
|
1711 | e6e5ad80 | bellard | } |
1712 | e6e5ad80 | bellard | |
1713 | e6e5ad80 | bellard | return (uint8_t) value;
|
1714 | e6e5ad80 | bellard | } |
1715 | e6e5ad80 | bellard | |
1716 | e6e5ad80 | bellard | static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
1717 | e6e5ad80 | bellard | uint8_t value) |
1718 | e6e5ad80 | bellard | { |
1719 | e6e5ad80 | bellard | switch (address) {
|
1720 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1721 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x00, value);
|
1722 | e6e5ad80 | bellard | break;
|
1723 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1724 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x10, value);
|
1725 | e6e5ad80 | bellard | break;
|
1726 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1727 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x12, value);
|
1728 | e6e5ad80 | bellard | break;
|
1729 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1730 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x14, value);
|
1731 | e6e5ad80 | bellard | break;
|
1732 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1733 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x01, value);
|
1734 | e6e5ad80 | bellard | break;
|
1735 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1736 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x11, value);
|
1737 | e6e5ad80 | bellard | break;
|
1738 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1739 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x13, value);
|
1740 | e6e5ad80 | bellard | break;
|
1741 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1742 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x15, value);
|
1743 | e6e5ad80 | bellard | break;
|
1744 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1745 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x20, value);
|
1746 | e6e5ad80 | bellard | break;
|
1747 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1748 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x21, value);
|
1749 | e6e5ad80 | bellard | break;
|
1750 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1751 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x22, value);
|
1752 | e6e5ad80 | bellard | break;
|
1753 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1754 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x23, value);
|
1755 | e6e5ad80 | bellard | break;
|
1756 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1757 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x24, value);
|
1758 | e6e5ad80 | bellard | break;
|
1759 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1760 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x25, value);
|
1761 | e6e5ad80 | bellard | break;
|
1762 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1763 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x26, value);
|
1764 | e6e5ad80 | bellard | break;
|
1765 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1766 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x27, value);
|
1767 | e6e5ad80 | bellard | break;
|
1768 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1769 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x28, value);
|
1770 | e6e5ad80 | bellard | break;
|
1771 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1772 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x29, value);
|
1773 | e6e5ad80 | bellard | break;
|
1774 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1775 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2a, value);
|
1776 | e6e5ad80 | bellard | break;
|
1777 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 3): |
1778 | e6e5ad80 | bellard | /* ignored */
|
1779 | e6e5ad80 | bellard | break;
|
1780 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1781 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2c, value);
|
1782 | e6e5ad80 | bellard | break;
|
1783 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1784 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2d, value);
|
1785 | e6e5ad80 | bellard | break;
|
1786 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1787 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2e, value);
|
1788 | e6e5ad80 | bellard | break;
|
1789 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1790 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x2f, value);
|
1791 | e6e5ad80 | bellard | break;
|
1792 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1793 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x30, value);
|
1794 | e6e5ad80 | bellard | break;
|
1795 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1796 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x32, value);
|
1797 | e6e5ad80 | bellard | break;
|
1798 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1799 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x34, value);
|
1800 | e6e5ad80 | bellard | break;
|
1801 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1802 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x35, value);
|
1803 | e6e5ad80 | bellard | break;
|
1804 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1805 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x38, value);
|
1806 | e6e5ad80 | bellard | break;
|
1807 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1808 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x39, value);
|
1809 | e6e5ad80 | bellard | break;
|
1810 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1811 | e6e5ad80 | bellard | cirrus_hook_write_gr(s, 0x31, value);
|
1812 | e6e5ad80 | bellard | break;
|
1813 | e6e5ad80 | bellard | default:
|
1814 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1815 | e6e5ad80 | bellard | printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
1816 | e6e5ad80 | bellard | address, value); |
1817 | e6e5ad80 | bellard | #endif
|
1818 | e6e5ad80 | bellard | break;
|
1819 | e6e5ad80 | bellard | } |
1820 | e6e5ad80 | bellard | } |
1821 | e6e5ad80 | bellard | |
1822 | e6e5ad80 | bellard | /***************************************
|
1823 | e6e5ad80 | bellard | *
|
1824 | e6e5ad80 | bellard | * memory-mapped I/O (vga)
|
1825 | e6e5ad80 | bellard | *
|
1826 | e6e5ad80 | bellard | ***************************************/
|
1827 | e6e5ad80 | bellard | |
1828 | e6e5ad80 | bellard | static uint8_t cirrus_mmio_vga_read(CirrusVGAState * s, unsigned address) |
1829 | e6e5ad80 | bellard | { |
1830 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1831 | e6e5ad80 | bellard | printf("cirrus: mmio vga read (unimplemented) - address 0x%04x\n",
|
1832 | e6e5ad80 | bellard | address); |
1833 | e6e5ad80 | bellard | #endif
|
1834 | e6e5ad80 | bellard | return 0xff; |
1835 | e6e5ad80 | bellard | } |
1836 | e6e5ad80 | bellard | |
1837 | e6e5ad80 | bellard | static void cirrus_mmio_vga_write(CirrusVGAState * s, unsigned address, |
1838 | e6e5ad80 | bellard | uint8_t value) |
1839 | e6e5ad80 | bellard | { |
1840 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1841 | e6e5ad80 | bellard | printf |
1842 | e6e5ad80 | bellard | ("cirrus: mmio vga write (unimplemented) - address 0x%04x, value 0x%02x\n",
|
1843 | e6e5ad80 | bellard | address, value); |
1844 | e6e5ad80 | bellard | #endif
|
1845 | e6e5ad80 | bellard | } |
1846 | e6e5ad80 | bellard | |
1847 | e6e5ad80 | bellard | /***************************************
|
1848 | e6e5ad80 | bellard | *
|
1849 | e6e5ad80 | bellard | * write mode 4/5
|
1850 | e6e5ad80 | bellard | *
|
1851 | e6e5ad80 | bellard | * assume TARGET_PAGE_SIZE >= 16
|
1852 | e6e5ad80 | bellard | *
|
1853 | e6e5ad80 | bellard | ***************************************/
|
1854 | e6e5ad80 | bellard | |
1855 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
1856 | e6e5ad80 | bellard | unsigned mode,
|
1857 | e6e5ad80 | bellard | unsigned offset,
|
1858 | e6e5ad80 | bellard | uint32_t mem_value) |
1859 | e6e5ad80 | bellard | { |
1860 | e6e5ad80 | bellard | int x;
|
1861 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1862 | e6e5ad80 | bellard | uint8_t *dst; |
1863 | e6e5ad80 | bellard | |
1864 | e6e5ad80 | bellard | dst = s->vram_ptr + offset; |
1865 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1866 | e6e5ad80 | bellard | if (val & 0x80) { |
1867 | e6e5ad80 | bellard | *dst++ = s->gr[0x01];
|
1868 | e6e5ad80 | bellard | } else if (mode == 5) { |
1869 | e6e5ad80 | bellard | *dst++ = s->gr[0x00];
|
1870 | e6e5ad80 | bellard | } |
1871 | e6e5ad80 | bellard | val <<= 1;
|
1872 | e6e5ad80 | bellard | } |
1873 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset); |
1874 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
|
1875 | e6e5ad80 | bellard | } |
1876 | e6e5ad80 | bellard | |
1877 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
1878 | e6e5ad80 | bellard | unsigned mode,
|
1879 | e6e5ad80 | bellard | unsigned offset,
|
1880 | e6e5ad80 | bellard | uint32_t mem_value) |
1881 | e6e5ad80 | bellard | { |
1882 | e6e5ad80 | bellard | int x;
|
1883 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1884 | e6e5ad80 | bellard | uint8_t *dst; |
1885 | e6e5ad80 | bellard | |
1886 | e6e5ad80 | bellard | dst = s->vram_ptr + offset; |
1887 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1888 | e6e5ad80 | bellard | if (val & 0x80) { |
1889 | e6e5ad80 | bellard | *dst++ = s->gr[0x01];
|
1890 | e6e5ad80 | bellard | *dst++ = s->gr[0x11];
|
1891 | e6e5ad80 | bellard | } else if (mode == 5) { |
1892 | e6e5ad80 | bellard | *dst++ = s->gr[0x00];
|
1893 | e6e5ad80 | bellard | *dst++ = s->gr[0x10];
|
1894 | e6e5ad80 | bellard | } |
1895 | e6e5ad80 | bellard | val <<= 1;
|
1896 | e6e5ad80 | bellard | } |
1897 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset); |
1898 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
|
1899 | e6e5ad80 | bellard | } |
1900 | e6e5ad80 | bellard | |
1901 | e6e5ad80 | bellard | /***************************************
|
1902 | e6e5ad80 | bellard | *
|
1903 | e6e5ad80 | bellard | * memory access between 0xa0000-0xbffff
|
1904 | e6e5ad80 | bellard | *
|
1905 | e6e5ad80 | bellard | ***************************************/
|
1906 | e6e5ad80 | bellard | |
1907 | e6e5ad80 | bellard | static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr) |
1908 | e6e5ad80 | bellard | { |
1909 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1910 | e6e5ad80 | bellard | unsigned bank_index;
|
1911 | e6e5ad80 | bellard | unsigned bank_offset;
|
1912 | e6e5ad80 | bellard | uint32_t val; |
1913 | e6e5ad80 | bellard | |
1914 | e6e5ad80 | bellard | if ((s->sr[0x07] & 0x01) == 0) { |
1915 | e6e5ad80 | bellard | return vga_mem_readb(s, addr);
|
1916 | e6e5ad80 | bellard | } |
1917 | e6e5ad80 | bellard | |
1918 | e6e5ad80 | bellard | if (addr < 0x10000) { |
1919 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
1920 | e6e5ad80 | bellard | /* video memory */
|
1921 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
1922 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
1923 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1924 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
1925 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
1926 | e6e5ad80 | bellard | bank_offset <<= 4;
|
1927 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
1928 | e6e5ad80 | bellard | bank_offset <<= 3;
|
1929 | e6e5ad80 | bellard | } |
1930 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
1931 | e6e5ad80 | bellard | val = *(s->vram_ptr + bank_offset); |
1932 | e6e5ad80 | bellard | } else
|
1933 | e6e5ad80 | bellard | val = 0xff;
|
1934 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
1935 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
1936 | e6e5ad80 | bellard | val = 0xff;
|
1937 | e6e5ad80 | bellard | if ((s->sr[0x17] & 0x44) == 0x04) { |
1938 | e6e5ad80 | bellard | val = cirrus_mmio_blt_read(s, addr & 0xff);
|
1939 | e6e5ad80 | bellard | } |
1940 | e6e5ad80 | bellard | } else {
|
1941 | e6e5ad80 | bellard | val = 0xff;
|
1942 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1943 | e6e5ad80 | bellard | printf("cirrus: mem_readb %06x\n", addr);
|
1944 | e6e5ad80 | bellard | #endif
|
1945 | e6e5ad80 | bellard | } |
1946 | e6e5ad80 | bellard | return val;
|
1947 | e6e5ad80 | bellard | } |
1948 | e6e5ad80 | bellard | |
1949 | e6e5ad80 | bellard | static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr) |
1950 | e6e5ad80 | bellard | { |
1951 | e6e5ad80 | bellard | uint32_t v; |
1952 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1953 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr) << 8;
|
1954 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1);
|
1955 | e6e5ad80 | bellard | #else
|
1956 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr); |
1957 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
1958 | e6e5ad80 | bellard | #endif
|
1959 | e6e5ad80 | bellard | return v;
|
1960 | e6e5ad80 | bellard | } |
1961 | e6e5ad80 | bellard | |
1962 | e6e5ad80 | bellard | static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr) |
1963 | e6e5ad80 | bellard | { |
1964 | e6e5ad80 | bellard | uint32_t v; |
1965 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1966 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr) << 24;
|
1967 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16; |
1968 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8; |
1969 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 3);
|
1970 | e6e5ad80 | bellard | #else
|
1971 | e6e5ad80 | bellard | v = cirrus_vga_mem_readb(opaque, addr); |
1972 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8; |
1973 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16; |
1974 | e6e5ad80 | bellard | v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24; |
1975 | e6e5ad80 | bellard | #endif
|
1976 | e6e5ad80 | bellard | return v;
|
1977 | e6e5ad80 | bellard | } |
1978 | e6e5ad80 | bellard | |
1979 | e6e5ad80 | bellard | static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, |
1980 | e6e5ad80 | bellard | uint32_t mem_value) |
1981 | e6e5ad80 | bellard | { |
1982 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1983 | e6e5ad80 | bellard | unsigned bank_index;
|
1984 | e6e5ad80 | bellard | unsigned bank_offset;
|
1985 | e6e5ad80 | bellard | unsigned mode;
|
1986 | e6e5ad80 | bellard | |
1987 | e6e5ad80 | bellard | if ((s->sr[0x07] & 0x01) == 0) { |
1988 | e6e5ad80 | bellard | vga_mem_writeb(s, addr, mem_value); |
1989 | e6e5ad80 | bellard | return;
|
1990 | e6e5ad80 | bellard | } |
1991 | e6e5ad80 | bellard | |
1992 | e6e5ad80 | bellard | if (addr < 0x10000) { |
1993 | e6e5ad80 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
1994 | e6e5ad80 | bellard | /* bitblt */
|
1995 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) mem_value; |
1996 | e6e5ad80 | bellard | if (s->cirrus_srcptr == s->cirrus_srcptr_end) {
|
1997 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
1998 | e6e5ad80 | bellard | } |
1999 | e6e5ad80 | bellard | } else {
|
2000 | e6e5ad80 | bellard | /* video memory */
|
2001 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
2002 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
2003 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
2004 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
2005 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
2006 | e6e5ad80 | bellard | bank_offset <<= 4;
|
2007 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
2008 | e6e5ad80 | bellard | bank_offset <<= 3;
|
2009 | e6e5ad80 | bellard | } |
2010 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
2011 | e6e5ad80 | bellard | mode = s->gr[0x05] & 0x7; |
2012 | e6e5ad80 | bellard | if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
2013 | e6e5ad80 | bellard | *(s->vram_ptr + bank_offset) = mem_value; |
2014 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + |
2015 | e6e5ad80 | bellard | bank_offset); |
2016 | e6e5ad80 | bellard | } else {
|
2017 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) != 0x14) { |
2018 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
2019 | e6e5ad80 | bellard | bank_offset, |
2020 | e6e5ad80 | bellard | mem_value); |
2021 | e6e5ad80 | bellard | } else {
|
2022 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
2023 | e6e5ad80 | bellard | bank_offset, |
2024 | e6e5ad80 | bellard | mem_value); |
2025 | e6e5ad80 | bellard | } |
2026 | e6e5ad80 | bellard | } |
2027 | e6e5ad80 | bellard | } |
2028 | e6e5ad80 | bellard | } |
2029 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
2030 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2031 | e6e5ad80 | bellard | if ((s->sr[0x17] & 0x44) == 0x04) { |
2032 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
2033 | e6e5ad80 | bellard | } |
2034 | e6e5ad80 | bellard | } else {
|
2035 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
2036 | e6e5ad80 | bellard | printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
|
2037 | e6e5ad80 | bellard | #endif
|
2038 | e6e5ad80 | bellard | } |
2039 | e6e5ad80 | bellard | } |
2040 | e6e5ad80 | bellard | |
2041 | e6e5ad80 | bellard | static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
2042 | e6e5ad80 | bellard | { |
2043 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2044 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff); |
2045 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff); |
2046 | e6e5ad80 | bellard | #else
|
2047 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
2048 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2049 | e6e5ad80 | bellard | #endif
|
2050 | e6e5ad80 | bellard | } |
2051 | e6e5ad80 | bellard | |
2052 | e6e5ad80 | bellard | static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
2053 | e6e5ad80 | bellard | { |
2054 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2055 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff); |
2056 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2057 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2058 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff); |
2059 | e6e5ad80 | bellard | #else
|
2060 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
|
2061 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2062 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2063 | e6e5ad80 | bellard | cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2064 | e6e5ad80 | bellard | #endif
|
2065 | e6e5ad80 | bellard | } |
2066 | e6e5ad80 | bellard | |
2067 | e6e5ad80 | bellard | static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = { |
2068 | e6e5ad80 | bellard | cirrus_vga_mem_readb, |
2069 | e6e5ad80 | bellard | cirrus_vga_mem_readw, |
2070 | e6e5ad80 | bellard | cirrus_vga_mem_readl, |
2071 | e6e5ad80 | bellard | }; |
2072 | e6e5ad80 | bellard | |
2073 | e6e5ad80 | bellard | static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = { |
2074 | e6e5ad80 | bellard | cirrus_vga_mem_writeb, |
2075 | e6e5ad80 | bellard | cirrus_vga_mem_writew, |
2076 | e6e5ad80 | bellard | cirrus_vga_mem_writel, |
2077 | e6e5ad80 | bellard | }; |
2078 | e6e5ad80 | bellard | |
2079 | e6e5ad80 | bellard | /***************************************
|
2080 | e6e5ad80 | bellard | *
|
2081 | e6e5ad80 | bellard | * LFB memory access
|
2082 | e6e5ad80 | bellard | *
|
2083 | e6e5ad80 | bellard | ***************************************/
|
2084 | e6e5ad80 | bellard | |
2085 | e6e5ad80 | bellard | static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr) |
2086 | e6e5ad80 | bellard | { |
2087 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2088 | e6e5ad80 | bellard | uint32_t ret; |
2089 | e6e5ad80 | bellard | |
2090 | e6e5ad80 | bellard | /* XXX: s->vram_size must be a power of two */
|
2091 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2092 | e6e5ad80 | bellard | |
2093 | e6e5ad80 | bellard | if (((s->sr[0x17] & 0x44) == 0x44) && ((addr & 0x1fff00) == 0x1fff00)) { |
2094 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2095 | e6e5ad80 | bellard | ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
2096 | e6e5ad80 | bellard | } else if (0) { |
2097 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
2098 | e6e5ad80 | bellard | ret = 0xff;
|
2099 | e6e5ad80 | bellard | } else {
|
2100 | e6e5ad80 | bellard | /* video memory */
|
2101 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
2102 | e6e5ad80 | bellard | addr <<= 4;
|
2103 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
2104 | e6e5ad80 | bellard | addr <<= 3;
|
2105 | e6e5ad80 | bellard | } |
2106 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2107 | e6e5ad80 | bellard | ret = *(s->vram_ptr + addr); |
2108 | e6e5ad80 | bellard | } |
2109 | e6e5ad80 | bellard | |
2110 | e6e5ad80 | bellard | return ret;
|
2111 | e6e5ad80 | bellard | } |
2112 | e6e5ad80 | bellard | |
2113 | e6e5ad80 | bellard | static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr) |
2114 | e6e5ad80 | bellard | { |
2115 | e6e5ad80 | bellard | uint32_t v; |
2116 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2117 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr) << 8;
|
2118 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1);
|
2119 | e6e5ad80 | bellard | #else
|
2120 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr); |
2121 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2122 | e6e5ad80 | bellard | #endif
|
2123 | e6e5ad80 | bellard | return v;
|
2124 | e6e5ad80 | bellard | } |
2125 | e6e5ad80 | bellard | |
2126 | e6e5ad80 | bellard | static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr) |
2127 | e6e5ad80 | bellard | { |
2128 | e6e5ad80 | bellard | uint32_t v; |
2129 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2130 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr) << 24;
|
2131 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 16; |
2132 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 2) << 8; |
2133 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 3);
|
2134 | e6e5ad80 | bellard | #else
|
2135 | e6e5ad80 | bellard | v = cirrus_linear_readb(opaque, addr); |
2136 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 1) << 8; |
2137 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 2) << 16; |
2138 | e6e5ad80 | bellard | v |= cirrus_linear_readb(opaque, addr + 3) << 24; |
2139 | e6e5ad80 | bellard | #endif
|
2140 | e6e5ad80 | bellard | return v;
|
2141 | e6e5ad80 | bellard | } |
2142 | e6e5ad80 | bellard | |
2143 | e6e5ad80 | bellard | static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, |
2144 | e6e5ad80 | bellard | uint32_t val) |
2145 | e6e5ad80 | bellard | { |
2146 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2147 | e6e5ad80 | bellard | unsigned mode;
|
2148 | e6e5ad80 | bellard | |
2149 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2150 | e6e5ad80 | bellard | |
2151 | e6e5ad80 | bellard | if (((s->sr[0x17] & 0x44) == 0x44) && ((addr & 0x1fff00) == 0x1fff00)) { |
2152 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2153 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, val);
|
2154 | e6e5ad80 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2155 | e6e5ad80 | bellard | /* bitblt */
|
2156 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2157 | e6e5ad80 | bellard | if (s->cirrus_srcptr == s->cirrus_srcptr_end) {
|
2158 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2159 | e6e5ad80 | bellard | } |
2160 | e6e5ad80 | bellard | } else {
|
2161 | e6e5ad80 | bellard | /* video memory */
|
2162 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) == 0x14) { |
2163 | e6e5ad80 | bellard | addr <<= 4;
|
2164 | e6e5ad80 | bellard | } else if (s->gr[0x0B] & 0x02) { |
2165 | e6e5ad80 | bellard | addr <<= 3;
|
2166 | e6e5ad80 | bellard | } |
2167 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2168 | e6e5ad80 | bellard | |
2169 | e6e5ad80 | bellard | mode = s->gr[0x05] & 0x7; |
2170 | e6e5ad80 | bellard | if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) { |
2171 | e6e5ad80 | bellard | *(s->vram_ptr + addr) = (uint8_t) val; |
2172 | e6e5ad80 | bellard | cpu_physical_memory_set_dirty(s->vram_offset + addr); |
2173 | e6e5ad80 | bellard | } else {
|
2174 | e6e5ad80 | bellard | if ((s->gr[0x0B] & 0x14) != 0x14) { |
2175 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2176 | e6e5ad80 | bellard | } else {
|
2177 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
2178 | e6e5ad80 | bellard | } |
2179 | e6e5ad80 | bellard | } |
2180 | e6e5ad80 | bellard | } |
2181 | e6e5ad80 | bellard | } |
2182 | e6e5ad80 | bellard | |
2183 | e6e5ad80 | bellard | static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr, |
2184 | e6e5ad80 | bellard | uint32_t val) |
2185 | e6e5ad80 | bellard | { |
2186 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2187 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff); |
2188 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, val & 0xff); |
2189 | e6e5ad80 | bellard | #else
|
2190 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2191 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2192 | e6e5ad80 | bellard | #endif
|
2193 | e6e5ad80 | bellard | } |
2194 | e6e5ad80 | bellard | |
2195 | e6e5ad80 | bellard | static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, |
2196 | e6e5ad80 | bellard | uint32_t val) |
2197 | e6e5ad80 | bellard | { |
2198 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2199 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff); |
2200 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2201 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2202 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 3, val & 0xff); |
2203 | e6e5ad80 | bellard | #else
|
2204 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr, val & 0xff);
|
2205 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2206 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2207 | e6e5ad80 | bellard | cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2208 | e6e5ad80 | bellard | #endif
|
2209 | e6e5ad80 | bellard | } |
2210 | e6e5ad80 | bellard | |
2211 | e6e5ad80 | bellard | |
2212 | e6e5ad80 | bellard | static CPUReadMemoryFunc *cirrus_linear_read[3] = { |
2213 | e6e5ad80 | bellard | cirrus_linear_readb, |
2214 | e6e5ad80 | bellard | cirrus_linear_readw, |
2215 | e6e5ad80 | bellard | cirrus_linear_readl, |
2216 | e6e5ad80 | bellard | }; |
2217 | e6e5ad80 | bellard | |
2218 | e6e5ad80 | bellard | static CPUWriteMemoryFunc *cirrus_linear_write[3] = { |
2219 | e6e5ad80 | bellard | cirrus_linear_writeb, |
2220 | e6e5ad80 | bellard | cirrus_linear_writew, |
2221 | e6e5ad80 | bellard | cirrus_linear_writel, |
2222 | e6e5ad80 | bellard | }; |
2223 | e6e5ad80 | bellard | |
2224 | e6e5ad80 | bellard | /***************************************
|
2225 | e6e5ad80 | bellard | *
|
2226 | e6e5ad80 | bellard | * memory-mapped I/O access
|
2227 | e6e5ad80 | bellard | *
|
2228 | e6e5ad80 | bellard | ***************************************/
|
2229 | e6e5ad80 | bellard | |
2230 | e6e5ad80 | bellard | static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) |
2231 | e6e5ad80 | bellard | { |
2232 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2233 | e6e5ad80 | bellard | |
2234 | e6e5ad80 | bellard | addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2235 | e6e5ad80 | bellard | /* ??? Does CLGD5430 have memory-mapped VGA registers ??? */
|
2236 | e6e5ad80 | bellard | return (addr >= 0x100) ? |
2237 | e6e5ad80 | bellard | cirrus_mmio_blt_read(s, addr - 0x100) :
|
2238 | e6e5ad80 | bellard | cirrus_mmio_vga_read(s, addr); |
2239 | e6e5ad80 | bellard | } |
2240 | e6e5ad80 | bellard | |
2241 | e6e5ad80 | bellard | static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr) |
2242 | e6e5ad80 | bellard | { |
2243 | e6e5ad80 | bellard | uint32_t v; |
2244 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2245 | e6e5ad80 | bellard | v = cirrus_mmio_readb(opaque, addr) << 8;
|
2246 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1);
|
2247 | e6e5ad80 | bellard | #else
|
2248 | e6e5ad80 | bellard | v = cirrus_mmio_readb(opaque, addr); |
2249 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2250 | e6e5ad80 | bellard | #endif
|
2251 | e6e5ad80 | bellard | return v;
|
2252 | e6e5ad80 | bellard | } |
2253 | e6e5ad80 | bellard | |
2254 | e6e5ad80 | bellard | static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr) |
2255 | e6e5ad80 | bellard | { |
2256 | e6e5ad80 | bellard | uint32_t v; |
2257 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2258 | e6e5ad80 | bellard | v = cirrus_mmio_readb(opaque, addr) << 24;
|
2259 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 16; |
2260 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 2) << 8; |
2261 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 3);
|
2262 | e6e5ad80 | bellard | #else
|
2263 | e6e5ad80 | bellard | v = cirrus_mmio_readb(opaque, addr); |
2264 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 1) << 8; |
2265 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 2) << 16; |
2266 | e6e5ad80 | bellard | v |= cirrus_mmio_readb(opaque, addr + 3) << 24; |
2267 | e6e5ad80 | bellard | #endif
|
2268 | e6e5ad80 | bellard | return v;
|
2269 | e6e5ad80 | bellard | } |
2270 | e6e5ad80 | bellard | |
2271 | e6e5ad80 | bellard | static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, |
2272 | e6e5ad80 | bellard | uint32_t val) |
2273 | e6e5ad80 | bellard | { |
2274 | e6e5ad80 | bellard | CirrusVGAState *s = (CirrusVGAState *) opaque; |
2275 | e6e5ad80 | bellard | |
2276 | e6e5ad80 | bellard | addr &= CIRRUS_PNPMMIO_SIZE - 1;
|
2277 | e6e5ad80 | bellard | /* ??? Does CLGD5430 have memory-mapped VGA registers ??? */
|
2278 | e6e5ad80 | bellard | if (addr >= 0x100) { |
2279 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr - 0x100, val);
|
2280 | e6e5ad80 | bellard | } else {
|
2281 | e6e5ad80 | bellard | cirrus_mmio_vga_write(s, addr, val); |
2282 | e6e5ad80 | bellard | } |
2283 | e6e5ad80 | bellard | } |
2284 | e6e5ad80 | bellard | |
2285 | e6e5ad80 | bellard | static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr, |
2286 | e6e5ad80 | bellard | uint32_t val) |
2287 | e6e5ad80 | bellard | { |
2288 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2289 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff); |
2290 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 1, val & 0xff); |
2291 | e6e5ad80 | bellard | #else
|
2292 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2293 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2294 | e6e5ad80 | bellard | #endif
|
2295 | e6e5ad80 | bellard | } |
2296 | e6e5ad80 | bellard | |
2297 | e6e5ad80 | bellard | static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, |
2298 | e6e5ad80 | bellard | uint32_t val) |
2299 | e6e5ad80 | bellard | { |
2300 | e6e5ad80 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
2301 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff); |
2302 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff); |
2303 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff); |
2304 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 3, val & 0xff); |
2305 | e6e5ad80 | bellard | #else
|
2306 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr, val & 0xff);
|
2307 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
2308 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
2309 | e6e5ad80 | bellard | cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
2310 | e6e5ad80 | bellard | #endif
|
2311 | e6e5ad80 | bellard | } |
2312 | e6e5ad80 | bellard | |
2313 | e6e5ad80 | bellard | |
2314 | e6e5ad80 | bellard | static CPUReadMemoryFunc *cirrus_mmio_read[3] = { |
2315 | e6e5ad80 | bellard | cirrus_mmio_readb, |
2316 | e6e5ad80 | bellard | cirrus_mmio_readw, |
2317 | e6e5ad80 | bellard | cirrus_mmio_readl, |
2318 | e6e5ad80 | bellard | }; |
2319 | e6e5ad80 | bellard | |
2320 | e6e5ad80 | bellard | static CPUWriteMemoryFunc *cirrus_mmio_write[3] = { |
2321 | e6e5ad80 | bellard | cirrus_mmio_writeb, |
2322 | e6e5ad80 | bellard | cirrus_mmio_writew, |
2323 | e6e5ad80 | bellard | cirrus_mmio_writel, |
2324 | e6e5ad80 | bellard | }; |
2325 | e6e5ad80 | bellard | |
2326 | e6e5ad80 | bellard | /* I/O ports */
|
2327 | e6e5ad80 | bellard | |
2328 | e6e5ad80 | bellard | static uint32_t vga_ioport_read(void *opaque, uint32_t addr) |
2329 | e6e5ad80 | bellard | { |
2330 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2331 | e6e5ad80 | bellard | int val, index;
|
2332 | e6e5ad80 | bellard | |
2333 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2334 | e6e5ad80 | bellard | if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) |
2335 | e6e5ad80 | bellard | || (addr >= 0x3d0 && addr <= 0x3df |
2336 | e6e5ad80 | bellard | && !(s->msr & MSR_COLOR_EMULATION))) { |
2337 | e6e5ad80 | bellard | val = 0xff;
|
2338 | e6e5ad80 | bellard | } else {
|
2339 | e6e5ad80 | bellard | switch (addr) {
|
2340 | e6e5ad80 | bellard | case 0x3c0: |
2341 | e6e5ad80 | bellard | if (s->ar_flip_flop == 0) { |
2342 | e6e5ad80 | bellard | val = s->ar_index; |
2343 | e6e5ad80 | bellard | } else {
|
2344 | e6e5ad80 | bellard | val = 0;
|
2345 | e6e5ad80 | bellard | } |
2346 | e6e5ad80 | bellard | break;
|
2347 | e6e5ad80 | bellard | case 0x3c1: |
2348 | e6e5ad80 | bellard | index = s->ar_index & 0x1f;
|
2349 | e6e5ad80 | bellard | if (index < 21) |
2350 | e6e5ad80 | bellard | val = s->ar[index]; |
2351 | e6e5ad80 | bellard | else
|
2352 | e6e5ad80 | bellard | val = 0;
|
2353 | e6e5ad80 | bellard | break;
|
2354 | e6e5ad80 | bellard | case 0x3c2: |
2355 | e6e5ad80 | bellard | val = s->st00; |
2356 | e6e5ad80 | bellard | break;
|
2357 | e6e5ad80 | bellard | case 0x3c4: |
2358 | e6e5ad80 | bellard | val = s->sr_index; |
2359 | e6e5ad80 | bellard | break;
|
2360 | e6e5ad80 | bellard | case 0x3c5: |
2361 | e6e5ad80 | bellard | if (cirrus_hook_read_sr(s, s->sr_index, &val))
|
2362 | e6e5ad80 | bellard | break;
|
2363 | e6e5ad80 | bellard | val = s->sr[s->sr_index]; |
2364 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2365 | e6e5ad80 | bellard | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
2366 | e6e5ad80 | bellard | #endif
|
2367 | e6e5ad80 | bellard | break;
|
2368 | e6e5ad80 | bellard | case 0x3c6: |
2369 | e6e5ad80 | bellard | cirrus_read_hidden_dac(s, &val); |
2370 | e6e5ad80 | bellard | break;
|
2371 | e6e5ad80 | bellard | case 0x3c7: |
2372 | e6e5ad80 | bellard | val = s->dac_state; |
2373 | e6e5ad80 | bellard | break;
|
2374 | e6e5ad80 | bellard | case 0x3c9: |
2375 | e6e5ad80 | bellard | if (cirrus_hook_read_palette(s, &val))
|
2376 | e6e5ad80 | bellard | break;
|
2377 | e6e5ad80 | bellard | val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
|
2378 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
2379 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2380 | e6e5ad80 | bellard | s->dac_read_index++; |
2381 | e6e5ad80 | bellard | } |
2382 | e6e5ad80 | bellard | break;
|
2383 | e6e5ad80 | bellard | case 0x3ca: |
2384 | e6e5ad80 | bellard | val = s->fcr; |
2385 | e6e5ad80 | bellard | break;
|
2386 | e6e5ad80 | bellard | case 0x3cc: |
2387 | e6e5ad80 | bellard | val = s->msr; |
2388 | e6e5ad80 | bellard | break;
|
2389 | e6e5ad80 | bellard | case 0x3ce: |
2390 | e6e5ad80 | bellard | val = s->gr_index; |
2391 | e6e5ad80 | bellard | break;
|
2392 | e6e5ad80 | bellard | case 0x3cf: |
2393 | e6e5ad80 | bellard | if (cirrus_hook_read_gr(s, s->gr_index, &val))
|
2394 | e6e5ad80 | bellard | break;
|
2395 | e6e5ad80 | bellard | val = s->gr[s->gr_index]; |
2396 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2397 | e6e5ad80 | bellard | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
2398 | e6e5ad80 | bellard | #endif
|
2399 | e6e5ad80 | bellard | break;
|
2400 | e6e5ad80 | bellard | case 0x3b4: |
2401 | e6e5ad80 | bellard | case 0x3d4: |
2402 | e6e5ad80 | bellard | val = s->cr_index; |
2403 | e6e5ad80 | bellard | break;
|
2404 | e6e5ad80 | bellard | case 0x3b5: |
2405 | e6e5ad80 | bellard | case 0x3d5: |
2406 | e6e5ad80 | bellard | if (cirrus_hook_read_cr(s, s->cr_index, &val))
|
2407 | e6e5ad80 | bellard | break;
|
2408 | e6e5ad80 | bellard | val = s->cr[s->cr_index]; |
2409 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2410 | e6e5ad80 | bellard | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
2411 | e6e5ad80 | bellard | #endif
|
2412 | e6e5ad80 | bellard | #ifdef DEBUG_S3
|
2413 | e6e5ad80 | bellard | if (s->cr_index >= 0x20) |
2414 | e6e5ad80 | bellard | printf("S3: CR read index=0x%x val=0x%x\n",
|
2415 | e6e5ad80 | bellard | s->cr_index, val); |
2416 | e6e5ad80 | bellard | #endif
|
2417 | e6e5ad80 | bellard | break;
|
2418 | e6e5ad80 | bellard | case 0x3ba: |
2419 | e6e5ad80 | bellard | case 0x3da: |
2420 | e6e5ad80 | bellard | /* just toggle to fool polling */
|
2421 | e6e5ad80 | bellard | s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE; |
2422 | e6e5ad80 | bellard | val = s->st01; |
2423 | e6e5ad80 | bellard | s->ar_flip_flop = 0;
|
2424 | e6e5ad80 | bellard | break;
|
2425 | e6e5ad80 | bellard | default:
|
2426 | e6e5ad80 | bellard | val = 0x00;
|
2427 | e6e5ad80 | bellard | break;
|
2428 | e6e5ad80 | bellard | } |
2429 | e6e5ad80 | bellard | } |
2430 | e6e5ad80 | bellard | #if defined(DEBUG_VGA)
|
2431 | e6e5ad80 | bellard | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
2432 | e6e5ad80 | bellard | #endif
|
2433 | e6e5ad80 | bellard | return val;
|
2434 | e6e5ad80 | bellard | } |
2435 | e6e5ad80 | bellard | |
2436 | e6e5ad80 | bellard | static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
2437 | e6e5ad80 | bellard | { |
2438 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2439 | e6e5ad80 | bellard | int index;
|
2440 | e6e5ad80 | bellard | |
2441 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2442 | e6e5ad80 | bellard | if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) |
2443 | e6e5ad80 | bellard | || (addr >= 0x3d0 && addr <= 0x3df |
2444 | e6e5ad80 | bellard | && !(s->msr & MSR_COLOR_EMULATION))) |
2445 | e6e5ad80 | bellard | return;
|
2446 | e6e5ad80 | bellard | |
2447 | e6e5ad80 | bellard | #ifdef DEBUG_VGA
|
2448 | e6e5ad80 | bellard | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
2449 | e6e5ad80 | bellard | #endif
|
2450 | e6e5ad80 | bellard | |
2451 | e6e5ad80 | bellard | switch (addr) {
|
2452 | e6e5ad80 | bellard | case 0x3c0: |
2453 | e6e5ad80 | bellard | if (s->ar_flip_flop == 0) { |
2454 | e6e5ad80 | bellard | val &= 0x3f;
|
2455 | e6e5ad80 | bellard | s->ar_index = val; |
2456 | e6e5ad80 | bellard | } else {
|
2457 | e6e5ad80 | bellard | index = s->ar_index & 0x1f;
|
2458 | e6e5ad80 | bellard | switch (index) {
|
2459 | e6e5ad80 | bellard | case 0x00 ... 0x0f: |
2460 | e6e5ad80 | bellard | s->ar[index] = val & 0x3f;
|
2461 | e6e5ad80 | bellard | break;
|
2462 | e6e5ad80 | bellard | case 0x10: |
2463 | e6e5ad80 | bellard | s->ar[index] = val & ~0x10;
|
2464 | e6e5ad80 | bellard | break;
|
2465 | e6e5ad80 | bellard | case 0x11: |
2466 | e6e5ad80 | bellard | s->ar[index] = val; |
2467 | e6e5ad80 | bellard | break;
|
2468 | e6e5ad80 | bellard | case 0x12: |
2469 | e6e5ad80 | bellard | s->ar[index] = val & ~0xc0;
|
2470 | e6e5ad80 | bellard | break;
|
2471 | e6e5ad80 | bellard | case 0x13: |
2472 | e6e5ad80 | bellard | s->ar[index] = val & ~0xf0;
|
2473 | e6e5ad80 | bellard | break;
|
2474 | e6e5ad80 | bellard | case 0x14: |
2475 | e6e5ad80 | bellard | s->ar[index] = val & ~0xf0;
|
2476 | e6e5ad80 | bellard | break;
|
2477 | e6e5ad80 | bellard | default:
|
2478 | e6e5ad80 | bellard | break;
|
2479 | e6e5ad80 | bellard | } |
2480 | e6e5ad80 | bellard | } |
2481 | e6e5ad80 | bellard | s->ar_flip_flop ^= 1;
|
2482 | e6e5ad80 | bellard | break;
|
2483 | e6e5ad80 | bellard | case 0x3c2: |
2484 | e6e5ad80 | bellard | s->msr = val & ~0x10;
|
2485 | e6e5ad80 | bellard | break;
|
2486 | e6e5ad80 | bellard | case 0x3c4: |
2487 | e6e5ad80 | bellard | s->sr_index = val; |
2488 | e6e5ad80 | bellard | break;
|
2489 | e6e5ad80 | bellard | case 0x3c5: |
2490 | e6e5ad80 | bellard | if (cirrus_hook_write_sr(s, s->sr_index, val))
|
2491 | e6e5ad80 | bellard | break;
|
2492 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2493 | e6e5ad80 | bellard | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
2494 | e6e5ad80 | bellard | #endif
|
2495 | e6e5ad80 | bellard | s->sr[s->sr_index] = val & sr_mask[s->sr_index]; |
2496 | e6e5ad80 | bellard | break;
|
2497 | e6e5ad80 | bellard | case 0x3c6: |
2498 | e6e5ad80 | bellard | cirrus_write_hidden_dac(s, val); |
2499 | e6e5ad80 | bellard | break;
|
2500 | e6e5ad80 | bellard | case 0x3c7: |
2501 | e6e5ad80 | bellard | s->dac_read_index = val; |
2502 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2503 | e6e5ad80 | bellard | s->dac_state = 3;
|
2504 | e6e5ad80 | bellard | break;
|
2505 | e6e5ad80 | bellard | case 0x3c8: |
2506 | e6e5ad80 | bellard | s->dac_write_index = val; |
2507 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2508 | e6e5ad80 | bellard | s->dac_state = 0;
|
2509 | e6e5ad80 | bellard | break;
|
2510 | e6e5ad80 | bellard | case 0x3c9: |
2511 | e6e5ad80 | bellard | if (cirrus_hook_write_palette(s, val))
|
2512 | e6e5ad80 | bellard | break;
|
2513 | e6e5ad80 | bellard | s->dac_cache[s->dac_sub_index] = val; |
2514 | e6e5ad80 | bellard | if (++s->dac_sub_index == 3) { |
2515 | e6e5ad80 | bellard | memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); |
2516 | e6e5ad80 | bellard | s->dac_sub_index = 0;
|
2517 | e6e5ad80 | bellard | s->dac_write_index++; |
2518 | e6e5ad80 | bellard | } |
2519 | e6e5ad80 | bellard | break;
|
2520 | e6e5ad80 | bellard | case 0x3ce: |
2521 | e6e5ad80 | bellard | s->gr_index = val; |
2522 | e6e5ad80 | bellard | break;
|
2523 | e6e5ad80 | bellard | case 0x3cf: |
2524 | e6e5ad80 | bellard | if (cirrus_hook_write_gr(s, s->gr_index, val))
|
2525 | e6e5ad80 | bellard | break;
|
2526 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2527 | e6e5ad80 | bellard | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
2528 | e6e5ad80 | bellard | #endif
|
2529 | e6e5ad80 | bellard | s->gr[s->gr_index] = val & gr_mask[s->gr_index]; |
2530 | e6e5ad80 | bellard | break;
|
2531 | e6e5ad80 | bellard | case 0x3b4: |
2532 | e6e5ad80 | bellard | case 0x3d4: |
2533 | e6e5ad80 | bellard | s->cr_index = val; |
2534 | e6e5ad80 | bellard | break;
|
2535 | e6e5ad80 | bellard | case 0x3b5: |
2536 | e6e5ad80 | bellard | case 0x3d5: |
2537 | e6e5ad80 | bellard | if (cirrus_hook_write_cr(s, s->cr_index, val))
|
2538 | e6e5ad80 | bellard | break;
|
2539 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2540 | e6e5ad80 | bellard | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
2541 | e6e5ad80 | bellard | #endif
|
2542 | e6e5ad80 | bellard | /* handle CR0-7 protection */
|
2543 | e6e5ad80 | bellard | if ((s->cr[11] & 0x80) && s->cr_index <= 7) { |
2544 | e6e5ad80 | bellard | /* can always write bit 4 of CR7 */
|
2545 | e6e5ad80 | bellard | if (s->cr_index == 7) |
2546 | e6e5ad80 | bellard | s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10); |
2547 | e6e5ad80 | bellard | return;
|
2548 | e6e5ad80 | bellard | } |
2549 | e6e5ad80 | bellard | switch (s->cr_index) {
|
2550 | e6e5ad80 | bellard | case 0x01: /* horizontal display end */ |
2551 | e6e5ad80 | bellard | case 0x07: |
2552 | e6e5ad80 | bellard | case 0x09: |
2553 | e6e5ad80 | bellard | case 0x0c: |
2554 | e6e5ad80 | bellard | case 0x0d: |
2555 | e6e5ad80 | bellard | case 0x12: /* veritcal display end */ |
2556 | e6e5ad80 | bellard | s->cr[s->cr_index] = val; |
2557 | e6e5ad80 | bellard | break;
|
2558 | e6e5ad80 | bellard | |
2559 | e6e5ad80 | bellard | default:
|
2560 | e6e5ad80 | bellard | s->cr[s->cr_index] = val; |
2561 | e6e5ad80 | bellard | break;
|
2562 | e6e5ad80 | bellard | } |
2563 | e6e5ad80 | bellard | break;
|
2564 | e6e5ad80 | bellard | case 0x3ba: |
2565 | e6e5ad80 | bellard | case 0x3da: |
2566 | e6e5ad80 | bellard | s->fcr = val & 0x10;
|
2567 | e6e5ad80 | bellard | break;
|
2568 | e6e5ad80 | bellard | } |
2569 | e6e5ad80 | bellard | } |
2570 | e6e5ad80 | bellard | |
2571 | e6e5ad80 | bellard | /***************************************
|
2572 | e6e5ad80 | bellard | *
|
2573 | e6e5ad80 | bellard | * initialize
|
2574 | e6e5ad80 | bellard | *
|
2575 | e6e5ad80 | bellard | ***************************************/
|
2576 | e6e5ad80 | bellard | |
2577 | e6e5ad80 | bellard | static void cirrus_init_common(CirrusVGAState * s) |
2578 | e6e5ad80 | bellard | { |
2579 | e6e5ad80 | bellard | int vga_io_memory;
|
2580 | e6e5ad80 | bellard | |
2581 | e6e5ad80 | bellard | register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s); |
2582 | e6e5ad80 | bellard | |
2583 | e6e5ad80 | bellard | register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s); |
2584 | e6e5ad80 | bellard | register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s); |
2585 | e6e5ad80 | bellard | register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s); |
2586 | e6e5ad80 | bellard | register_ioport_write(0x3da, 1, 1, vga_ioport_write, s); |
2587 | e6e5ad80 | bellard | |
2588 | e6e5ad80 | bellard | register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s); |
2589 | e6e5ad80 | bellard | |
2590 | e6e5ad80 | bellard | register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s); |
2591 | e6e5ad80 | bellard | register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); |
2592 | e6e5ad80 | bellard | register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); |
2593 | e6e5ad80 | bellard | register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); |
2594 | e6e5ad80 | bellard | |
2595 | e6e5ad80 | bellard | vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
|
2596 | e6e5ad80 | bellard | cirrus_vga_mem_write, s); |
2597 | e6e5ad80 | bellard | cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000, |
2598 | e6e5ad80 | bellard | vga_io_memory); |
2599 | e6e5ad80 | bellard | |
2600 | e6e5ad80 | bellard | s->sr[0x06] = 0x0f; |
2601 | e6e5ad80 | bellard | s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
2602 | e6e5ad80 | bellard | s->sr[0x1F] = 0x22; // MemClock |
2603 | e6e5ad80 | bellard | |
2604 | e6e5ad80 | bellard | s->cr[0x27] = CIRRUS_ID_CLGD5430;
|
2605 | e6e5ad80 | bellard | |
2606 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 5;
|
2607 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = 0;
|
2608 | e6e5ad80 | bellard | |
2609 | e6e5ad80 | bellard | /* I/O handler for LFB */
|
2610 | e6e5ad80 | bellard | s->cirrus_linear_io_addr = |
2611 | e6e5ad80 | bellard | cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
|
2612 | e6e5ad80 | bellard | s); |
2613 | e6e5ad80 | bellard | /* I/O handler for memory-mapped I/O */
|
2614 | e6e5ad80 | bellard | s->cirrus_mmio_io_addr = |
2615 | e6e5ad80 | bellard | cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
|
2616 | e6e5ad80 | bellard | |
2617 | e6e5ad80 | bellard | /* XXX: s->vram_size must be a power of two */
|
2618 | e6e5ad80 | bellard | s->cirrus_addr_mask = s->vram_size - 1;
|
2619 | e6e5ad80 | bellard | |
2620 | e6e5ad80 | bellard | s->get_bpp = cirrus_get_bpp; |
2621 | e6e5ad80 | bellard | s->get_offsets = cirrus_get_offsets; |
2622 | e6e5ad80 | bellard | } |
2623 | e6e5ad80 | bellard | |
2624 | e6e5ad80 | bellard | /***************************************
|
2625 | e6e5ad80 | bellard | *
|
2626 | e6e5ad80 | bellard | * ISA bus support
|
2627 | e6e5ad80 | bellard | *
|
2628 | e6e5ad80 | bellard | ***************************************/
|
2629 | e6e5ad80 | bellard | |
2630 | e6e5ad80 | bellard | void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
2631 | e6e5ad80 | bellard | unsigned long vga_ram_offset, int vga_ram_size) |
2632 | e6e5ad80 | bellard | { |
2633 | e6e5ad80 | bellard | CirrusVGAState *s; |
2634 | e6e5ad80 | bellard | |
2635 | e6e5ad80 | bellard | s = qemu_mallocz(sizeof(CirrusVGAState));
|
2636 | e6e5ad80 | bellard | |
2637 | e6e5ad80 | bellard | vga_common_init((VGAState *)s, |
2638 | e6e5ad80 | bellard | ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
2639 | e6e5ad80 | bellard | cirrus_init_common(s); |
2640 | e6e5ad80 | bellard | s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
|
2641 | e6e5ad80 | bellard | /* XXX ISA-LFB support */
|
2642 | e6e5ad80 | bellard | } |
2643 | e6e5ad80 | bellard | |
2644 | e6e5ad80 | bellard | /***************************************
|
2645 | e6e5ad80 | bellard | *
|
2646 | e6e5ad80 | bellard | * PCI bus support
|
2647 | e6e5ad80 | bellard | *
|
2648 | e6e5ad80 | bellard | ***************************************/
|
2649 | e6e5ad80 | bellard | |
2650 | e6e5ad80 | bellard | static void cirrus_pci_lfb_map(PCIDevice *d, int region_num, |
2651 | e6e5ad80 | bellard | uint32_t addr, uint32_t size, int type)
|
2652 | e6e5ad80 | bellard | { |
2653 | e6e5ad80 | bellard | CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; |
2654 | e6e5ad80 | bellard | |
2655 | e6e5ad80 | bellard | cpu_register_physical_memory(addr, s->vram_size, |
2656 | e6e5ad80 | bellard | s->cirrus_linear_io_addr); |
2657 | e6e5ad80 | bellard | } |
2658 | e6e5ad80 | bellard | |
2659 | e6e5ad80 | bellard | static void cirrus_pci_mmio_map(PCIDevice *d, int region_num, |
2660 | e6e5ad80 | bellard | uint32_t addr, uint32_t size, int type)
|
2661 | e6e5ad80 | bellard | { |
2662 | e6e5ad80 | bellard | CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga; |
2663 | e6e5ad80 | bellard | |
2664 | e6e5ad80 | bellard | cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE, |
2665 | e6e5ad80 | bellard | s->cirrus_mmio_io_addr); |
2666 | e6e5ad80 | bellard | } |
2667 | e6e5ad80 | bellard | |
2668 | e6e5ad80 | bellard | void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
2669 | e6e5ad80 | bellard | unsigned long vga_ram_offset, int vga_ram_size) |
2670 | e6e5ad80 | bellard | { |
2671 | e6e5ad80 | bellard | PCICirrusVGAState *d; |
2672 | e6e5ad80 | bellard | uint8_t *pci_conf; |
2673 | e6e5ad80 | bellard | CirrusVGAState *s; |
2674 | e6e5ad80 | bellard | |
2675 | e6e5ad80 | bellard | /* setup PCI configuration registers */
|
2676 | e6e5ad80 | bellard | d = (PCICirrusVGAState *)pci_register_device("Cirrus VGA",
|
2677 | e6e5ad80 | bellard | sizeof(PCICirrusVGAState),
|
2678 | e6e5ad80 | bellard | 0, -1, NULL, NULL); |
2679 | e6e5ad80 | bellard | pci_conf = d->dev.config; |
2680 | e6e5ad80 | bellard | pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff); |
2681 | e6e5ad80 | bellard | pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8); |
2682 | e6e5ad80 | bellard | pci_conf[0x02] = (uint8_t) (PCI_DEVICE_CLGD5430 & 0xff); |
2683 | e6e5ad80 | bellard | pci_conf[0x03] = (uint8_t) (PCI_DEVICE_CLGD5430 >> 8); |
2684 | e6e5ad80 | bellard | pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
|
2685 | e6e5ad80 | bellard | pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
|
2686 | e6e5ad80 | bellard | pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
|
2687 | e6e5ad80 | bellard | pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
|
2688 | e6e5ad80 | bellard | |
2689 | e6e5ad80 | bellard | /* setup VGA */
|
2690 | e6e5ad80 | bellard | s = &d->cirrus_vga; |
2691 | e6e5ad80 | bellard | vga_common_init((VGAState *)s, |
2692 | e6e5ad80 | bellard | ds, vga_ram_base, vga_ram_offset, vga_ram_size); |
2693 | e6e5ad80 | bellard | cirrus_init_common(s); |
2694 | e6e5ad80 | bellard | s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
|
2695 | e6e5ad80 | bellard | |
2696 | e6e5ad80 | bellard | /* setup memory space */
|
2697 | e6e5ad80 | bellard | /* memory #0 LFB */
|
2698 | e6e5ad80 | bellard | /* memory #1 memory-mapped I/O */
|
2699 | e6e5ad80 | bellard | /* XXX: s->vram_size must be a power of two */
|
2700 | e6e5ad80 | bellard | pci_register_io_region((PCIDevice *)d, 0, s->vram_size,
|
2701 | e6e5ad80 | bellard | PCI_ADDRESS_SPACE_MEM, cirrus_pci_lfb_map); |
2702 | e6e5ad80 | bellard | pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
|
2703 | e6e5ad80 | bellard | PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map); |
2704 | e6e5ad80 | bellard | /* XXX: ROM BIOS */
|
2705 | e6e5ad80 | bellard | } |