Revision e735b55a hw/piix_pci.c
| b/hw/piix_pci.c | ||
|---|---|---|
| 37 | 37 |
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| 38 | 38 |
typedef PCIHostState I440FXState; |
| 39 | 39 |
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
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| 40 | 42 |
typedef struct PIIX3State {
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| 41 | 43 |
PCIDevice dev; |
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int pci_irq_levels[4]; |
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| 43 | 44 |
qemu_irq *pic; |
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/* This member isn't used. Just for save/load compatibility */ |
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; |
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| 44 | 48 |
} PIIX3State; |
| 45 | 49 |
|
| 46 | 50 |
struct PCII440FXState {
|
| ... | ... | |
| 162 | 166 |
i440fx_update_memory_mappings(d); |
| 163 | 167 |
qemu_get_8s(f, &d->smm_enabled); |
| 164 | 168 |
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if (version_id == 2) |
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for (i = 0; i < 4; i++) |
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d->piix3->pci_irq_levels[i] = qemu_get_be32(f); |
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if (version_id == 2) {
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for (i = 0; i < PIIX_NUM_PIRQS; i++) {
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qemu_get_be32(f); /* dummy load for compatibility */ |
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} |
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} |
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return 0; |
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} |
| ... | ... | |
| 236 | 242 |
piix3 = DO_UPCAST(PIIX3State, dev, |
| 237 | 243 |
pci_create_simple_multifunction(b, -1, true, "PIIX3")); |
| 238 | 244 |
piix3->pic = pic; |
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pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
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pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS);
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(*pi440fx_state)->piix3 = piix3; |
| 241 | 247 |
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*piix3_devfn = piix3->dev.devfn; |
| ... | ... | |
| 256 | 262 |
int i, pic_irq, pic_level; |
| 257 | 263 |
PIIX3State *piix3 = opaque; |
| 258 | 264 |
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piix3->pci_irq_levels[irq_num] = level; |
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/* now we change the pic irq level according to the piix irq mappings */ |
| 262 | 266 |
/* XXX: optimize */ |
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pic_irq = piix3->dev.config[0x60 + irq_num]; |
| ... | ... | |
| 266 | 270 |
to it */ |
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pic_level = 0; |
| 268 | 272 |
for (i = 0; i < 4; i++) {
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if (pic_irq == piix3->dev.config[0x60 + i]) |
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pic_level |= piix3->pci_irq_levels[i]; |
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if (pic_irq == piix3->dev.config[0x60 + i]) {
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pic_level |= pci_bus_get_irq_level(piix3->dev.bus, i); |
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} |
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| 271 | 276 |
} |
| 272 | 277 |
qemu_set_irq(piix3->pic[pic_irq], pic_level); |
| 273 | 278 |
} |
| ... | ... | |
| 309 | 314 |
pci_conf[0xab] = 0x00; |
| 310 | 315 |
pci_conf[0xac] = 0x00; |
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pci_conf[0xae] = 0x00; |
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} |
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| 312 | 318 |
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memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels)); |
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static void piix3_pre_save(void *opaque) |
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{
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int i; |
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PIIX3State *piix3 = opaque; |
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for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
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piix3->pci_irq_levels_vmstate[i] = |
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pci_bus_get_irq_level(piix3->dev.bus, i); |
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} |
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| 314 | 328 |
} |
| 315 | 329 |
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static const VMStateDescription vmstate_piix3 = {
|
| ... | ... | |
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.version_id = 3, |
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.minimum_version_id = 2, |
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.minimum_version_id_old = 2, |
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.pre_save = piix3_pre_save, |
|
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.fields = (VMStateField []) {
|
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VMSTATE_PCI_DEVICE(dev, PIIX3State), |
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VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3), |
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VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
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PIIX_NUM_PIRQS, 3), |
|
| 324 | 340 |
VMSTATE_END_OF_LIST() |
| 325 | 341 |
} |
| 326 | 342 |
}; |
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