Revision e737b32a target-i386/op_helper.c
| b/target-i386/op_helper.c | ||
|---|---|---|
| 1919 | 1919 |
ECX = 0; |
| 1920 | 1920 |
EDX = 0x2c307d; |
| 1921 | 1921 |
break; |
| 1922 |
case 4: |
|
| 1923 |
/* cache info: needed for Core compatibility */ |
|
| 1924 |
switch (ECX) {
|
|
| 1925 |
case 0: /* L1 dcache info */ |
|
| 1926 |
EAX = 0x0000121; |
|
| 1927 |
EBX = 0x1c0003f; |
|
| 1928 |
ECX = 0x000003f; |
|
| 1929 |
EDX = 0x0000001; |
|
| 1930 |
break; |
|
| 1931 |
case 1: /* L1 icache info */ |
|
| 1932 |
EAX = 0x0000122; |
|
| 1933 |
EBX = 0x1c0003f; |
|
| 1934 |
ECX = 0x000003f; |
|
| 1935 |
EDX = 0x0000001; |
|
| 1936 |
break; |
|
| 1937 |
case 2: /* L2 cache info */ |
|
| 1938 |
EAX = 0x0000143; |
|
| 1939 |
EBX = 0x3c0003f; |
|
| 1940 |
ECX = 0x0000fff; |
|
| 1941 |
EDX = 0x0000001; |
|
| 1942 |
break; |
|
| 1943 |
default: /* end of info */ |
|
| 1944 |
EAX = 0; |
|
| 1945 |
EBX = 0; |
|
| 1946 |
ECX = 0; |
|
| 1947 |
EDX = 0; |
|
| 1948 |
break; |
|
| 1949 |
} |
|
| 1950 |
|
|
| 1951 |
break; |
|
| 1952 |
case 5: |
|
| 1953 |
/* mwait info: needed for Core compatibility */ |
|
| 1954 |
EAX = 0; /* Smallest monitor-line size in bytes */ |
|
| 1955 |
EBX = 0; /* Largest monitor-line size in bytes */ |
|
| 1956 |
ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; |
|
| 1957 |
EDX = 0; |
|
| 1958 |
break; |
|
| 1922 | 1959 |
case 0x80000000: |
| 1923 | 1960 |
EAX = env->cpuid_xlevel; |
| 1924 | 1961 |
EBX = env->cpuid_vendor1; |
| ... | ... | |
| 3089 | 3126 |
case MSR_VM_HSAVE_PA: |
| 3090 | 3127 |
env->vm_hsave = val; |
| 3091 | 3128 |
break; |
| 3129 |
case MSR_IA32_PERF_STATUS: |
|
| 3130 |
/* tsc_increment_by_tick */ |
|
| 3131 |
val = 1000ULL; |
|
| 3132 |
/* CPU multiplier */ |
|
| 3133 |
val |= (((uint64_t)4ULL) << 40); |
|
| 3134 |
break; |
|
| 3092 | 3135 |
#ifdef TARGET_X86_64 |
| 3093 | 3136 |
case MSR_LSTAR: |
| 3094 | 3137 |
env->lstar = val; |
Also available in: Unified diff